JP5874433B2 - Trace coupling device and program - Google Patents

Description

  The present invention relates to a trace combining device and a program for combining traces of a plurality of processors for evaluating a system in which a plurality of processors are mounted in performance simulation.

  Conventionally, a performance simulator has been used for performance estimation when examining a processor architecture. When a program such as a benchmark test is executed, trace data including all instructions processed by the processor is acquired. Then, the trace data and architecture parameters (cache size, cache protocol, pipeline specifications, etc.) are input to the performance simulator and started, and a performance simulation based on the trace data is executed, and the cache of the evaluation target processor is executed. Outputs performance information such as hit rate and CPI (Clock Per Instruction). Then, the optimum architecture is determined while trying various parameters.

  In recent years, simulations have been performed when a plurality of cores such as multiprocessors and multicores operate simultaneously. When performing simulation of a single core, that is, one CPU (Central Processing Unit), performance simulation can be executed by sequentially inputting one trace data. However, in the case of a multi-core or the like, if the processor is capable of executing instructions in parallel, the trace data may change dynamically as processing proceeds during inter-processor communication, and a simulator for a single processor However, if the simulation is performed by collecting the trace data of each processor each time, there is a problem that the time required for the simulation becomes enormous.

  Based on the execution trace data collected for each processor, the actual processing execution time in the processor is estimated, and the multiprocessing system is simulated using the processing execution time estimated for each processor. It has been proposed to evaluate the performance of multiprocessing systems.

Japanese Patent Laid-Open No. 11-096130

  However, in the above-described prior art, since the processing execution time is estimated for each trace data of each processor, a path for transferring the trace data corresponding to the number of installed processors is required. Therefore, in the performance simulation, there is a problem that the configuration related to the transfer of trace data depends on the number of processors.

  Accordingly, an object of the present invention is to provide a trace combining device and a program for combining traces of a plurality of processors for evaluating a system in which a plurality of processors are mounted in performance simulation.

  In the disclosed technique, a storage unit storing a plurality of trace data corresponding to each of a plurality of processors operating in one system, and one of the plurality of trace data stored in the storage unit is selected in a predetermined order Trace combining processing for combining the traces of the respective processors by reading the instructions traced from the respective trace data one by one, sorting and rearranging them for each synchronous instruction, and adding them to the transfer trace data in the storage unit Configured as a trace coupling device.

  Further, as means for solving the above-mentioned problems, a program for causing a computer to function as the trace coupling device, a recording medium recording the program, and a trace coupling method can be used.

  In the disclosed technique, one transfer trace data in which the plurality of trace data are combined is created by dividing and rearranging the synchronization commands included in the plurality of trace data corresponding to each of the plurality of processors. In the performance simulation, by using the transfer trace data created by separating and rearranging with the synchronous instruction in this way, the instruction after the synchronous instruction is input after all the synchronous instructions to each processor are completed. can do.

It is a figure for demonstrating the basic composition which concerns on a performance simulation. It is a figure which shows the hardware constitutions of the computer apparatus for performing the performance simulator shown in FIG. 1 with software. It is a figure for demonstrating the outline | summary of a function structure of the computer apparatus of FIG. It is a figure which shows the hardware constitutions of the system for implement | achieving the performance simulator shown in FIG. 1 by hardware. FIG. 5 is a diagram for explaining a configuration outline of the system of FIG. 4. It is a figure which shows the structural example for inputting the trace data of multiple cores by one path | route. It is a figure which shows the structural example which rearranges an instruction | indication at the time of transfer. It is a figure which shows the structural example which has the buffer for every core. It is a figure which shows the structural example which rearranges an instruction | indication and produces one trace. It is a figure for demonstrating the execution timing of the command in a real machine. It is a figure for demonstrating the execution timing using the trace data rearranged simply. It is a figure for comparing the shift | offset | difference of execution timing in the case of a performance simulation using a real machine and the rearranged trace data of FIG. It is a figure for demonstrating the execution timing when a synchronous command is included in a program. It is a figure for demonstrating the case where operation | movement of a performance simulator stops. It is a figure for demonstrating the outline | summary of the trace data creation method. It is a figure which shows the example of a function structure for producing the trace data for transfer. It is a flowchart for demonstrating the trace joint process by a trace joint process part. It is a figure for demonstrating the buffer output process in step S17 of FIG. It is a figure which shows the example of the execution timing divided | segmented by the synchronous command. FIG. 20 is a diagram for comparing a difference in execution timing between an actual machine and a performance simulation using the transfer trace data of FIG. 19.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The inventor obtains trace data including a synchronous instruction that causes a decrease in processing performance of performance simulation for evaluating a system in which a plurality of processors (CPU (Central Processing Unit)) such as a multiprocessor and a multicore operate simultaneously. When it was used, the phenomenon that the processing performance deteriorated was analyzed. In this embodiment, generation of trace data that can improve the processing performance even when trace data including a synchronization instruction is used will be described.

  First, a basic configuration related to performance simulation will be described with reference to FIG. In the system 1000 shown in FIG. 1, when the trace data 2 and the architecture setting information 4 are input to the performance simulator 5 and the performance simulator 5 is operated, the performance information report 8 relating to the evaluation target processor is output from the performance simulator 5. Is done.

  The trace data 2 is a data file including instructions 3 in the execution order obtained by executing a program in advance with an actual machine or an ISS (Instruction Set Simulator). The instruction 3 is data indicating a PC (Program Counter), an instruction, an address, and data. The architecture setting information 4 indicates parameters related to an evaluation target processor such as a cache size, a cache protocol, and a pipeline specification.

  The performance simulator 5 simulates the timing of pipelines, memory accesses, etc. without actually executing instructions. The performance simulator 5 is realized by software or hardware as will be described later.

  The performance information report 8 shows performance evaluation results including CPI (Clock per Instruction), cache hit rate, and the like.

  In a system 1000a in which the performance simulator 5 shown in FIG. 1 is realized by software (program), a hardware configuration of a computer device 100a for executing the software is shown in FIG. In the system 1000a shown in FIG. 2, a hardware configuration for the computer apparatus 100a to operate as the performance simulator 5 is shown.

  The computer device 100a includes a CPU 11, a ROM (Read-Only Memory) 12, a RAM (Random Access Memory) 13, a hard disk drive 14, an input device 15, an output device 16, a communication I / F 17, and a drive 18. And they are connected to bus B.

  The CPU 11 controls the computer device 100 a according to a program stored in the ROM 12 or the RAM 13. The ROM 12 and the RAM 13 as main storage devices store programs executed by the CPU 11, data necessary for processing by the CPU 11, data obtained by processing by the CPU 11, and the like. Also, a partial area of the RAM 13 is allocated as a work area used for processing by the CPU 11. The hard disk drive 14 serving as an auxiliary storage device stores data such as programs for executing various processes.

  The storage unit 30 has storage areas such as a ROM 12, a RAM 13, and a hard disk drive 14. The storage unit 30 stores trace data 2, architecture setting information 4, a performance information report 8, and the like.

  The input device 15 includes a mouse, a keyboard, and the like, and is used by a user to input various information necessary for the computer device 100a to perform processing. The output device 16 includes a display device such as an LCD (Liquid Crystal Display) or CRT (Cathode Ray Tube), a printer, and the like, and displays various information necessary under the control of the CPU 11 or / and from the user. Various information is output according to the instructions. The performance information report 8 is displayed or / and output on the output device 16.

  The communication I / F 17 is an interface for connecting to the Internet, a LAN (Local Area Network), etc., for example, and is a device for controlling communication with an external device.

  A program that implements processing performed by the computer apparatus 100a is provided to the computer apparatus 100a by a storage medium 19 such as a CD-ROM (Compact Disc Read-Only Memory). That is, when the storage medium 19 storing the program is set in the drive 18, the drive 18 reads the program from the storage medium 19, and the read program is installed in the hard disk drive 14 via the bus B. When the program is activated, the CPU 11 starts its processing according to the program installed in the hard disk drive 14.

  The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer may be used. As a computer-readable storage medium, in addition to a CD-ROM, a portable recording medium such as a DVD disk or a USB memory, or a semiconductor memory such as a flash memory may be used.

  Further, a program that realizes processing performed by the computer device 100a may be provided from an external device via the communication I / F 17. Alternatively, the program may be provided to an external device, and each process described below may be realized by the external device. Communication by the communication I / F 17 is not limited to wireless or wired.

  FIG. 3 is a diagram for explaining an outline of a functional configuration of the computer apparatus 100a of FIG. In FIG. 3, as an example of a plurality of cores, a case where there are four CPUs is illustrated, but the number is not limited. The same applies to the following drawings.

  In FIG. 3, when CPU 0 to CPU 3 are evaluation targets, trace data 200 to 203 corresponding to each of CPU 0 to CPU 3 are prepared and stored in the storage unit 30. Trace data 200 is trace data for CPU0, trace data 201 is trace data for CPU1, trace data 202 is trace data for CPU2, and trace data 203 is trace data for CPU3.

  The computer apparatus 100a implements the performance simulation unit 50a by the CPU 11 executing a predetermined program. The performance simulation unit 50 a is a processing unit that performs a function corresponding to the performance simulator 5.

  The performance simulation unit 50a includes the CPU0 to CPU3 as CPU models expressed in a hardware description language or the like. In this example, only CPU0 to CPU3 are illustrated as models, but the performance simulation unit 50a includes models such as a memory and a bus.

  When the trace data 200 to 203 is input from the storage unit 30 to the performance simulation unit 50a, the performance simulation unit 50a evaluates the performance of each of the CPU0 to CPU3. A performance information report 8 indicating the result of performance evaluation by the performance simulation unit 50 a is output and stored in the storage unit 30.

  Next, FIG. 4 shows a hardware configuration of a system 1000b in which the performance simulator 5 shown in FIG. 1 is realized by hardware such as a dedicated device. A system 1000b illustrated in FIG. 4 includes a computer device 100b and a performance simulation device 50b. Of the hardware configuration of the computer apparatus 100b shown in FIG. 4, the same reference numerals are given to the same hardware as the computer apparatus 100a shown in FIG. 2, and the description thereof is omitted.

  In contrast to the computer device 100a shown in FIG. 2, the computer device 100b is a host PC (Personal Computer) which is a host device with respect to the performance simulation device 50b, and in addition to the hardware configuration of the computer device 100a, A performance simulation apparatus I / F 20 for connecting and communicating with the performance simulation apparatus 50b is provided.

  Trace data 2, architecture setting information 4 and the like are input from the storage unit 30 of the computer apparatus 100b to the performance simulation apparatus 50b via the performance simulation apparatus I / F 20, and performance evaluation is performed by the performance simulation apparatus 50b.

  The performance information report 8 indicating the result of the performance evaluation executed by the performance simulation device 50b is stored in the storage unit 30 of the computer device 100b via the performance simulation device I / F 20.

  The performance simulation device 50b is a device such as a field-programmable gate array (FPGA), inputs necessary information from the computer device 100b as a host device, evaluates the performance of the evaluation target processor, and shows the result. An information report 8 is output.

  FIG. 5 is a diagram for explaining the outline of the configuration of the system 1000b of FIG. In FIG. 5, the performance simulation apparatus 50b includes a performance simulator 5, an I / F 51b, and an I / F 52b.

  The performance simulator 5 performs a simulation while reading the instruction 3 of the trace data 200 to 203 corresponding to each operation of the CPU0 to CPU3 expressed as a model in the hardware description language.

  The I / F 51b is an interface for receiving each trace data 200 to 203 from the computer device 100b which is a host PC and inputting it to the performance simulator 5. Corresponding CPU0 to CPU3 are simulated in accordance with the trace data 200 to 203 input from the I / F 51b.

  The I / F 52b is an interface for outputting a performance information report 8 indicating the evaluation results of the CPU0 to CPU3 performed by the performance simulator 5 to an external device. When the external device is the computer device 100b, the performance information report 8 is transferred to the computer device 100b via the I / F 52b and stored in the storage unit 30. The performance information report 8 stored in the storage unit 30 is output as a result display to the output device 16 under the control of the CPU 11. Alternatively, when the I / F 52b is connected to an external device for displaying results other than the computer device 100b, the performance information report 8 may be displayed on the external device.

  In such a configuration of the system 1000b, a route to the computer device 100b of the host PC is prepared for each CPU0 to CPU3, and data is transferred independently through each route. Therefore, as the number of cores increases, the resources required for the transfer path such as PCI-Express increase, which increases costs.

  Therefore, it is conceivable to input trace data 200 to 203 corresponding to each of a plurality of cores through one path. FIG. 6 is a diagram illustrating a configuration example for inputting trace data of a plurality of cores through one path.

In the system 1000c shown in FIG. 6, the trace data 200 to 203 corresponding to s husband CPU0~CPU3 corresponding to multiple cores is input to I / F51b on one path. Therefore, the performance simulation device 50b further includes a trace receiving unit 6.

  In the performance simulation device 50b, the trace data 2b is prepared and stored in the storage unit 30. The instruction 3b included in the trace data 2b indicates a CPU number, a PC (Program Counter), an instruction, an address, data, and the like for specifying the CPU0 to CPU3 of the performance simulator 5.

  The trace receiving unit 6 includes a distribution processing unit 6 b and buffers 0 to 3 corresponding to the CPU 0 to CPU 3 of the performance simulator 5. The trace receiving unit 6 receives the trace data 2b transferred serially from the computer device 100b, which is the host PC, and performs a process of writing the command to the CPU buffer corresponding to the CPU number of each command 3b. When the buffer to be written is full, the process waits until the buffer becomes empty without reading the trace data 2b.

  The distribution processing unit 6b stores it in one of the corresponding buffers 0 to 3 based on the CPU number of each instruction 3b input via the I / F 51b. For example, when the CPU number of the instruction 3b specifies CPU0, the instruction 3b is stored in the buffer 0 and given to the CPU0 of the performance simulator 5.

  As a method of transferring the trace data 200 to 203 through one route, a configuration (FIG. 7) for rearranging the instructions 3b of a plurality of cores (CPU0 to CPU3) at the time of transfer and the trace data for each core are stored in advance. A configuration (FIG. 8) having a buffer for storing the data (FIG. 8) and a configuration (FIG. 9) in which the trace data instructions 3b are rearranged between a plurality of cores (CPU0 to CPU3) to create one trace.

  FIG. 7 is a diagram illustrating a configuration example in which instructions are rearranged at the time of transfer. In the configuration illustrated in FIG. 7, the computer device 100 b that is a host PC includes a transfer processing unit 33. The computer apparatus 100b does not rearrange the instructions 3b in advance, and the transfer processing unit 33 responds in units of instructions in response to a request transmitted at the time of fetching instructions of the CPUs 0 to 3 from the performance simulator 5. The instruction 3b is acquired from the trace data to be processed.

  In such a configuration, the performance simulator 5 can be stopped at the same timing as the actual machine by stopping the operation of the performance simulator 5 from when the performance simulator 5 issues a request until there is a response including the instruction 3b. . However, since data is transferred to and from the computer device 100b (host PC) for each instruction, the processing by the transfer processing unit 33 becomes a bottleneck and the execution speed cannot be sufficiently obtained.

  FIG. 8 is a diagram illustrating a configuration example having a buffer for each core. In the configuration shown in FIG. 8, in the performance simulation device 50 b, the trace receiving unit 6 includes buffers 0 to 3 corresponding to the trace size corresponding to the CPUs 0 to 3 of the performance simulator 5.

  The trace data 200 to 203 corresponding to each of the CPUs 0 to 3 are transferred from the computer device 100b (host PC) via the I / F 51b before the operation of the performance simulator 5 is started, and the trace data of the trace receiving unit 6 is buffered. 0 to 3 are stored. However, in this configuration, in general, the size of the trace data often increases (for example, the size in GB units), so it is considered difficult to hold all of the data on the performance simulation device 50b side.

  FIG. 9 is a diagram illustrating a configuration example in which instructions are rearranged to create one trace. In the configuration shown in FIG. 9, before the performance simulator 5 starts its operation, the computer device 100b (host PC) side rearranges the instructions 3b of the CPUs 0 to 3 from the trace data 200 to 203 to form one rearranged trace. Data 210 is prepared in the storage unit 30.

  When the performance simulator 5 is executed, the transfer processing unit 33 of the computer device 100b (host PC) only has to transfer the instruction 3b in order from the top of one rearranged trace data 210, thereby preventing a decrease in transfer speed. it can.

  Next, an example in which instructions 3 of a plurality of cores are simply rearranged with respect to the rearranged trace data 210 will be described. FIG. 10 is a diagram for explaining the instruction execution timing in the actual machine. In FIG. 10, ten instructions are executed in the order of CPUn-0 to CPUn-9 by the four CPUs CPU0 to CPU3, and the position of each instruction indicates the execution timing 9 of the actual machine.

  For example, in the case of CPU0, CPU0-0 instruction in clock cycle 1, CPU0-1 instruction in cycle 3, CPU0-2 instruction in cycle 4, CPU0-3 instruction in cycle 6, and so on. Show. There are various causes of the execution interval being free, such as a cache miss, waiting for data dependency, and branching by a branch instruction.

  Trace data does not have timing information between instructions. On the other hand, at the execution timing 9 of the actual machine, even with the same 10 instructions, the delay of each instruction is different for each core, and the instruction fetch timing is different.

  FIG. 11 illustrates an example of simple rearrangement in which the instructions are fetched one by one (in the direction of the dotted arrow) in the order from the CPU 0 to the CPU 3 in accordance with the execution order. FIG. 11 is a diagram for explaining execution timing using trace data simply rearranged.

  In FIG. 11, when rearranged trace data 210 is used, a delay depending on the order of traces due to rearrangement occurs in addition to the delay at the time of actual instruction execution as shown in FIG. For example, at the execution timing 9 of the actual machine shown in FIG. 10, the CPU2-2 instruction is executed prior to the CPU1-2 instruction, but in FIG. 11, the input trace order is CPU1-2> CPU2- Therefore, the CPU2-2 instruction cannot be input until the CPU1-2 instruction is executed.

  In addition, a delay is added according to the trace order, and an error between the execution timing 9 of the actual machine and the execution timing by the performance simulation increases.

  FIG. 12 is a diagram illustrating a deviation in execution timing between the actual machine and the performance simulation using the rearranged trace data of FIG. In the execution timing comparison between the actual machine and the performance simulator 5, FIG. 12A shows the deviation of the execution timing of the CPU 0, FIG. 12B shows the deviation of the execution timing of the CPU 1, and FIG. FIG. 12D shows a deviation in execution timing of the CPU 3.

  At the time when 10 instructions are completed, in FIG. 12A, the performance simulation of the CPU 0 by the performance simulator 5 ends with a delay of d0 compared to the actual machine. In FIG. 12 (B), the performance simulation of the CPU 1 by the performance simulator 5 is finished with a delay of d1 compared to the actual machine. In FIG. 12 (C), the performance simulation of the CPU 2 by the performance simulator 5 ends with a delay of d2 compared to the actual machine. In FIG. 12 (D), the performance simulation of the CPU 3 by the performance simulator 5 is completed with a delay of d3 compared to the actual machine.

  In this example, the execution timings of each of the CPUs 0 to 3 are shifted, but the performance simulation execution itself has been completed.

  Regarding the above-described shift in execution timing, in the case of a multiprocessor, a synchronization instruction that synchronizes between a plurality of CPUs such as a barrier synchronization instruction is often used. In that case, when the transfer is performed by simple rearrangement, not only the timing is shifted, but also a case where the process stops during the performance simulation occurs. An example thereof will be described with reference to FIG.

  FIG. 13 is a diagram for explaining execution timing when a synchronization instruction is included in a program. In the execution timing shown in FIG. 13, the CPU0-4 instruction, the CPU1-4 instruction, the CPU2-2 instruction, and the CPU3-6 instruction are synchronous instructions. The synchronization instruction needs to be completed simultaneously among a plurality of designated CPUs. That is, the instruction next to the synchronization instruction is executed simultaneously by all the CPUs so as to synchronize. Such synchronization can ensure that the data is correct when data is shared in the same memory area.

  At the execution timing shown in FIG. 13, for example, after the CPU 1 writes data to the shared memory area with the CPU 1-3 instruction and the CPU 0, CPU 2, and CPU 3 have completed writing by the instruction without fail, the CPU 0-5 instruction, CPU 2 In order to read the shared memory area by the -3 instruction and the CPU 3-7 instruction, it is assumed that a synchronization instruction of the CPU 0-4 instruction, the CPU 1-4 instruction, the CPU 2-2 instruction, and the CPU 3-6 instruction is inserted.

  In this example, after execution of CPU1-4 which is the last synchronization instruction, each of CPU0 to CPU3 executes the next instruction CPU0-5, CPU1-5, CPU2-3 and CPU3-7.

  In such a case, in the simple rearrangement method described with reference to FIG. 11, as shown in FIG. 13, the processing of each of the CPUs 0 to 3 is put into a waiting state by the synchronization command, and the operation of the performance simulator 5 is in progress. It may stop.

  FIG. 14 is a diagram for explaining a case where the operation of the performance simulator 5 stops. In FIG. 14, the trace receiving unit of the performance simulation apparatus 50b in the order of rearranged trace data 210, CPU0-0 instruction, CPU1-0 instruction, CPU2-0 instruction, CPU3-0 instruction, CPU0-1 instruction,. 6 and distributed to the corresponding CPU buffer according to the CPU number of each instruction, and then input to the performance simulator 5. In FIG. 14, the buffer size is assumed to be one instruction in order to simplify the description.

  After the CPU2-2 instruction is executed, the next instruction (CPU2-3) is not executed in the CPU2 until all synchronous instructions (CPU0-4 instruction, CPU1-4 instruction, and CPU3-6 instruction) are executed. .

  Since the rearranged trace data 210 is repeatedly arranged one by one in the order of a predetermined CPU, after the CPU2-2 instruction, the CPU3-2 instruction, the CPU0-3 instruction, and the CPU1-3 instruction are sequentially input. When the CPU2-3 instruction enters the buffer 2, the CPU2 waits for the synchronization instructions (CPU0-4 instruction, CPU1-4 instruction, and CPU3-6 instruction) to be executed by the other CPUs 0, 2, and 3. It will be in a waiting state. The CPU 2 stops without performing the instruction fetch.

  Thereafter, after the CPU3-3 instruction, the CPU0-4 instruction, and the CPU1-4 instruction are further input, the CPU2-4 instruction cannot be input to the buffer, and the execution by each of the CPU0 to CPU3 is stopped. The entire simulation process stops.

  As described above, the inventor has analyzed a mechanism in which the performance simulation process stops when the trace data including the synchronization command is simply rearranged and used. And the inventor discovered the trace data creation method which concerns on a present Example demonstrated below.

  A trace data creation method according to the present embodiment will be described. FIG. 15 is a diagram for explaining the outline of the trace data creation method. The trace data creation method is performed by the CPU 11 of the computer apparatus 100a or 100b.

  In FIG. 15, instructions are fetched one by one from the trace data 200 to 203 of the CPUs 0 to 3 in a predetermined order and added to the transfer trace data 300. At this time, if the fetched instruction is a synchronous instruction, the CPU skips without adding the instruction from the trace data of the CPU in which the synchronous instruction appears to the transfer trace data 300, and all the synchronous instructions are transferred to the transfer trace data 300. Are added to the trace data 300 for transfer of instructions after the synchronous instruction from the trace data 200 to 203 in a predetermined order.

  In the example of FIG. 15, the first synchronization instruction CPU 2-2 appears and CPU 0-0 to CPU 3 until all the synchronization instructions CPU 0-4, CPU 1-4, and CPU 3-6 are added to the transfer trace data 300. Up to −6 is a break based on the first synchronization instruction CPU2-2, and is indicated by a break 7 immediately after the last synchronization instruction CPU3-6 corresponding to the synchronization instruction CPU2-2.

  Also, immediately after the last synchronization instruction CPU 3-6, one instruction after the synchronization instruction is taken out from each trace data 200 to 203 in a predetermined order including the skipped instruction, and added to the transfer trace data 300.

  Therefore, in the example of FIG. 15, the instruction of the CPU 2 is not included after the first synchronization instruction CPU2-2 until the synchronization instruction appears in all the other CPUs 1, 3, and 4. When the synchronous instruction CPU0-4 appears after the synchronous instruction CPU2-2, the instruction of the CPU0 is not included until the synchronous instruction appears in the CPUs 1 and 3 other than the CPU2 and CPU0.

  The same applies to CPU1 and CPU3. Then, when the synchronous instruction CPU1-4 and the synchronous instruction CPU3-6 appear, the addition of the instruction to the transfer trace data 300 is resumed in a predetermined order. After the last synchronization instruction CPU3-6, instructions from CPU0-5 to CPU2-9 are added to the transfer trace data 300, so that they are executed after the synchronization instruction.

  By performing such rearrangement every time a synchronous command appears in the trace, it is possible to create transfer trace data 300 that is partitioned by the synchronous command and operates normally without stopping the performance simulation.

  FIG. 16 is a diagram illustrating a functional configuration example for creating transfer trace data. The functional configuration illustrated in FIG. 16 is implemented in the computer device 100a or 100b. The computer apparatus 100 a or 100 b includes the multi-core compatible ISS unit 35 and the trace combination processing unit 36 as processing units for creating the transfer trace data 300. The multi-core compatible ISS unit 35 and the trace combination processing unit 36 are realized by processing by the CPU 11 executing a corresponding program.

  The multi-core compatible ISS unit 35 reads the multi-thread program 34 stored in the storage unit 30 and performs an instruction set level simulation. As a result, trace data TD-1, TD-2, TD-3,..., TD-n are output and stored in the storage unit 30.

  The trace combination processing unit 36 reads instructions one by one from the trace data TD-1, TD-2, TD-3,..., TD-n stored in the storage unit 30 in a predetermined order. One transfer trace data 300 is created and stored in the storage unit 30 by the trace data creation method described above. In order to simplify the processing, the CPU 30 corresponding to the file name of each trace data TD-1, TD-2, TD-3,..., TD-n may be stored in the storage unit 30.

  The trace combination processing by the trace combination processing unit 36 is performed before the performance simulation is executed. As described above, the trace coupling program may be realized by software or hardware so as to be realized by the CPU 11 executing it. The computer devices 100a and 100b may be realized by a different device.

  FIG. 17 is a flowchart for explaining the trace combination processing by the trace combination processing unit. In FIG. 17, the trace combination processing unit 36 reads one instruction 3b in the traced order from the trace data of the CPU number 73 stored in the storage unit 30 according to a predetermined order for selecting trace data (step S11). .

  The predetermined order of selection indicates the order of selecting the trace data when reading the instruction 3b by the CPU number. For example, by including the CPU number in the file name of each trace data, the trace data may be selected according to the CPU number order such as descending order or ascending order. When the predetermined order is the order of CPU0, CPU1, CPU2,..., CPUn (0, 1, 2,..., N), the trace data for CPU0, the trace data for CPU1, and the trace data for CPU2. ... Are selected in the order of trace data for CPUn.

  The trace combination processing unit 36 determines whether or not the read instruction 3b is a synchronous instruction (step S12). If the instruction 3b is a synchronization instruction, a synchronization flag is set in the flag table 71 of the CPU number 73 (step S13), and the instruction 3b is output and stored in the transfer trace data 300 (step S14).

  The flag table 71 is stored in the storage unit 30 and may have at least the number of bits corresponding to the number of cores, for example. The CPU number may be associated with the synchronization flag. The synchronization flag indicates “1” by being set. That is, if the synchronization flag corresponding to the CPU number indicates “1”, it indicates that the read instruction is a synchronization instruction. If the synchronization flag corresponding to the CPU number indicates “0”, it indicates that the synchronization command has not been read yet.

  On the other hand, if it is determined in step S12 that the read instruction is not a synchronous instruction, the trace combination processing unit 36 refers to the flag table 71 stored in the storage unit 30 and sets the synchronization flag of the CPU number 73. It is determined whether it has been performed (step S13-2). If the synchronization flag is set, the read instruction 3b is stored in the synchronization buffer 72 of the CPU number 73 (step S14-2).

  The synchronization buffer 72 is a work buffer area for each CPU number prepared in the storage unit 30. When the instruction 3b indicating the same CPU number as the read synchronization instruction is read from the trace data, it is stored in the synchronization buffer 72 for that CPU number until all synchronization instructions for other CPUs are detected.

  If it is determined in step S13-2 that the synchronization flag is not set, the trace combination processing unit 36 outputs and stores the instruction 3b in the transfer trace data 300 (step S14-4).

  After the processing of steps S14, S14-2, and S14-4, the trace combination processing unit 36 refers to the flag table 71 to determine whether or not the synchronization flag has been set for all the CPUs (step S15). ). When the synchronization flag is set for all the CPUs, the trace combination processing unit 36 clears all the synchronization flags (step S16). All the synchronization flags are set to “0”.

  Then, the trace combination processing unit 36 executes a buffer output process as illustrated in FIG. After executing the buffer output process, the trace combination processing unit 36 proceeds to step S18.

  If it is determined in step S15 that the synchronization flag has not been set for all the CPUs, or if it is determined that there is a CPU for which the synchronization flag has not been set, the trace combination processing unit 36, in a predetermined order, It is determined whether or not the CPU number 73 is the last number (step S18).

  When determining that the CPU number 73 is the last number, the trace combination processing unit 36 initializes the CPU number 73 (step S19), and proceeds to step S20. The CPU number 73 stored in the storage unit 30 is set to “0”. On the other hand, when determining that the CPU number 73 is not the last number, the trace combination processing unit 36 increments the CPU number 73 by 1 (step S19-2), and proceeds to step S20.

  Then, the trace combination processing unit 36 determines whether or not all the traces have been read (step S20). If it is determined that reading of all the traces is incomplete, the trace combination processing unit 36 returns to step S11 and repeats the same processing described above based on the CPU number 73 stored in the storage unit 30.

  On the other hand, if it is determined in step S20 that all the traces have been read, the trace combination processing unit 36 ends this process.

  FIG. 18 is a diagram for explaining the buffer output process in step S17 of FIG. In FIG. 18, the trace combination processing unit 36 initializes the CPU number 73-2 for buffer output processing (step S51), and reads one instruction 3b from the synchronization buffer having the CPU number 73-2 (step S52). .

  The trace combination processing unit 36 outputs the read instruction to the transfer trace data 300 (step S53). The trace combination processing unit 36 determines whether or not the CPU number 73-2 is the last number in a predetermined order (step S54).

  When determining that the CPU number 73-2 is the last number, the trace combination processing unit 36 initializes the CPU number 73-2 (step S55), and proceeds to step S20. The CPU number 73-2 stored in the storage unit 30 is set to “0”. On the other hand, when determining that the CPU number 73-2 is not the last number, the trace combination processing unit 36 increments the CPU number 73-2 by 1 (step S55-2), and proceeds to step S56.

Then, the trace combination processing unit 36 determines whether or not all the synchronization buffers 72 are empty (step S56). When all the synchronization buffers 72 are empty, the trace combination processing unit 36 ends this buffer output processing . If all the synchronization buffers 72 are not empty, the trace combination processing unit 36 returns to step S52 and repeats the same processing as described above.

  The execution timing when the transfer trace data 300 created by the trace combination processing by the trace combination processing unit 36 described above is used will be described with reference to FIGS. 19 and 20, the case where the trace data 300 is used in the configuration example shown in FIG. 6 will be described. Also in the trace data 300, the data structure of the instruction 3b is the same as the instruction 3b of the trace data 2b.

  FIG. 19 is a diagram illustrating an example of execution timing divided by a synchronization instruction. In FIG. 19, when the transfer trace data 300 created by the trace combination processing unit 36 is input to the trace receiving unit 6 of the performance simulation apparatus 50b, the instruction 3b is stored in the buffer corresponding to the CPU number of the instruction 3b. The

  Each of the CPU0 to CPU3 simulated by the performance simulator 5 reads the instruction 3b from the corresponding buffer 0 to buffer 3 and executes it. When the CPU 2 executes the first synchronization instruction CPU2-2, the CPU 2 waits for execution of the synchronization instruction by the other CPUs 0, 1 and 3.

  Next, when the synchronization instruction CPU0-4 is executed by the CPU0, the CPU0 waits for execution of the synchronization instruction by the other CPUs 1 and 3. Further, when the synchronization instruction CPU1-4 is executed by the CPU1, the CPU1 waits for execution of the synchronization instruction by the other CPU3. Finally, when the synchronous instruction CPU 3-6 is executed by the CPU 3, all the synchronous instructions have been executed, and instruction fetches by the CPUs 0 to 3 are executed without delay. The point in time is indicated by a break 7. After the break 7, the instructions 3b traced by the CPUs 0 to 3 are sequentially executed.

  FIG. 20 is a diagram for comparing a difference in execution timing between the actual machine and the performance simulation using the transfer trace data of FIG. In the comparison of execution timing between the actual machine and the performance simulator 5, FIG. 20A shows a shift in the execution timing of CPU0, FIG. 20B shows a shift in the execution timing of CPU1, and FIG. FIG. 20D shows a deviation in the execution timing of the CPU 3.

  At the time when 10 instructions are finished, in FIG. 20A, the performance simulation of the CPU 0 by the performance simulator 5 is finished with a delay of d20 compared to the actual machine. In FIG. 12 (B), the performance simulation of the CPU 1 by the performance simulator 5 is completed with a delay of d21 compared to the actual machine. In FIG. 12C, the performance simulation of the CPU 2 by the performance simulator 5 is completed with a delay of d22 compared to the actual machine. In FIG. 12 (D), the performance simulation of the CPU 3 by the performance simulator 5 is finished with a delay of d23 compared to the actual machine.

  In each of FIG. 20A to FIG. 12D, the performance simulator 5 has a difference of the delay of the break 7b at the execution timing by the performance simulator 5 with respect to the break 7a at the execution timing of the actual machine. However, by using the transfer trace data 300 created by the trace combination processing unit 36, the performance simulation can be executed without stopping midway. Further, the execution timing by the synchronization of all the CPU0 to CPU3 can also be realized as shown in the partition 7b.

  As described above, in the performance evaluation of a system equipped with a plurality of processors (CPUs), one trace data 300 is obtained by rearranging the instructions 3b traced by the plurality of CPUs 0 to CPUn so as to be divided for each synchronization instruction. As a result of the creation, the instruction fetch by each processor after the synchronization instruction is performed without delay even for the trace including the synchronization instruction, so that the performance simulation is executed without stopping midway.

  In this embodiment, transfer trace data for performance simulation for evaluating a system of a plurality of processors is divided into a plurality of traces for each synchronization instruction so that the next instruction is input after all synchronization instructions to the plurality of processors. Create by combining.

  The transfer trace data 300 according to the present embodiment can be applied for performance simulation performed by the configurations of FIGS. 2 and 6 to 9. The computer devices 100a and 100b correspond to a trace coupling device described below.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

The following additional notes are further disclosed with respect to the embodiment including the above examples.
(Appendix 1)
A storage unit storing a plurality of trace data corresponding to each of a plurality of processors operating in one system;
One of the plurality of trace data stored in the storage unit is selected according to a predetermined order, and the instructions traced from each trace data are read one by one and rearranged for each synchronous command, and transferred in the storage unit And a trace combination processing unit for combining the traces of the respective processors by adding to the trace data.
(Appendix 2)
The trace combination processing unit
An instruction reading unit for reading an instruction from the trace data selected according to the predetermined order of the storage unit;
A synchronous instruction determination unit for determining whether or not the instruction read by the instruction reading unit is a synchronous instruction;
An instruction storage unit that stores the instruction in the synchronization buffer associated with the processor in which the instruction is traced when the instruction is not a synchronization instruction by the synchronization instruction determination unit;
When reading of the synchronous instruction from the plurality of trace data corresponding to all the processors is completed, the instruction is read one by one from the synchronization buffer selected according to the predetermined order, and is output to the transfer trace data and added. The trace combining device according to claim 1, further comprising: a buffer output unit configured to perform the above operation.
(Appendix 3)
3. The trace combining device according to claim 2, wherein when the output to the transfer trace data by the buffer output unit is completed, the processing by the instruction reading unit is resumed.
(Appendix 4)
When the synchronous instruction determination unit determines that the instruction is a synchronous instruction, the instruction is traced in a flag table having a synchronization flag corresponding to each of the plurality of processors stored in the storage unit. A flag setting unit for setting the synchronization flag corresponding to the processor;
When the synchronous instruction determination unit determines that the instruction is not a synchronous instruction, it determines whether or not the synchronous flag corresponding to the processor in which the instruction is traced is set by referring to the flag table. A flag determination unit;
The flag non-setting addition unit that outputs and adds the instruction to the transfer trace data when the flag determination unit determines that the synchronization flag is not set. Trace coupling device.
(Appendix 5)
A case wherein the instruction by the synchronization instruction determination unit is determined not to be synchronization command, and, when the synchronization flag by the flag determination unit determines a is configured, the instruction is traced The trace combining device according to claim 4, further comprising an unset instruction storage unit that stores the synchronization buffer in the synchronization buffer corresponding to the processor.
(Appendix 6)
When the synchronization instruction determination unit determines that the instruction is a synchronization instruction, and the flag setting unit sets the synchronization flag corresponding to the processor in which the instruction is traced in the flag table, the instruction 6. The trace combining device according to appendix 4 or 5, further comprising a post-setting instruction storage unit that outputs and stores the data to the transfer trace data.
(Appendix 7)
A trace combining method executed by a computer,
Selecting trace data according to a predetermined order from a plurality of trace data corresponding to each of a plurality of processors operating in one system stored in the storage unit;
The traces of the respective processors are combined by reading the traced instructions from each trace data one by one, sorting them in synchronization instructions and adding them to the trace data for transfer in the storage unit. How to combine traces.
(Appendix 8)
Selecting trace data according to a predetermined order from a plurality of trace data corresponding to each of a plurality of processors operating in one system stored in the storage unit;
The traces of the processors are combined by reading the traced instructions from each trace data one by one and sorting and sorting by each synchronous instruction and adding to the trace data for transfer in the storage unit.
A program that causes a computer to execute processing.
(Appendix 9)
Selecting trace data according to a predetermined order from a plurality of trace data corresponding to each of a plurality of processors operating in one system stored in the storage unit;
The traces of the processors are combined by reading the traced instructions from each trace data one by one and sorting and sorting by each synchronous instruction and adding to the trace data for transfer in the storage unit.
A computer-readable storage medium storing a program for causing a computer to execute processing.

2, 2b Trace data 3, 3b Instruction 4 Architecture setting information 5 Performance simulator 6 Trace reception unit 7, 7a, 7b Delimiter 8 Performance information report 9 Actual machine execution timing 11 CPU
12 ROM
13 RAM
14 hard disk drive 15 input device 16 output device 17 communication I / F
18 drive 19 storage medium 20 performance simulation device I / F
30 storage unit 33 transfer processing unit 34 multi-thread program 35 multi-core compatible ISS unit 36 trace combination processing unit 50a performance simulation unit 50b performance simulation device 51b, 52b I / F
71 Flag table 72 Synchronization buffer 73 CPU number 100a, 100b Computer device 200, 201, 202, 203 Trace data 210 Rearranged trace data 300 Transfer trace data

Claims (5)

A storage unit storing a plurality of trace data corresponding to each of a plurality of processors operating in one system;
Selecting one of the plurality of trace data stored in the storage unit according to a predetermined order, reading one instruction traced from each trace data one by one, rearranging the data by dividing each synchronization instruction, A trace combining device comprising: a trace combination processing unit for combining the traces of the processors by adding to the trace data for transfer. The trace combination processing unit
An instruction reading unit for reading an instruction from the trace data selected according to the predetermined order of the storage unit;
A synchronous instruction determination unit for determining whether or not the instruction read by the instruction reading unit is a synchronous instruction;
When the synchronous instruction determination unit determines that the instruction is a synchronous instruction, the instruction is traced in a flag table having a synchronization flag corresponding to each of the plurality of processors stored in the storage unit. A flag setting unit for setting the synchronization flag corresponding to the processor;
When the synchronous instruction determining unit determines that the instruction is not a synchronous instruction, it is determined whether or not the synchronous flag corresponding to the processor in which the instruction is traced is set by referring to the flag table. A flag determination unit to
When the flag determination unit determines that the synchronization flag is set , an instruction storage unit that stores the instruction in a synchronization buffer corresponding to the processor in which the instruction is traced;
When reading of the synchronous instruction from the plurality of trace data corresponding to all the processors is completed, the instruction is read one by one from the synchronization buffer selected according to the predetermined order, and is output to the transfer trace data and added. 2. The trace combining device according to claim 1, further comprising a buffer output unit.   3. The trace coupling apparatus according to claim 2, wherein when the output to the transfer trace data by the buffer output unit is completed, the processing by the instruction reading unit is resumed. The trace combination processing unit
4. A flag non-setting addition unit that outputs and adds the instruction to the transfer trace data when the flag determination unit determines that the synchronization flag is not set. Trace coupling device. Selecting trace data according to a predetermined order from a plurality of trace data corresponding to each of a plurality of processors operating in one system stored in the storage unit;
The traces of the processors are combined by reading the traced instructions from each trace data one by one and sorting and sorting by each synchronous instruction and adding to the trace data for transfer in the storage unit.
A program that causes a computer to execute processing.

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