WO2017158786A1 - Simulation device, simulation method, and simulation program - Google Patents

Simulation device, simulation method, and simulation program Download PDF

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Publication number
WO2017158786A1
WO2017158786A1 PCT/JP2016/058471 JP2016058471W WO2017158786A1 WO 2017158786 A1 WO2017158786 A1 WO 2017158786A1 JP 2016058471 W JP2016058471 W JP 2016058471W WO 2017158786 A1 WO2017158786 A1 WO 2017158786A1
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simulation
instruction
execution
unit
elements
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PCT/JP2016/058471
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French (fr)
Japanese (ja)
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哲也 武尾
西川　浩司
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三菱電機株式会社
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Priority to PCT/JP2016/058471 priority Critical patent/WO2017158786A1/en
Priority to JP2017546753A priority patent/JP6239212B1/en
Publication of WO2017158786A1 publication Critical patent/WO2017158786A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Definitions

  • the present invention relates to a simulation apparatus, a simulation method, and a simulation program.
  • the ISS is a simulator that converts an instruction set of a target processor into an instruction set of a host processor and executes the converted instruction set.
  • a target processor is a processor of a target machine to be simulated.
  • the host processor is a processor of a host machine that executes simulation.
  • a multi-core processor system is a system in which a plurality of cores are mounted in one processor.
  • a multiprocessor system is a system having a plurality of processors.
  • an independent performance simulator takes charge of the simulation of each processor of the multiprocessor system.
  • the performance simulator alternately executes the simulation of the processor in charge at regular time intervals, and exchanges shared resource occupancy status data with each other, thereby avoiding shared resource occupancy conflicts.
  • FIG. 7 is a timing chart showing instruction execution of actual hardware which is a 2-core multi-core processor.
  • the core X first accesses the shared resource, and then the core Y accesses the shared resource.
  • FIG. 8 is a timing chart showing a simulation of instruction execution of the same multi-core processor as in FIG. 7 using a method of alternately executing simulations of a plurality of cores.
  • the simulation is performed such that the core X and the core Y alternately execute the instruction sequence divided by the specified time, the specified number of instructions, or the appearance of the specified instruction.
  • the core Y accesses the shared resource first, and then the core X accesses the shared resource.
  • the order of access to shared resources may not be the same as that of actual hardware.
  • An object of the present invention is to generate access to shared resources in the same order as actual hardware in simulation.
  • a simulation apparatus includes: The parallel processing operation of a system having a plurality of elements that individually execute program instructions and a shared resource accessed from the plurality of elements is simulated.
  • the simulation apparatus includes: A simulation unit that repeatedly selects one element from the plurality of elements one by one, and simulates execution of an instruction in the selected element; In accordance with the execution of the instruction simulated by the simulation unit, the progress of time in the element selected by the simulation unit is simulated, and the progress of time in the plurality of elements stored in the memory according to the simulation result
  • An interrupting unit that controls the simulation unit so as to simulate the execution of an instruction in another element by interrupting the simulation of the instruction execution in the element selected by the unit.
  • a parallel processing operation of a system having a plurality of elements such as a plurality of cores and a plurality of processors and a shared resource is simulated.
  • simulation of instruction execution with access to a shared resource in one element is started, simulation of instruction execution in that element is interrupted until the time progress of the elements is the same. The execution of instructions in another element is simulated. For this reason, in the simulation, access to the shared resource can occur in the same order as the actual hardware.
  • FIG. 1 is a block diagram illustrating a configuration of a simulation apparatus according to Embodiment 1.
  • FIG. 3 is a block diagram illustrating a configuration of an interruption unit of the simulation apparatus according to the first embodiment.
  • FIG. 3 is a block diagram illustrating a configuration of a detection unit of the simulation apparatus according to the first embodiment.
  • FIG. 3 is a diagram illustrating an example of instruction execution by the simulation apparatus according to the first embodiment.
  • FIG. 3 is a diagram illustrating an example of instruction execution by the simulation apparatus according to the first embodiment.
  • 5 is a flowchart showing the operation of the simulation apparatus according to the first embodiment.
  • a timing chart showing instruction execution of actual hardware which is a two-core multi-core processor.
  • the timing chart showing the simulation of the instruction execution of the same multi-core processor as FIG. 7 using the system which performs the simulation of a some core alternately.
  • Embodiment 1 FIG. *** Explanation of configuration *** The configuration of the simulation apparatus 100 according to the present embodiment will be described with reference to FIG. 1, FIG. 2, and FIG.
  • the simulation apparatus 100 is a computer.
  • the simulation apparatus 100 includes hardware such as a processor 301 and a memory 302.
  • the processor 301 is connected to other hardware via a signal line, and controls these other hardware.
  • the simulation device 100 is a device that simulates the parallel processing operation of a system having a plurality of elements that individually execute program instructions and a shared resource that is accessed from the plurality of elements.
  • the “plural elements” are a plurality of cores of a processor provided in a multi-core processor system. That is, in this embodiment, the simulation apparatus 100 is a host machine, the processor 301 of the simulation apparatus 100 is a host processor, the multicore processor system is a target machine, and the processor of the multicore processor system is a target processor.
  • the number of “elements” may be two or more, but in this embodiment, there are two cores X and Y.
  • the “plurality of elements” may be a plurality of processors of a multiprocessor system.
  • the simulation apparatus 100 includes, as functional elements, a simulation unit 101, a management unit 103, a decoding processing unit 110, a conversion processing unit 111, an execution processing unit 112, an information selection unit 131, a detection unit 201, and an interruption unit. 202.
  • the simulation unit 101 includes a core selection unit 102.
  • the interruption unit 202 includes a previous state holding unit 220 and a previous state restoring unit 221.
  • the detection unit 201 includes a shared resource data restoration unit 222 and an operand address monitoring unit 223. Functions of “units” such as the simulation unit 101, the management unit 103, the decoding processing unit 110, the conversion processing unit 111, the execution processing unit 112, the information selection unit 131, the detection unit 201, and the interruption unit 202 are realized by software.
  • the processor 301 is an IC (Integrated Circuit) that performs processing. Specifically, the processor 301 is a CPU (Central Processing Unit).
  • IC Integrated Circuit
  • CPU Central Processing Unit
  • the memory 302 stores a target instruction code 121, a host instruction code 122, context information X132, context information Y133, and shared resource information 203.
  • the memory 302 is a flash memory or a RAM (Random Access Memory).
  • the simulation apparatus 100 may include additional hardware such as an input device, a display, and a communication device.
  • the input device is specifically a mouse, a keyboard, or a touch panel.
  • the display is specifically an LCD (Liquid Crystal Display).
  • the communication device includes a receiver that receives data and a transmitter that transmits data.
  • the communication device is a communication chip or a NIC (Network Interface Card).
  • the memory 302 stores a program that realizes the function of “unit”. This program is read by the processor 301 and executed by the processor 301.
  • the memory 302 also stores an OS (Operating System).
  • the processor 301 executes a program that realizes the function of “unit” while executing the OS.
  • the program and OS for realizing the function of “unit” may be stored in the auxiliary storage device.
  • the auxiliary storage device is a flash memory or an HDD (Hard Disk Drive).
  • the program and OS stored in the auxiliary storage device are loaded into the memory 302 and executed by the processor 301.
  • the simulation apparatus 100 may include only one processor 301 or may include a plurality of processors 301.
  • a plurality of processors 301 may execute a program that realizes the function of “unit” in cooperation.
  • Information, data, signal values, and variable values indicating the processing results of “unit” are stored in the memory 302, the auxiliary storage device, or a register or cache memory in the processor 301.
  • the program for realizing the function of “unit” may be stored in a portable recording medium such as a magnetic disk or an optical disk.
  • the operation of the simulation apparatus 100 according to the present embodiment will be described with reference to FIGS.
  • the operation of the simulation apparatus 100 corresponds to the simulation method according to the present embodiment.
  • the operation of the simulation apparatus 100 corresponds to the processing procedure of the simulation program according to the present embodiment.
  • the simulation unit 101 has a function corresponding to ISS.
  • the simulation unit 101 manages processing for converting a target instruction code 121 that is an instruction code that can be executed by the target processor into a host instruction code 122 that is an instruction code that can be executed by the host processor.
  • the decode processing unit 110 performs instruction decode processing. Specifically, the decode processing unit 110 confirms whether or not the converted host instruction code 122 exists in the memory 302 for the instruction execution location indicated by the instruction execution address, according to the instruction of the simulation unit 101. When such a host instruction code 122 does not exist, the decode processing unit 110 interprets the type of instruction included in the target instruction code 121 at the corresponding location and the source and destination registers or memory addresses.
  • the conversion processing unit 111 performs instruction conversion processing. Specifically, the conversion processing unit 111 converts the target instruction code 121 interpreted by the decoding processing unit 110 into one or a plurality of host instruction codes 122. The conversion processor 111 stores the converted host instruction code 122 in the memory 302.
  • the execution processing unit 112 performs host instruction code execution processing. Specifically, the execution processing unit 112 executes the host instruction code 122 corresponding to the target instruction code 121 to be executed among the converted host instruction codes 122 stored in the memory 302 by the conversion processing unit 111. , Do a simulation.
  • the decode processing unit 110 searches the memory 302. If the corresponding host instruction code 122 is stored, the simulation unit 101 does not issue an instruction decode processing instruction to the decode processing unit 110 and an instruction conversion processing instruction to the conversion processing unit 111, and executes the execution processing unit 112. The host instruction code execution processing instruction is issued. Thus, the simulation can be speeded up by omitting the instruction decoding process and the instruction converting process and performing only the host instruction code execution process.
  • Context information X132 and context information Y133 are context information for executing a simulation of a multi-core processor system having two cores, core X and core Y. By preparing the context information for the number of cores, it is possible to deal with an arbitrary number of cores.
  • the core selection unit 102 determines whether the target instruction code 121 to be executed next is the instruction code of the core X or the instruction code of the core Y.
  • the core selection unit 102 transmits context information to be selected to the information selection unit 131 according to the determination result.
  • the context information X132 and the context information Y133 are information necessary when the core X and the core Y of the target processor execute the target instruction code 121, respectively.
  • the context information X132 and the context information Y133 include information on internal registers of the target processor, information on instruction execution addresses held in each core, information on time, information on interrupts, and other information on resources.
  • the information selection unit 131 When the target instruction code 121 to be executed next is the instruction code of the core X, the information selection unit 131 reads the context information X132, and when the target instruction code 121 to be executed next is the instruction code of the core Y Reads the context information Y133. The information selection unit 131 provides the read context information as resource information used in the host instruction code execution process of the execution processing unit 112.
  • the management unit 103 simulates the time progress of the target processor in accordance with the execution of the host instruction code 122. Each time one host instruction code 122 is executed, the management unit 103 calculates the time required for executing the instruction and the time required for memory access, I / O access, and the like, and prepares a calculation result for each core. Is reflected in the context information X132 and the context information Y133. The time information of each core is synchronized at regular intervals. The time information of each core can be used as performance information together with the instruction execution status.
  • the order of access to shared resources among multiple cores cannot be controlled, so that the actual hardware operation cannot be accurately reproduced. If the goal is simply to simulate software functions without considering performance analysis, the software has exclusive control for accessing shared resources without having to accurately simulate the order of access to shared resources. It only needs to have a function. However, when performing performance simulation for analyzing performance, it is necessary to accurately simulate the order of access to shared resources.
  • the simulation apparatus 100 includes an interruption unit 202 that interrupts instruction execution when access to a shared resource occurs. Therefore, synchronization between a plurality of cores becomes possible at the time of access to the shared resource, and the order of access to the shared resource between the plurality of cores can be controlled.
  • the simulation apparatus 100 further includes a detection unit 201 that detects that access to the shared resource has occurred on the simulation when the host instruction code 122 is being executed.
  • the memory 302 stores shared resource information 203 indicating the address range of the shared resource area.
  • the detection unit 201 detects the occurrence of access to the shared resource based on the shared resource information 203 and the operand address of the instruction executed by the execution processing unit 112.
  • the interruption unit 202 interrupts instruction execution upon receiving notification from the detection unit 201 that occurrence of access to the shared resource has been detected.
  • the previous state holding unit 220 receives context information at the time of instruction execution from the simulation unit 101.
  • the immediately preceding state holding unit 220 holds the received context information until after the next instruction is executed.
  • the previous state holding unit 220 replaces the held context information with the context information at the time of execution of the previous instruction when the next instruction is executed.
  • the immediately preceding state restoring unit 221 When the immediately preceding state restoring unit 221 receives a notification from the detecting unit 201 that the occurrence of access to the shared resource has been detected, the immediately preceding state restoring unit 221 instructs the simulating unit 101 to suspend instruction execution, and the context information of the simulating unit 101 is immediately before The context information stored in the state storage unit 220 is restored. Thereby, the state of the simulation unit 101 can be returned to the state immediately before the access to the shared resource occurs.
  • the operand address monitoring unit 223 receives the operand address information of the instruction being executed from the execution processing unit 112, and if the address area is a shared resource area, that is, the address is indicated by the shared resource information 203. If it is within the specified address range, a notification is sent to the interruption unit 202.
  • the shared resource data restoration unit 222 restores the state before the data transfer generated by the instruction when the instruction executed by the execution processing unit 112 is an instruction accompanied by access to the shared resource.
  • FIGS. 4 and 5 show the instruction code string of the target processor in the order of execution, and the contents held in the immediately preceding state holding unit 220 when each instruction is executed are shown corresponding to each instruction.
  • the instruction sequence of the target processor is converted into the instruction sequence of the host processor. For simplicity, the operation will be described using the instruction sequence of the target processor.
  • the instructions are executed in order from the instruction a1, and the instruction string is delimited by the Load / Store instruction a10. That is, an instruction sequence starting with the instruction a1 and ending with the Load / Store instruction a10 is configured.
  • the instruction a11 to instruction a16 are the next delimited instruction sequence. That is, the instruction sequence starting with the instruction a11 and ending with the instruction a16 is formed next.
  • the content held by the immediately previous state holding unit 220 when the instruction a3 is executed is the state after the execution of the instruction a2.
  • the content held in the immediately preceding state holding unit 220 when the Load / Store instruction a10 is executed is the state after the execution of the immediately preceding instruction a5. If this Load / Store instruction a10 is not an instruction that causes access to a shared resource, the instruction sequence from the next instruction a11 is executed as it is.
  • the Load / Store instruction a10 is an access to a shared resource, instruction execution is interrupted and synchronization between cores is performed as in the example of FIG.
  • the Load / Store instruction a10 is an instruction that causes access to the shared resource
  • the instruction execution is interrupted, and the state after execution of the immediately preceding instruction a5 is restored by the immediately preceding state restoring unit 221.
  • the cores are synchronized, and the instruction execution is resumed when the instruction execution is interrupted in the core where the instruction execution is interrupted later than the other cores. If there is a core whose instruction execution is delayed in another core, the instruction of the delayed core is executed.
  • the execution of instructions that cause access to shared resources is delayed most recently, and instruction execution is resumed, and access to shared resources occurs. The order of access will be guaranteed.
  • FIG. 6 shows an operation flow of the simulation apparatus 100.
  • step S11 the core selection unit 102, which is a component of the simulation unit 101, selects the core that executes the instruction next.
  • the core that executes the instruction next may be arbitrary. If there is a difference in instruction execution status between cores, that is, if the time of one of the cores precedes, the core with the later time is selected.
  • step S12 the information selection unit 131 selects the context information of the core selected in step S11 as reference information at the time of instruction execution.
  • the instruction execution address indicating the target instruction code 121 to be executed next by the core selected in step S11 is held in the context information X132 or the context information Y133. If the target instruction code 121 of the instruction execution address has been converted to the host instruction code 122, the process of step S17 is performed. On the other hand, if the target instruction code 121 of the instruction execution address has not been converted to the host instruction code 122, the process of step S13 is performed.
  • step S13 the decode processing unit 110 reads the target instruction code 121 of the instruction execution address.
  • step S14 the decode processing unit 110 decodes the target instruction code 121 read in step S14.
  • step S15 the conversion processing unit 111 converts the target instruction code 121 into the host instruction code 122 according to the information decoded in step S15.
  • the host instruction code 122 is an instruction sequence including one or more instructions.
  • the conversion processor 111 embeds information related to internal resources such as registers in the host instruction code 122 with reference to the context information selected in step S12.
  • step S16 the conversion processing unit 111 stores the host instruction code 122 obtained in step S15 in the memory 302 as one block.
  • step S16 it is determined whether synchronization between cores is necessary. If the host instruction code 122 stored in step S16 is one of a synchronization instruction, a branch instruction, and an instruction that may cause access to a shared resource, synchronization is necessary, and either For example, no synchronization is necessary. If synchronization is not necessary, the processing from step S13 to step S16 is repeated and the target instruction code 121 is converted. If synchronization is required, the conversion of the target instruction code 121 is interrupted, and the storage of the block of the host instruction code 122 at that time is completed. Then, the process of step S17 is performed.
  • step S17 the immediately preceding state holding unit 220, which is a component of the interrupting unit 202, stores the context information selected in step S12 as the state after execution of the immediately preceding instruction.
  • step S18 the execution processing unit 112 executes the host instruction code 122 corresponding to one target instruction code 121.
  • step S19 the immediately preceding state restoring unit 221 that is a component of the interrupting unit 202 restores the state after the previous instruction execution saved in step S17.
  • step S20 it is determined whether execution of one block of the host instruction code 122 is completed. If the host instruction code 122 is not an instruction that causes access to the shared resource in step S18, it is also determined whether execution of one block of the host instruction code 122 is completed. If not completed, the processing after step S17 is repeated and the execution of the host instruction code 122 is continued. If completed, the process of step S20 is performed.
  • step S20 synchronization between cores is performed. That is, when there is no difference in the instruction execution status between the cores, the process of step S11 is performed again, and an arbitrary core is selected. If there is a difference in instruction execution status between the cores, the core whose time is delayed is selected in step S11.
  • An instruction that causes shared resource access is stored at the end of one block of the host instruction code 122 because it needs to be synchronized. Therefore, after an instruction that causes shared resource access is executed in step S18 and the state after execution of the previous instruction is restored in step S19, it is determined that execution of one block is completed, and in step S20 Synchronization between cores is performed.
  • the simulation unit 101 repeatedly selects a core from a plurality of cores one by one, and simulates execution of an instruction in the selected core.
  • the management unit 103 simulates the progress of time in the core selected by the simulation unit 101 in accordance with the execution of the command simulated by the simulation unit 101.
  • the management unit 103 updates the time information of the core selected by the simulation unit 101 according to the simulation result.
  • the time information is information indicating the degree of time progress in a plurality of cores.
  • the time information is created individually for each core.
  • the time information is stored in the memory 302 as part of the context information.
  • the interruption unit 202 continues until the time progress in the plurality of cores indicated by the time information stored in the memory 302 becomes the same.
  • the simulation unit 101 is controlled so as to simulate the execution of the instruction in another core by interrupting the simulation of the instruction execution in the core selected by the simulation unit 101.
  • the detection unit 201 is designated by referring to the shared resource information 203 when the simulation unit 101 starts simulating the execution of an instruction to transfer data by specifying a transfer destination address. The address indicated by the referenced shared resource information 203 is compared. The detection unit 201 detects that the simulation of execution of an instruction involving access to the shared resource is started by the simulation unit 101 according to the comparison result, and sends a notification to the interruption unit 202. Upon receiving this notification, the interrupting unit 202 can recognize that the simulation unit 101 has started to simulate the execution of an instruction that accompanies access to the shared resource.
  • the simulation unit 101 updates the context information of the selected core according to the simulation result every time the execution of the instruction in the selected core is simulated.
  • the context information is information indicating the execution status of instructions in a plurality of cores.
  • the context information is created individually for each core.
  • the interruption unit 202 acquires the context information before the simulation of the execution of the next instruction by the simulation unit 101 from the memory 302 as the immediately preceding context information. To do.
  • the interruption unit 202 causes the simulation unit 101 to suspend the execution of the next instruction and
  • the context information stored in 302 is replaced with the previous context information.
  • the parallel processing operation of a system having a plurality of cores and shared resources is simulated.
  • simulation of instruction execution with access to a shared resource in one core is started, simulation of instruction execution in that core is suspended until the time progress in the multiple cores is the same.
  • the execution of instructions in another core is simulated. For this reason, in the simulation, access to the shared resource can occur in the same order as the actual hardware.
  • the same effect can be obtained when a plurality of cores are replaced with a plurality of processors.
  • the function of “unit” is realized by software.
  • the function of “unit” may be realized by a combination of software and hardware.
  • one or several “unit” functions may be realized by a processing circuit, and the remaining functions may be realized by software.
  • the processing circuit is a single circuit, a composite circuit, a programmed processor, a processor programmed in parallel, a logic IC, a GA (Gate Array), or an FPGA (Field-Programmable Gate Array).
  • the processing circuit is specifically an ASIC (Application Specific Integrated Circuit).
  • the processor 301, the memory 302, and the processing circuit are collectively referred to as “processing circuit”. That is, the function of “unit” is realized by a processing circuit regardless of whether it is realized by software or a combination of software and hardware.
  • Part may be read as “Process”, “Procedure” or “Process”.
  • 100 simulation device 101 simulation unit, 102 core selection unit, 103 management unit, 110 decode processing unit, 111 conversion processing unit, 112 execution processing unit, 121 target instruction code, 122 host instruction code, 131 information selection unit, 132 context information X, 133 Context information Y, 201 Detection unit, 202 Interruption unit, 203 Shared resource information, 220 Immediate state holding unit, 221 Immediate state restoration unit, 222 Shared resource data restoration unit, 223 Operand address monitoring unit, 301 processor, 302 memory .

Abstract

In this simulation device (100), a simulation unit (101) repeatedly selects cores one at a time from a plurality of cores and simulates instruction execution performed by each selected core. A management unit (103) simulates the progression of time in each core selected by the simulation unit (101), in accordance with the instruction execution simulated by the simulation unit (101), and updates time information about each core selected by the simulation unit (101), on the basis of the results of the simulated progression of time in the core. When the simulation unit (101) has initiated simulation of instruction execution requiring access to a shared resource, an interruption unit (202) controls the simulation unit (101) to stop and refrain from simulating any instruction execution performed by the core currently selected by the simulation unit (101), and to simulate instruction execution performed by other cores instead, until the degrees of progress of time in the plurality of cores, as indicated by the time information about these cores, become equal.

Description

シミュレーション装置、シミュレーション方法及びシミュレーションプログラムSimulation device, simulation method, and simulation program
　本発明は、シミュレーション装置、シミュレーション方法及びシミュレーションプログラムに関するものである。 The present invention relates to a simulation apparatus, a simulation method, and a simulation program.
　近年では、ＩＳＳ（Ｉｎｓｔｒｕｃｔｉｏｎ　Ｓｅｔ　Ｓｉｍｕｌａｔｏｒ）を用いることで実際のハードウェアの作成前にソフトウェアのデバッグが可能となっている。ＩＳＳは、ターゲットプロセッサの命令セットをホストプロセッサの命令セットに変換し、変換後の命令セットを実行するシミュレータである。ターゲットプロセッサとは、シミュレーションの対象となるターゲットマシンのプロセッサのことである。ホストプロセッサとは、シミュレーションを実行するホストマシンのプロセッサのことである。 In recent years, it has become possible to debug software before creating actual hardware by using an ISS (Instruction Set Simulator). The ISS is a simulator that converts an instruction set of a target processor into an instruction set of a host processor and executes the converted instruction set. A target processor is a processor of a target machine to be simulated. The host processor is a processor of a host machine that executes simulation.
　マルチコアプロセッサシステム及びマルチプロセッサシステムのシミュレーションも可能になってきている。マルチコアプロセッサシステムとは、１つのプロセッサの中に複数のコアが実装されているシステムのことである。マルチプロセッサシステムとは、複数のプロセッサを持つシステムのことである。 Multi-core processor systems and multi-processor system simulations are also becoming possible. A multi-core processor system is a system in which a plurality of cores are mounted in one processor. A multiprocessor system is a system having a plurality of processors.
　特許文献１に記載の技術では、マルチプロセッサシステムの各プロセッサのシミュレーションを独立の性能シミュレータが担当する。性能シミュレータは、担当のプロセッサのシミュレーションを規定時間ごとに交互に実行し、かつ、共有リソースの占有状況データを互いにやり取りすることで、共有リソースの占有の衝突を回避する。 In the technology described in Patent Document 1, an independent performance simulator takes charge of the simulation of each processor of the multiprocessor system. The performance simulator alternately executes the simulation of the processor in charge at regular time intervals, and exchanges shared resource occupancy status data with each other, thereby avoiding shared resource occupancy conflicts.
特開平１１－２９６４０９号公報Japanese Patent Laid-Open No. 11-296409
　特許文献１に記載の技術では、複数のプロセッサのシミュレーションを規定時間ごとに交互に実行するため、複数のプロセッサが実際のハードウェアと同じ順序で共有リソースにアクセスするようにシミュレーションを行うことが困難である。複数のプロセッサを複数のコアに置き換えた場合も同じである。以下に具体例を示す。 In the technique described in Patent Document 1, since simulation of a plurality of processors is alternately executed at a predetermined time, it is difficult to perform simulation so that the plurality of processors access shared resources in the same order as actual hardware. It is. The same is true when multiple processors are replaced with multiple cores. Specific examples are shown below.
　図７は、２コアのマルチコアプロセッサである実際のハードウェアの命令実行を表したタイミングチャートである。この例では、先にコアＸが共有リソースにアクセスし、その後にコアＹが共有リソースにアクセスしている。 FIG. 7 is a timing chart showing instruction execution of actual hardware which is a 2-core multi-core processor. In this example, the core X first accesses the shared resource, and then the core Y accesses the shared resource.
　図８は、複数のコアのシミュレーションを交互に実行する方式を用いた、図７と同じマルチコアプロセッサの命令実行のシミュレーションを表したタイミングチャートである。この例では、規定時間、規定命令数、又は、規定命令の出現によって区切られた命令列をコアＸ及びコアＹが交互に実行するようにシミュレーションが行われている。図８では、図７の順序とは異なり、先にコアＹが共有リソースにアクセスし、その後にコアＸが共有リソースにアクセスしている。 FIG. 8 is a timing chart showing a simulation of instruction execution of the same multi-core processor as in FIG. 7 using a method of alternately executing simulations of a plurality of cores. In this example, the simulation is performed such that the core X and the core Y alternately execute the instruction sequence divided by the specified time, the specified number of instructions, or the appearance of the specified instruction. In FIG. 8, unlike the order of FIG. 7, the core Y accesses the shared resource first, and then the core X accesses the shared resource.
　このように、複数のプロセッサ又はコアのシミュレーションを交互に実行する方式では、共有リソースへのアクセスの順序が実際のハードウェアと同じ順序にならないことがある。 As described above, in the method of alternately executing simulations of a plurality of processors or cores, the order of access to shared resources may not be the same as that of actual hardware.
　本発明は、シミュレーションにおいて、共有リソースへのアクセスを実際のハードウェアと同じ順序で発生させることを目的とする。 An object of the present invention is to generate access to shared resources in the same order as actual hardware in simulation.
　本発明の一態様に係るシミュレーション装置は、
　プログラムの命令を個別に実行する複数の要素と前記複数の要素からアクセスされる共有リソースとを有するシステムの並列処理の動作を模擬する。
　前記シミュレーション装置は、
　前記複数の要素の中から要素を１つずつ繰り返し選択し、選択した要素における命令の実行を模擬する模擬部と、
　前記模擬部により模擬された命令の実行に合わせて、前記模擬部により選択された要素における時間の進行を模擬し、模擬の結果に応じて、メモリに格納され前記複数の要素における時間の進行度を示す時間情報を更新する管理部と、
　前記模擬部により前記共有リソースへのアクセスを伴う命令の実行の模擬が開始された場合、前記メモリに格納された時間情報が示す前記複数の要素における時間の進行度が同じになるまで、前記模擬部により選択された要素における命令の実行の模擬を中断して別の要素における命令の実行を模擬するよう前記模擬部を制御する中断部とを備える。 A simulation apparatus according to one embodiment of the present invention includes:
The parallel processing operation of a system having a plurality of elements that individually execute program instructions and a shared resource accessed from the plurality of elements is simulated.
The simulation apparatus includes:
A simulation unit that repeatedly selects one element from the plurality of elements one by one, and simulates execution of an instruction in the selected element;
In accordance with the execution of the instruction simulated by the simulation unit, the progress of time in the element selected by the simulation unit is simulated, and the progress of time in the plurality of elements stored in the memory according to the simulation result A management unit for updating the time information indicating
When the simulation unit starts simulating the execution of an instruction involving access to the shared resource, the simulation is performed until the time progress in the plurality of elements indicated by the time information stored in the memory becomes the same. An interrupting unit that controls the simulation unit so as to simulate the execution of an instruction in another element by interrupting the simulation of the instruction execution in the element selected by the unit.
　本発明では、複数のコア、複数のプロセッサといった複数の要素と、共有リソースとを有するシステムの並列処理の動作が模擬される。１つの要素における、共有リソースへのアクセスを伴う命令の実行の模擬が開始された場合、複数の要素における時間の進行度が同じになるまで、当該１つの要素における命令の実行の模擬が中断され、別の要素における命令の実行が模擬される。このため、シミュレーションにおいて、共有リソースへのアクセスを実際のハードウェアと同じ順序で発生させることができる。 In the present invention, a parallel processing operation of a system having a plurality of elements such as a plurality of cores and a plurality of processors and a shared resource is simulated. When simulation of instruction execution with access to a shared resource in one element is started, simulation of instruction execution in that element is interrupted until the time progress of the elements is the same. The execution of instructions in another element is simulated. For this reason, in the simulation, access to the shared resource can occur in the same order as the actual hardware.
実施の形態１に係るシミュレーション装置の構成を示すブロック図。1 is a block diagram illustrating a configuration of a simulation apparatus according to Embodiment 1. FIG. 実施の形態１に係るシミュレーション装置の中断部の構成を示すブロック図。FIG. 3 is a block diagram illustrating a configuration of an interruption unit of the simulation apparatus according to the first embodiment. 実施の形態１に係るシミュレーション装置の検出部の構成を示すブロック図。FIG. 3 is a block diagram illustrating a configuration of a detection unit of the simulation apparatus according to the first embodiment. 実施の形態１に係るシミュレーション装置による命令実行の例を示す図。FIG. 3 is a diagram illustrating an example of instruction execution by the simulation apparatus according to the first embodiment. 実施の形態１に係るシミュレーション装置による命令実行の例を示す図。FIG. 3 is a diagram illustrating an example of instruction execution by the simulation apparatus according to the first embodiment. 実施の形態１に係るシミュレーション装置の動作を示すフローチャート。5 is a flowchart showing the operation of the simulation apparatus according to the first embodiment. ２コアのマルチコアプロセッサである実際のハードウェアの命令実行を表したタイミングチャート。A timing chart showing instruction execution of actual hardware which is a two-core multi-core processor. 複数のコアのシミュレーションを交互に実行する方式を用いた、図７と同じマルチコアプロセッサの命令実行のシミュレーションを表したタイミングチャート。The timing chart showing the simulation of the instruction execution of the same multi-core processor as FIG. 7 using the system which performs the simulation of a some core alternately.
　以下、本発明の実施の形態について、図を用いて説明する。なお、各図中、同一又は相当する部分には、同一符号を付している。実施の形態の説明において、同一又は相当する部分については、その説明を適宜省略又は簡略化する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the part which is the same or it corresponds in each figure. In the description of the embodiments, the description of the same or corresponding parts will be omitted or simplified as appropriate.
　実施の形態１．
　＊＊＊構成の説明＊＊＊
　図１、図２及び図３を参照して、本実施の形態に係るシミュレーション装置１００の構成を説明する。 Embodiment 1 FIG.
*** Explanation of configuration ***
The configuration of the simulation apparatus 100 according to the present embodiment will be described with reference to FIG. 1, FIG. 2, and FIG.
　シミュレーション装置１００は、コンピュータである。シミュレーション装置１００は、プロセッサ３０１、メモリ３０２といったハードウェアを備える。プロセッサ３０１は、信号線を介して他のハードウェアと接続され、これら他のハードウェアを制御する。 The simulation apparatus 100 is a computer. The simulation apparatus 100 includes hardware such as a processor 301 and a memory 302. The processor 301 is connected to other hardware via a signal line, and controls these other hardware.
　シミュレーション装置１００は、プログラムの命令を個別に実行する複数の要素と複数の要素からアクセスされる共有リソースとを有するシステムの並列処理の動作を模擬する装置である。本実施の形態において、「複数の要素」は、マルチコアプロセッサシステムに備えられたプロセッサの複数のコアである。すなわち、本実施の形態では、シミュレーション装置１００がホストマシンであり、シミュレーション装置１００のプロセッサ３０１がホストプロセッサであり、マルチコアプロセッサシステムがターゲットマシンであり、マルチコアプロセッサシステムのプロセッサがターゲットプロセッサである。「要素」の数は、２つ以上であればよいが、本実施の形態ではコアＸ及びコアＹの２つである。なお、「複数の要素」は、マルチプロセッサシステムの複数のプロセッサであってもよい。 The simulation device 100 is a device that simulates the parallel processing operation of a system having a plurality of elements that individually execute program instructions and a shared resource that is accessed from the plurality of elements. In the present embodiment, the “plural elements” are a plurality of cores of a processor provided in a multi-core processor system. That is, in this embodiment, the simulation apparatus 100 is a host machine, the processor 301 of the simulation apparatus 100 is a host processor, the multicore processor system is a target machine, and the processor of the multicore processor system is a target processor. The number of “elements” may be two or more, but in this embodiment, there are two cores X and Y. The “plurality of elements” may be a plurality of processors of a multiprocessor system.
　シミュレーション装置１００は、機能要素として、模擬部１０１と、管理部１０３と、デコード処理部１１０と、変換処理部１１１と、実行処理部１１２と、情報選択部１３１と、検出部２０１と、中断部２０２とを備える。模擬部１０１は、コア選択部１０２を有する。中断部２０２は、直前状態保持部２２０と、直前状態復元部２２１とを有する。検出部２０１は、共有リソースデータ復元部２２２と、オペランドアドレス監視部２２３とを有する。模擬部１０１、管理部１０３、デコード処理部１１０、変換処理部１１１、実行処理部１１２、情報選択部１３１、検出部２０１、中断部２０２といった「部」の機能は、ソフトウェアにより実現される。 The simulation apparatus 100 includes, as functional elements, a simulation unit 101, a management unit 103, a decoding processing unit 110, a conversion processing unit 111, an execution processing unit 112, an information selection unit 131, a detection unit 201, and an interruption unit. 202. The simulation unit 101 includes a core selection unit 102. The interruption unit 202 includes a previous state holding unit 220 and a previous state restoring unit 221. The detection unit 201 includes a shared resource data restoration unit 222 and an operand address monitoring unit 223. Functions of “units” such as the simulation unit 101, the management unit 103, the decoding processing unit 110, the conversion processing unit 111, the execution processing unit 112, the information selection unit 131, the detection unit 201, and the interruption unit 202 are realized by software.
　プロセッサ３０１は、プロセッシングを行うＩＣ（Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）である。プロセッサ３０１は、具体的には、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）である。 The processor 301 is an IC (Integrated Circuit) that performs processing. Specifically, the processor 301 is a CPU (Central Processing Unit).
　メモリ３０２には、ターゲット命令コード１２１と、ホスト命令コード１２２と、コンテキスト情報Ｘ１３２と、コンテキスト情報Ｙ１３３と、共有リソース情報２０３とが格納される。メモリ３０２は、具体的には、フラッシュメモリ、又は、ＲＡＭ（Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）である。 The memory 302 stores a target instruction code 121, a host instruction code 122, context information X132, context information Y133, and shared resource information 203. Specifically, the memory 302 is a flash memory or a RAM (Random Access Memory).
　シミュレーション装置１００は、入力装置、ディスプレイ、通信装置といった追加のハードウェアを備えていてもよい。 The simulation apparatus 100 may include additional hardware such as an input device, a display, and a communication device.
　入力装置は、具体的には、マウス、キーボード、又は、タッチパネルである。 The input device is specifically a mouse, a keyboard, or a touch panel.
　ディスプレイは、具体的には、ＬＣＤ（Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ　Ｄｉｓｐｌａｙ）である。 The display is specifically an LCD (Liquid Crystal Display).
　通信装置は、データを受信するレシーバ及びデータを送信するトランスミッタを含む。通信装置は、具体的には、通信チップ又はＮＩＣ（Ｎｅｔｗｏｒｋ　Ｉｎｔｅｒｆａｃｅ　Ｃａｒｄ）である。 The communication device includes a receiver that receives data and a transmitter that transmits data. Specifically, the communication device is a communication chip or a NIC (Network Interface Card).
　メモリ３０２には、「部」の機能を実現するプログラムが記憶されている。このプログラムは、プロセッサ３０１に読み込まれ、プロセッサ３０１によって実行される。メモリ３０２には、ＯＳ（Ｏｐｅｒａｔｉｎｇ　Ｓｙｓｔｅｍ）も記憶されている。プロセッサ３０１はＯＳを実行しながら、「部」の機能を実現するプログラムを実行する。 The memory 302 stores a program that realizes the function of “unit”. This program is read by the processor 301 and executed by the processor 301. The memory 302 also stores an OS (Operating System). The processor 301 executes a program that realizes the function of “unit” while executing the OS.
　「部」の機能を実現するプログラムの全体又は一部がＯＳに組み込まれていてもよい。 The whole or part of the program that realizes the function of “part” may be incorporated in the OS.
　「部」の機能を実現するプログラム及びＯＳは、補助記憶装置に記憶されていてもよい。補助記憶装置は、具体的には、フラッシュメモリ、又は、ＨＤＤ（Ｈａｒｄ　Ｄｉｓｋ　Ｄｒｉｖｅ）である。補助記憶装置に記憶されているプログラム及びＯＳは、メモリ３０２にロードされ、プロセッサ３０１によって実行される。 The program and OS for realizing the function of “unit” may be stored in the auxiliary storage device. Specifically, the auxiliary storage device is a flash memory or an HDD (Hard Disk Drive). The program and OS stored in the auxiliary storage device are loaded into the memory 302 and executed by the processor 301.
　シミュレーション装置１００は、１つのプロセッサ３０１のみを備えていてもよいし、複数のプロセッサ３０１を備えていてもよい。複数のプロセッサ３０１が「部」の機能を実現するプログラムを連携して実行してもよい。 The simulation apparatus 100 may include only one processor 301 or may include a plurality of processors 301. A plurality of processors 301 may execute a program that realizes the function of “unit” in cooperation.
　「部」の処理の結果を示す情報、データ、信号値、及び、変数値は、メモリ３０２、補助記憶装置、又は、プロセッサ３０１内のレジスタ又はキャッシュメモリに記憶される。 Information, data, signal values, and variable values indicating the processing results of “unit” are stored in the memory 302, the auxiliary storage device, or a register or cache memory in the processor 301.
　「部」の機能を実現するプログラムは、磁気ディスク、光ディスクといった可搬記録媒体に記憶されてもよい。 The program for realizing the function of “unit” may be stored in a portable recording medium such as a magnetic disk or an optical disk.
　＊＊＊動作の説明＊＊＊
　図１から図６を参照して、本実施の形態に係るシミュレーション装置１００の動作を説明する。シミュレーション装置１００の動作は、本実施の形態に係るシミュレーション方法に相当する。シミュレーション装置１００の動作は、本実施の形態に係るシミュレーションプログラムの処理手順に相当する。 *** Explanation of operation ***
The operation of the simulation apparatus 100 according to the present embodiment will be described with reference to FIGS. The operation of the simulation apparatus 100 corresponds to the simulation method according to the present embodiment. The operation of the simulation apparatus 100 corresponds to the processing procedure of the simulation program according to the present embodiment.
　まず、図１に示したシミュレーション装置１００の各部の動作を説明する。 First, the operation of each part of the simulation apparatus 100 shown in FIG. 1 will be described.
　模擬部１０１は、ＩＳＳに相当する機能を有する。模擬部１０１は、ターゲットプロセッサが実行可能な命令コードであるターゲット命令コード１２１を、ホストプロセッサが実行可能な命令コードであるホスト命令コード１２２に変換して実行する処理を管理する。 The simulation unit 101 has a function corresponding to ISS. The simulation unit 101 manages processing for converting a target instruction code 121 that is an instruction code that can be executed by the target processor into a host instruction code 122 that is an instruction code that can be executed by the host processor.
　デコード処理部１１０は、命令デコード処理を行う。具体的には、デコード処理部１１０は、模擬部１０１の指示により、命令実行アドレスで示される命令実行箇所に関して、変換されたホスト命令コード１２２がメモリ３０２上に存在するかを確認する。デコード処理部１１０は、そのようなホスト命令コード１２２が存在しない場合は、該当箇所のターゲット命令コード１２１に含まれる命令の種類と、ソース及びデスティネーションのレジスタ又はメモリアドレスとを解釈する。 The decode processing unit 110 performs instruction decode processing. Specifically, the decode processing unit 110 confirms whether or not the converted host instruction code 122 exists in the memory 302 for the instruction execution location indicated by the instruction execution address, according to the instruction of the simulation unit 101. When such a host instruction code 122 does not exist, the decode processing unit 110 interprets the type of instruction included in the target instruction code 121 at the corresponding location and the source and destination registers or memory addresses.
　変換処理部１１１は、命令変換処理を行う。具体的には、変換処理部１１１は、デコード処理部１１０が解釈したターゲット命令コード１２１を１つ又は複数のホスト命令コード１２２に変換する。変換処理部１１１は、変換後のホスト命令コード１２２をメモリ３０２に格納する。 The conversion processing unit 111 performs instruction conversion processing. Specifically, the conversion processing unit 111 converts the target instruction code 121 interpreted by the decoding processing unit 110 into one or a plurality of host instruction codes 122. The conversion processor 111 stores the converted host instruction code 122 in the memory 302.
　実行処理部１１２は、ホスト命令コード実行処理を行う。具体的には、実行処理部１１２は、変換処理部１１１がメモリ３０２に格納した変換後のホスト命令コード１２２のうち、実行すべきターゲット命令コード１２１に対応したホスト命令コード１２２を実行することにより、シミュレーションを行う。 The execution processing unit 112 performs host instruction code execution processing. Specifically, the execution processing unit 112 executes the host instruction code 122 corresponding to the target instruction code 121 to be executed among the converted host instruction codes 122 stored in the memory 302 by the conversion processing unit 111. , Do a simulation.
　一度変換及び実行されたターゲット命令コード１２１のシミュレーションが再度実行されるときは、デコード処理部１１０がメモリ３０２内を検索する。対応するホスト命令コード１２２が格納されていれば、模擬部１０１は、デコード処理部１１０への命令デコード処理指示と、変換処理部１１１への命令変換処理指示とを出さずに、実行処理部１１２にホスト命令コード実行処理指示を出す。このように、命令デコード処理及び命令変換処理を省略し、ホスト命令コード実行処理のみを行うことで、シミュレーションを高速化することができる。 When the simulation of the target instruction code 121 once converted and executed is executed again, the decode processing unit 110 searches the memory 302. If the corresponding host instruction code 122 is stored, the simulation unit 101 does not issue an instruction decode processing instruction to the decode processing unit 110 and an instruction conversion processing instruction to the conversion processing unit 111, and executes the execution processing unit 112. The host instruction code execution processing instruction is issued. Thus, the simulation can be speeded up by omitting the instruction decoding process and the instruction converting process and performing only the host instruction code execution process.
　コンテキスト情報Ｘ１３２及びコンテキスト情報Ｙ１３３は、コアＸ及びコアＹという２つのコアを持つマルチコアプロセッサシステムのシミュレーションを実行するためのコンテキスト情報である。コンテキスト情報をコア数分用意することで、任意の数のコアに対応することができる。 Context information X132 and context information Y133 are context information for executing a simulation of a multi-core processor system having two cores, core X and core Y. By preparing the context information for the number of cores, it is possible to deal with an arbitrary number of cores.
　コア選択部１０２は、次に実行すべきターゲット命令コード１２１がコアＸの命令コードとコアＹの命令コードのいずれであるかを判断する。コア選択部１０２は、判断結果に応じて、選択すべきコンテキスト情報を情報選択部１３１に伝達する。コンテキスト情報Ｘ１３２及びコンテキスト情報Ｙ１３３は、それぞれターゲットプロセッサのコアＸ及びコアＹがターゲット命令コード１２１を実行する際に必要な情報である。コンテキスト情報Ｘ１３２及びコンテキスト情報Ｙ１３３は、それぞれターゲットプロセッサの内部レジスタの情報、各コアで保持する命令実行アドレスの情報、時刻に関する情報、割り込みの情報、及び、リソースに関するその他の情報を含む。シミュレーション実行時にコアを切り替える場合は、コンテキスト情報も切り替えることで、共通のデコード処理部１１０、変換処理部１１１及び実行処理部１１２を利用することができる。 The core selection unit 102 determines whether the target instruction code 121 to be executed next is the instruction code of the core X or the instruction code of the core Y. The core selection unit 102 transmits context information to be selected to the information selection unit 131 according to the determination result. The context information X132 and the context information Y133 are information necessary when the core X and the core Y of the target processor execute the target instruction code 121, respectively. The context information X132 and the context information Y133 include information on internal registers of the target processor, information on instruction execution addresses held in each core, information on time, information on interrupts, and other information on resources. When switching cores during simulation execution, the common decoding processing unit 110, conversion processing unit 111, and execution processing unit 112 can be used by switching context information.
　情報選択部１３１は、次に実行すべきターゲット命令コード１２１がコアＸの命令コードである場合は、コンテキスト情報Ｘ１３２を読み出し、次に実行すべきターゲット命令コード１２１がコアＹの命令コードである場合は、コンテキスト情報Ｙ１３３を読み出す。情報選択部１３１は、読み出したコンテキスト情報を、実行処理部１１２のホスト命令コード実行処理で用いられるリソース情報として提供する。 When the target instruction code 121 to be executed next is the instruction code of the core X, the information selection unit 131 reads the context information X132, and when the target instruction code 121 to be executed next is the instruction code of the core Y Reads the context information Y133. The information selection unit 131 provides the read context information as resource information used in the host instruction code execution process of the execution processing unit 112.
　管理部１０３は、ターゲットプロセッサの時間進行をホスト命令コード１２２の実行に合わせて模擬する。管理部１０３は、１つのホスト命令コード１２２が実行される度に、命令の実行にかかる時間と、メモリアクセス、Ｉ／Ｏアクセス等にかかる時間とを算出し、算出結果を、コアごとに用意されたコンテキスト情報Ｘ１３２及びコンテキスト情報Ｙ１３３に反映する。各コアの時間情報は、一定間隔で同期化される。各コアの時間情報は、命令実行状況と合わせて性能情報として利用することが可能である。 The management unit 103 simulates the time progress of the target processor in accordance with the execution of the host instruction code 122. Each time one host instruction code 122 is executed, the management unit 103 calculates the time required for executing the instruction and the time required for memory access, I / O access, and the like, and prepares a calculation result for each core. Is reflected in the context information X132 and the context information Y133. The time information of each core is synchronized at regular intervals. The time information of each core can be used as performance information together with the instruction execution status.
　従来のシミュレーション方式では、複数コア間の共有リソースへのアクセスの順序を制御できないため、実際のハードウェアの動作を正確に再現することができない。性能の分析を考慮せず、ソフトウェアの機能を模擬することだけが目的の場合は、共有リソースへのアクセスの順序を正確に模擬しなくても、ソフトウェアに共有リソースへのアクセスのための排他制御機能があればよい。しかし、性能を分析するための性能シミュレーションを行う場合は、共有リソースへのアクセスの順序まで正確に模擬する必要がある。 In the conventional simulation method, the order of access to shared resources among multiple cores cannot be controlled, so that the actual hardware operation cannot be accurately reproduced. If the goal is simply to simulate software functions without considering performance analysis, the software has exclusive control for accessing shared resources without having to accurately simulate the order of access to shared resources. It only needs to have a function. However, when performing performance simulation for analyzing performance, it is necessary to accurately simulate the order of access to shared resources.
　本実施の形態では、シミュレーション装置１００が、共有リソースへのアクセスが発生した場合に命令実行を中断する中断部２０２を備える。そのため、共有リソースへのアクセスの発生時点で複数コア間の同期が可能となり、複数コア間の共有リソースへのアクセスの順序を制御することが可能となる。 In the present embodiment, the simulation apparatus 100 includes an interruption unit 202 that interrupts instruction execution when access to a shared resource occurs. Therefore, synchronization between a plurality of cores becomes possible at the time of access to the shared resource, and the order of access to the shared resource between the plurality of cores can be controlled.
　本実施の形態では、シミュレーション装置１００が、さらに、ホスト命令コード１２２が実行されているときにシミュレーション上で共有リソースへのアクセスが発生したことを検出する検出部２０１を備える。メモリ３０２には、共有リソースの領域のアドレス範囲を示す共有リソース情報２０３が格納される。検出部２０１は、共有リソース情報２０３と実行処理部１１２が実行している命令のオペランドアドレスとを基に、共有リソースへのアクセスの発生を検出する。中断部２０２は、検出部２０１から共有リソースへのアクセスの発生を検出したことの通知を受けて命令実行を中断する。 In the present embodiment, the simulation apparatus 100 further includes a detection unit 201 that detects that access to the shared resource has occurred on the simulation when the host instruction code 122 is being executed. The memory 302 stores shared resource information 203 indicating the address range of the shared resource area. The detection unit 201 detects the occurrence of access to the shared resource based on the shared resource information 203 and the operand address of the instruction executed by the execution processing unit 112. The interruption unit 202 interrupts instruction execution upon receiving notification from the detection unit 201 that occurrence of access to the shared resource has been detected.
　次に、図２に示した中断部２０２の各部の動作を説明する。 Next, the operation of each unit of the interruption unit 202 shown in FIG. 2 will be described.
　直前状態保持部２２０は、模擬部１０１より命令実行時のコンテキスト情報を受信する。直前状態保持部２２０は、受信したコンテキスト情報を、次の命令実行後まで保持する。直前状態保持部２２０は、保持したコンテキスト情報を、さらに次の命令が実行されるときはその前の命令実行時のコンテキスト情報に置き換える。 The previous state holding unit 220 receives context information at the time of instruction execution from the simulation unit 101. The immediately preceding state holding unit 220 holds the received context information until after the next instruction is executed. The previous state holding unit 220 replaces the held context information with the context information at the time of execution of the previous instruction when the next instruction is executed.
　直前状態復元部２２１は、検出部２０１から共有リソースへのアクセスの発生を検出したことの通知を受信すると、模擬部１０１に対して命令実行の中断を指示し、模擬部１０１のコンテキスト情報を直前状態保持部２２０が保持しているコンテキスト情報に戻す。これにより、模擬部１０１の状態を共有リソースへのアクセスが発生する直前の状態に戻すことができる。 When the immediately preceding state restoring unit 221 receives a notification from the detecting unit 201 that the occurrence of access to the shared resource has been detected, the immediately preceding state restoring unit 221 instructs the simulating unit 101 to suspend instruction execution, and the context information of the simulating unit 101 is immediately before The context information stored in the state storage unit 220 is restored. Thereby, the state of the simulation unit 101 can be returned to the state immediately before the access to the shared resource occurs.
　次に、図３に示した検出部２０１の各部の動作を説明する。 Next, the operation of each unit of the detection unit 201 shown in FIG. 3 will be described.
　オペランドアドレス監視部２２３は、実行処理部１１２より実行中の命令のオペランドアドレスの情報を受信し、そのアドレスの領域が共有リソースの領域であった場合、すなわち、そのアドレスが共有リソース情報２０３で示されたアドレス範囲内であった場合に、中断部２０２に通知を送る。 The operand address monitoring unit 223 receives the operand address information of the instruction being executed from the execution processing unit 112, and if the address area is a shared resource area, that is, the address is indicated by the shared resource information 203. If it is within the specified address range, a notification is sent to the interruption unit 202.
　共有リソースデータ復元部２２２は、実行処理部１１２で実行されている命令が共有リソースへのアクセスを伴う命令であった場合、その命令で発生するデータ転送の前の状態を復元する。 The shared resource data restoration unit 222 restores the state before the data transfer generated by the instruction when the instruction executed by the execution processing unit 112 is an instruction accompanied by access to the shared resource.
　ここで、図４及び図５の例を用いて、具体的な動作を説明する。 Here, the specific operation will be described with reference to the examples of FIGS.
　図４及び図５は、ターゲットプロセッサの命令コード列を実行順に示すとともに、各命令の実行時の直前状態保持部２２０の保持内容を各命令に対応して示している。シミュレーション時は、ターゲットプロセッサの命令列はホストプロセッサの命令列に変換されているが、簡単のためターゲットプロセッサの命令列で動作を説明する。 4 and 5 show the instruction code string of the target processor in the order of execution, and the contents held in the immediately preceding state holding unit 220 when each instruction is executed are shown corresponding to each instruction. At the time of simulation, the instruction sequence of the target processor is converted into the instruction sequence of the host processor. For simplicity, the operation will be described using the instruction sequence of the target processor.
　図４の例では、命令ａ１から順に実行され、Ｌｏａｄ／Ｓｔｏｒｅ命令ａ１０で命令列が区切られている。すなわち、命令ａ１で始まり、Ｌｏａｄ／Ｓｔｏｒｅ命令ａ１０で終わる命令列が構成されている。Ｌｏａｄ／Ｓｔｏｒｅ命令ａ１０の次は命令ａ１１から命令ａ１６までが次の区切りの命令列になっている。すなわち、命令ａ１１で始まり、命令ａ１６で終わる命令列が次に構成されている。これらの命令列は、ホストプロセッサの命令コードに変換されて、それぞれホスト命令コード１２２のブロックとしてメモリ３０２に保存されている。 In the example of FIG. 4, the instructions are executed in order from the instruction a1, and the instruction string is delimited by the Load / Store instruction a10. That is, an instruction sequence starting with the instruction a1 and ending with the Load / Store instruction a10 is configured. Next to the Load / Store instruction a10, the instruction a11 to instruction a16 are the next delimited instruction sequence. That is, the instruction sequence starting with the instruction a11 and ending with the instruction a16 is formed next. These instruction sequences are converted into instruction codes of the host processor and stored in the memory 302 as blocks of the host instruction codes 122, respectively.
　また、図４の例では、命令ａ３実行時の直前状態保持部２２０の保持内容は、命令ａ２実行後の状態である。Ｌｏａｄ／Ｓｔｏｒｅ命令ａ１０実行時の直前状態保持部２２０の保持内容は、直前の命令ａ５実行後の状態である。このＬｏａｄ／Ｓｔｏｒｅ命令ａ１０が共有リソースへのアクセスが発生する命令でない場合は、そのまま次の命令ａ１１からの命令列が実行される。Ｌｏａｄ／Ｓｔｏｒｅ命令ａ１０が共有リソースへのアクセスだった場合は、図５の例のように、命令実行が中断され、コア間の同期化が行われる。 In the example of FIG. 4, the content held by the immediately previous state holding unit 220 when the instruction a3 is executed is the state after the execution of the instruction a2. The content held in the immediately preceding state holding unit 220 when the Load / Store instruction a10 is executed is the state after the execution of the immediately preceding instruction a5. If this Load / Store instruction a10 is not an instruction that causes access to a shared resource, the instruction sequence from the next instruction a11 is executed as it is. When the Load / Store instruction a10 is an access to a shared resource, instruction execution is interrupted and synchronization between cores is performed as in the example of FIG.
　図５の例では、Ｌｏａｄ／Ｓｔｏｒｅ命令ａ１０が共有リソースへのアクセスが発生する命令であるため、命令実行が中断されて直前の命令ａ５実行後の状態が直前状態復元部２２１により復元される。次に、コア間で同期がとられ、命令実行が中断されたコアが他のコアよりも命令実行が遅れている場合に命令実行が再開される。他のコアで命令実行が遅れているコアがある場合は、その遅れているコアの命令が実行される。コア間の同期化によって、共有リソースへのアクセスが発生する命令を実行するコアが最も遅れた状態になってから命令実行が再開され、共有リソースへのアクセスが発生することにより、共有リソースへのアクセスの順序が保障されることになる。 In the example of FIG. 5, since the Load / Store instruction a10 is an instruction that causes access to the shared resource, the instruction execution is interrupted, and the state after execution of the immediately preceding instruction a5 is restored by the immediately preceding state restoring unit 221. Next, the cores are synchronized, and the instruction execution is resumed when the instruction execution is interrupted in the core where the instruction execution is interrupted later than the other cores. If there is a core whose instruction execution is delayed in another core, the instruction of the delayed core is executed. By executing synchronization between cores, the execution of instructions that cause access to shared resources is delayed most recently, and instruction execution is resumed, and access to shared resources occurs. The order of access will be guaranteed.
　図６は、シミュレーション装置１００の動作のフローを示している。 FIG. 6 shows an operation flow of the simulation apparatus 100.
　ステップＳ１１において、模擬部１０１の構成要素であるコア選択部１０２は、次に命令を実行するコアを選択する。コア間の命令実行状況に差がない場合、すなわち、コア間の時間進行が同等の場合、次に命令を実行するコアは任意でよい。コア間の命令実行状況に差がある場合、すなわち、いずれかのコアの時間が先行している場合は、時間が遅れている方のコアが選択される。 In step S11, the core selection unit 102, which is a component of the simulation unit 101, selects the core that executes the instruction next. When there is no difference in the instruction execution status between the cores, that is, when the time progress between the cores is equal, the core that executes the instruction next may be arbitrary. If there is a difference in instruction execution status between cores, that is, if the time of one of the cores precedes, the core with the later time is selected.
　ステップＳ１２において、情報選択部１３１は、ステップＳ１１で選択されたコアのコンテキスト情報を命令実行時の参照情報として選択する。ステップＳ１１で選択されたコアが次に実行すべきターゲット命令コード１２１を示す命令実行アドレスは、コンテキスト情報Ｘ１３２又はコンテキスト情報Ｙ１３３に保持されている。命令実行アドレスのターゲット命令コード１２１がホスト命令コード１２２に変換済であれば、ステップＳ１７の処理が行われる。一方、命令実行アドレスのターゲット命令コード１２１がホスト命令コード１２２に変換されていなければ、ステップＳ１３の処理が行われる。 In step S12, the information selection unit 131 selects the context information of the core selected in step S11 as reference information at the time of instruction execution. The instruction execution address indicating the target instruction code 121 to be executed next by the core selected in step S11 is held in the context information X132 or the context information Y133. If the target instruction code 121 of the instruction execution address has been converted to the host instruction code 122, the process of step S17 is performed. On the other hand, if the target instruction code 121 of the instruction execution address has not been converted to the host instruction code 122, the process of step S13 is performed.
　ステップＳ１３において、デコード処理部１１０は、命令実行アドレスのターゲット命令コード１２１を読み込む。 In step S13, the decode processing unit 110 reads the target instruction code 121 of the instruction execution address.
　ステップＳ１４において、デコード処理部１１０は、ステップＳ１４で読み込んだターゲット命令コード１２１をデコードする。 In step S14, the decode processing unit 110 decodes the target instruction code 121 read in step S14.
　ステップＳ１５において、変換処理部１１１は、ステップＳ１５でデコードされた情報に従ってターゲット命令コード１２１をホスト命令コード１２２に変換する。このホスト命令コード１２２は、１つ以上の命令を含む命令列となっている。変換処理部１１１は、ステップＳ１２で選択されたコンテキスト情報を参照して、レジスタ等の内部リソースに関する情報をホスト命令コード１２２に埋め込む。 In step S15, the conversion processing unit 111 converts the target instruction code 121 into the host instruction code 122 according to the information decoded in step S15. The host instruction code 122 is an instruction sequence including one or more instructions. The conversion processor 111 embeds information related to internal resources such as registers in the host instruction code 122 with reference to the context information selected in step S12.
　ステップＳ１６において、変換処理部１１１は、ステップＳ１５で得られたホスト命令コード１２２を１つのブロックとしてメモリ３０２に格納する。 In step S16, the conversion processing unit 111 stores the host instruction code 122 obtained in step S15 in the memory 302 as one block.
　次に、コア間の同期化が必要か判断される。ステップＳ１６で格納されたホスト命令コード１２２が同期化命令、分岐命令、及び、共有リソースへのアクセスが発生する可能性がある命令のいずれかに当てはまれば、同期化が必要であり、いずれでもなければ、同期化は不要である。同期化が不要であれば、ステップＳ１３からステップＳ１６の処理が繰り返されてターゲット命令コード１２１の変換が実施される。同期化が必要であれば、ターゲット命令コード１２１の変換が中断され、その時点でのホスト命令コード１２２のブロックの格納が完了する。そして、ステップＳ１７の処理が行われる。 Next, it is determined whether synchronization between cores is necessary. If the host instruction code 122 stored in step S16 is one of a synchronization instruction, a branch instruction, and an instruction that may cause access to a shared resource, synchronization is necessary, and either For example, no synchronization is necessary. If synchronization is not necessary, the processing from step S13 to step S16 is repeated and the target instruction code 121 is converted. If synchronization is required, the conversion of the target instruction code 121 is interrupted, and the storage of the block of the host instruction code 122 at that time is completed. Then, the process of step S17 is performed.
　ステップＳ１７において、中断部２０２の構成要素である直前状態保持部２２０は、直前の命令実行後の状態として、ステップＳ１２で選択されたコンテキスト情報を保存する。 In step S17, the immediately preceding state holding unit 220, which is a component of the interrupting unit 202, stores the context information selected in step S12 as the state after execution of the immediately preceding instruction.
　ステップＳ１８において、実行処理部１１２は、１つのターゲット命令コード１２１に相当するホスト命令コード１２２を実行する。検出部２０１の構成要素であるオペランドアドレス監視部２２３は、そのホスト命令コード１２２が共有リソースへのアクセスが発生する命令であるか否かを判断する。共有リソースへのアクセスが発生する命令であれば、ステップＳ１９の処理が行われる。 In step S18, the execution processing unit 112 executes the host instruction code 122 corresponding to one target instruction code 121. The operand address monitoring unit 223, which is a component of the detection unit 201, determines whether or not the host instruction code 122 is an instruction that causes access to a shared resource. If it is an instruction that causes access to a shared resource, the process of step S19 is performed.
　ステップＳ１９において、中断部２０２の構成要素である直前状態復元部２２１は、ステップＳ１７で保存された直前の命令実行後の状態を復元する。 In step S19, the immediately preceding state restoring unit 221 that is a component of the interrupting unit 202 restores the state after the previous instruction execution saved in step S17.
　次に、ホスト命令コード１２２の１つのブロックの実行が完了しているか判断される。ステップＳ１８でホスト命令コード１２２が共有リソースへのアクセスが発生する命令でなかった場合も、ホスト命令コード１２２の１つのブロックの実行が完了しているか判断される。完了していなければ、ステップＳ１７以降の処理が繰り返されてホスト命令コード１２２の実行が継続される。完了していれば、ステップＳ２０の処理が行われる。 Next, it is determined whether execution of one block of the host instruction code 122 is completed. If the host instruction code 122 is not an instruction that causes access to the shared resource in step S18, it is also determined whether execution of one block of the host instruction code 122 is completed. If not completed, the processing after step S17 is repeated and the execution of the host instruction code 122 is continued. If completed, the process of step S20 is performed.
　ステップＳ２０において、コア間の同期化が行われる。すなわち、コア間の命令実行状況に差がない場合、ステップＳ１１の処理が再び行われて、任意のコアが選択される。コア間の命令実行状況に差がある場合は、ステップＳ１１で時間が遅れている方のコアが選択される。 In step S20, synchronization between cores is performed. That is, when there is no difference in the instruction execution status between the cores, the process of step S11 is performed again, and an arbitrary core is selected. If there is a difference in instruction execution status between the cores, the core whose time is delayed is selected in step S11.
　共有リソースアクセスが発生する命令は、同期化が必要なため、ホスト命令コード１２２の１つのブロックの最後に格納されている。よって、ステップＳ１８で共有リソースアクセスが発生する命令が実行され、ステップＳ１９で直前の命令実行後の状態が復元された後は、１つのブロックの実行が完了していると判断され、ステップＳ２０において、コア間の同期化が行われる。 An instruction that causes shared resource access is stored at the end of one block of the host instruction code 122 because it needs to be synchronized. Therefore, after an instruction that causes shared resource access is executed in step S18 and the state after execution of the previous instruction is restored in step S19, it is determined that execution of one block is completed, and in step S20 Synchronization between cores is performed.
　上記のように、本実施の形態において、模擬部１０１は、複数のコアの中からコアを１つずつ繰り返し選択し、選択したコアにおける命令の実行を模擬する。管理部１０３は、模擬部１０１により模擬された命令の実行に合わせて、模擬部１０１により選択されたコアにおける時間の進行を模擬する。管理部１０３は、模擬の結果に応じて、模擬部１０１により選択されたコアの時間情報を更新する。時間情報は、複数のコアにおける時間の進行度を示す情報である。時間情報は、コアごとに個別に作成される。図示していないが、時間情報は、コンテキスト情報の一部としてメモリ３０２に格納されている。中断部２０２は、模擬部１０１により共有リソースへのアクセスを伴う命令の実行の模擬が開始された場合、メモリ３０２に格納された時間情報が示す複数のコアにおける時間の進行度が同じになるまで、模擬部１０１により選択されたコアにおける命令の実行の模擬を中断して別のコアにおける命令の実行を模擬するよう模擬部１０１を制御する。 As described above, in the present embodiment, the simulation unit 101 repeatedly selects a core from a plurality of cores one by one, and simulates execution of an instruction in the selected core. The management unit 103 simulates the progress of time in the core selected by the simulation unit 101 in accordance with the execution of the command simulated by the simulation unit 101. The management unit 103 updates the time information of the core selected by the simulation unit 101 according to the simulation result. The time information is information indicating the degree of time progress in a plurality of cores. The time information is created individually for each core. Although not shown, the time information is stored in the memory 302 as part of the context information. When the simulation unit 101 starts simulating the execution of an instruction that involves access to a shared resource, the interruption unit 202 continues until the time progress in the plurality of cores indicated by the time information stored in the memory 302 becomes the same. The simulation unit 101 is controlled so as to simulate the execution of the instruction in another core by interrupting the simulation of the instruction execution in the core selected by the simulation unit 101.
　また、本実施の形態において、検出部２０１は、模擬部１０１により転送先のアドレスを指定してデータを転送する命令の実行の模擬が開始された場合、共有リソース情報２０３を参照し、指定されたアドレスと、参照した共有リソース情報２０３が示すアドレスとを比較する。検出部２０１は、比較の結果に応じて、模擬部１０１により共有リソースへのアクセスを伴う命令の実行の模擬が開始されたことを検出し、中断部２０２に通知を送る。中断部２０２は、この通知を受けることで、模擬部１０１により共有リソースへのアクセスを伴う命令の実行の模擬が開始されたことを認識できる。 Further, in the present embodiment, the detection unit 201 is designated by referring to the shared resource information 203 when the simulation unit 101 starts simulating the execution of an instruction to transfer data by specifying a transfer destination address. The address indicated by the referenced shared resource information 203 is compared. The detection unit 201 detects that the simulation of execution of an instruction involving access to the shared resource is started by the simulation unit 101 according to the comparison result, and sends a notification to the interruption unit 202. Upon receiving this notification, the interrupting unit 202 can recognize that the simulation unit 101 has started to simulate the execution of an instruction that accompanies access to the shared resource.
　また、本実施の形態において、模擬部１０１は、選択したコアにおける命令の実行を模擬する度に、模擬の結果に応じて、選択したコアのコンテキスト情報を更新する。コンテキスト情報は、複数のコアにおける命令の実行状況を示す情報である。コンテキスト情報は、コアごとに個別に作成される。中断部２０２は、模擬部１０１により１つの命令の実行が模擬される度に、模擬部１０１により次の命令の実行の模擬が開始される前のコンテキスト情報を直前のコンテキスト情報としてメモリ３０２から取得する。中断部２０２は、模擬部１０１により当該次の命令として共有リソースへのアクセスを伴う命令の実行の模擬が開始された場合、当該次の命令の実行の模擬を模擬部１０１に中断させるとともに、メモリ３０２に格納されているコンテキスト情報を直前のコンテキスト情報に置換する。 In the present embodiment, the simulation unit 101 updates the context information of the selected core according to the simulation result every time the execution of the instruction in the selected core is simulated. The context information is information indicating the execution status of instructions in a plurality of cores. The context information is created individually for each core. Whenever the simulation unit 101 simulates the execution of one instruction, the interruption unit 202 acquires the context information before the simulation of the execution of the next instruction by the simulation unit 101 from the memory 302 as the immediately preceding context information. To do. When the simulation unit 101 starts simulating the execution of an instruction with access to a shared resource as the next instruction, the interruption unit 202 causes the simulation unit 101 to suspend the execution of the next instruction and The context information stored in 302 is replaced with the previous context information.
　このように、本実施の形態では、共有リソースへのアクセスが発生する命令の実行時にコア間の同期をとることにより、複数コア間の共有リソースへのアクセスの順序を正確に模擬することができる。 As described above, according to the present embodiment, it is possible to accurately simulate the order of access to the shared resources among a plurality of cores by synchronizing the cores when executing an instruction that causes access to the shared resources. .
　＊＊＊実施の形態の効果の説明＊＊＊
　本実施の形態では、複数のコアと共有リソースとを有するシステムの並列処理の動作が模擬される。１つのコアにおける、共有リソースへのアクセスを伴う命令の実行の模擬が開始された場合、複数のコアにおける時間の進行度が同じになるまで、当該１つのコアにおける命令の実行の模擬が中断され、別のコアにおける命令の実行が模擬される。このため、シミュレーションにおいて、共有リソースへのアクセスを実際のハードウェアと同じ順序で発生させることができる。複数のコアを複数のプロセッサに置き換えた場合も、同等の効果を得ることができる。 *** Explanation of the effect of the embodiment ***
In the present embodiment, the parallel processing operation of a system having a plurality of cores and shared resources is simulated. When simulation of instruction execution with access to a shared resource in one core is started, simulation of instruction execution in that core is suspended until the time progress in the multiple cores is the same. The execution of instructions in another core is simulated. For this reason, in the simulation, access to the shared resource can occur in the same order as the actual hardware. The same effect can be obtained when a plurality of cores are replaced with a plurality of processors.
　＊＊＊他の構成＊＊＊
　本実施の形態では、「部」の機能がソフトウェアにより実現されるが、変形例として、「部」の機能がソフトウェアとハードウェアとの組み合わせにより実現されてもよい。具体例として、１つ又はいくつかの「部」の機能が処理回路により実現され、残りの機能がソフトウェアにより実現されてもよい。 *** Other configurations ***
In the present embodiment, the function of “unit” is realized by software. However, as a modification, the function of “unit” may be realized by a combination of software and hardware. As a specific example, one or several “unit” functions may be realized by a processing circuit, and the remaining functions may be realized by software.
　処理回路は、具体的には、単一回路、複合回路、プログラム化したプロセッサ、並列プログラム化したプロセッサ、ロジックＩＣ、ＧＡ（Ｇａｔｅ　Ａｒｒａｙ）、又は、ＦＰＧＡ（Ｆｉｅｌｄ－Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）である。或いは、処理回路は、具体的には、ＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ　Ｓｐｅｃｉｆｉｃ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）である。 Specifically, the processing circuit is a single circuit, a composite circuit, a programmed processor, a processor programmed in parallel, a logic IC, a GA (Gate Array), or an FPGA (Field-Programmable Gate Array). Alternatively, the processing circuit is specifically an ASIC (Application Specific Integrated Circuit).
　プロセッサ３０１、メモリ３０２、及び、処理回路を、総称して「プロセッシングサーキットリ」という。つまり、「部」の機能は、ソフトウェアにより実現されるか、ソフトウェアとハードウェアとの組み合わせにより実現されるかに関わらず、プロセッシングサーキットリにより実現される。 The processor 301, the memory 302, and the processing circuit are collectively referred to as “processing circuit”. That is, the function of “unit” is realized by a processing circuit regardless of whether it is realized by software or a combination of software and hardware.
　「部」を「工程」、「手順」又は「処理」に読み替えてもよい。 “Part” may be read as “Process”, “Procedure” or “Process”.
　以上、本発明の実施の形態について説明したが、この実施の形態を部分的に実施しても構わない。具体的には、この実施の形態に係るシミュレーション装置１００の機能要素のうち、一部の機能要素のみを採用してもよい。なお、本発明は、この実施の形態に限定されるものではなく、必要に応じて種々の変更が可能である。 As mentioned above, although embodiment of this invention was described, you may implement this embodiment partially. Specifically, only some of the functional elements of the simulation apparatus 100 according to this embodiment may be employed. In addition, this invention is not limited to this embodiment, A various change is possible as needed.
　１００　シミュレーション装置、１０１　模擬部、１０２　コア選択部、１０３　管理部、１１０　デコード処理部、１１１　変換処理部、１１２　実行処理部、１２１　ターゲット命令コード、１２２　ホスト命令コード、１３１　情報選択部、１３２　コンテキスト情報Ｘ、１３３　コンテキスト情報Ｙ、２０１　検出部、２０２　中断部、２０３　共有リソース情報、２２０　直前状態保持部、２２１　直前状態復元部、２２２　共有リソースデータ復元部、２２３　オペランドアドレス監視部、３０１　プロセッサ、３０２　メモリ。 100 simulation device, 101 simulation unit, 102 core selection unit, 103 management unit, 110 decode processing unit, 111 conversion processing unit, 112 execution processing unit, 121 target instruction code, 122 host instruction code, 131 information selection unit, 132 context information X, 133 Context information Y, 201 Detection unit, 202 Interruption unit, 203 Shared resource information, 220 Immediate state holding unit, 221 Immediate state restoration unit, 222 Shared resource data restoration unit, 223 Operand address monitoring unit, 301 processor, 302 memory .

Claims (7)

  1. 　プログラムの命令を個別に実行する複数の要素と前記複数の要素からアクセスされる共有リソースとを有するシステムの並列処理の動作を模擬するシミュレーション装置であって、
    　前記複数の要素の中から要素を１つずつ繰り返し選択し、選択した要素における命令の実行を模擬する模擬部と、
    　前記模擬部により模擬された命令の実行に合わせて、前記模擬部により選択された要素における時間の進行を模擬し、模擬の結果に応じて、メモリに格納され前記複数の要素における時間の進行度を示す時間情報を更新する管理部と、
    　前記模擬部により前記共有リソースへのアクセスを伴う命令の実行の模擬が開始された場合、前記メモリに格納された時間情報が示す前記複数の要素における時間の進行度が同じになるまで、前記模擬部により選択された要素における命令の実行の模擬を中断して別の要素における命令の実行を模擬するよう前記模擬部を制御する中断部と
    を備えるシミュレーション装置。     A simulation apparatus for simulating a parallel processing operation of a system having a plurality of elements that individually execute program instructions and a shared resource accessed from the plurality of elements,
    A simulation unit that repeatedly selects one element from the plurality of elements one by one, and simulates execution of an instruction in the selected element;
    In accordance with the execution of the instruction simulated by the simulation unit, the progress of time in the element selected by the simulation unit is simulated, and the progress of time in the plurality of elements stored in the memory according to the simulation result A management unit for updating the time information indicating
    When the simulation unit starts simulating the execution of an instruction involving access to the shared resource, the simulation is performed until the time progress in the plurality of elements indicated by the time information stored in the memory becomes the same. A simulation apparatus comprising: an interruption unit that controls the simulation unit so as to simulate the execution of an instruction in another element by interrupting the simulation of the instruction execution in the element selected by the unit.
  2. 　前記模擬部により転送先のアドレスを指定してデータを転送する命令の実行の模擬が開始された場合、前記メモリに格納され前記共有リソースのアドレスを示す共有リソース情報を参照し、指定されたアドレスと、参照した共有リソース情報が示すアドレスとを比較し、比較の結果に応じて、前記模擬部により前記共有リソースへのアクセスを伴う命令の実行の模擬が開始されたことを検出し、前記中断部に通知を送る検出部
    をさらに備える請求項１に記載のシミュレーション装置。     When simulation of the execution of an instruction to transfer data by designating a transfer destination address is started by the simulation unit, the specified address is referred to the shared resource information indicating the address of the shared resource stored in the memory And the address indicated by the referenced shared resource information, and according to the result of the comparison, the simulation unit detects that the execution of an instruction involving access to the shared resource has been started, and the interruption The simulation apparatus according to claim 1, further comprising a detection unit that sends a notification to the unit.
  3. 　前記模擬部は、選択した要素における命令の実行を模擬する度に、模擬の結果に応じて、前記メモリに格納され前記複数の要素における命令の実行状況を示すコンテキスト情報を更新し、
    　前記中断部は、前記模擬部により１つの命令の実行が模擬される度に、前記模擬部により次の命令の実行の模擬が開始される前のコンテキスト情報を直前のコンテキスト情報として前記メモリから取得し、前記模擬部により当該次の命令として前記共有リソースへのアクセスを伴う命令の実行の模擬が開始された場合、当該次の命令の実行の模擬を前記模擬部に中断させるとともに、前記メモリに格納されているコンテキスト情報を前記直前のコンテキスト情報に置換する請求項１又は２に記載のシミュレーション装置。     Each time the simulation unit simulates the execution of an instruction in the selected element, the context information stored in the memory and indicating the execution status of the instruction in the plurality of elements is updated according to the simulation result.
    Whenever the simulation unit simulates the execution of one instruction, the interruption unit acquires the context information before the simulation of the execution of the next instruction from the simulation unit as the previous context information from the memory. And when the simulation unit starts simulating the execution of an instruction with access to the shared resource as the next instruction, the simulation unit suspends the simulation of the execution of the next instruction and stores the memory in the memory. The simulation apparatus according to claim 1, wherein the stored context information is replaced with the immediately preceding context information.
  4. 　前記複数の要素は、プロセッサの複数のコアである請求項１から３のいずれか１項に記載のシミュレーション装置。 The simulation device according to any one of claims 1 to 3, wherein the plurality of elements are a plurality of cores of a processor.
  5. 　前記複数の要素は、複数のプロセッサである請求項１から３のいずれか１項に記載のシミュレーション装置。 The simulation device according to any one of claims 1 to 3, wherein the plurality of elements are a plurality of processors.
  6. 　プログラムの命令を個別に実行する複数の要素と前記複数の要素からアクセスされる共有リソースとを有するシステムの並列処理の動作を模擬するシミュレーション方法であって、
    　模擬部が、前記複数の要素の中から要素を１つずつ繰り返し選択し、選択した要素における命令の実行を模擬し、
    　管理部が、前記模擬部により模擬された命令の実行に合わせて、前記模擬部により選択された要素における時間の進行を模擬し、模擬の結果に応じて、メモリに格納され前記複数の要素における時間の進行度を示す時間情報を更新し、
    　中断部が、前記模擬部により前記共有リソースへのアクセスを伴う命令の実行の模擬が開始された場合、前記メモリに格納された時間情報が示す前記複数の要素における時間の進行度が同じになるまで、前記模擬部により選択された要素における命令の実行の模擬を中断して別の要素における命令の実行を模擬するよう前記模擬部を制御するシミュレーション方法。     A simulation method for simulating a parallel processing operation of a system having a plurality of elements that individually execute program instructions and a shared resource accessed from the plurality of elements,
    The simulation unit repeatedly selects one element from the plurality of elements one by one, simulates execution of an instruction in the selected element,
    The management unit simulates the progress of time in the element selected by the simulation unit in accordance with the execution of the instruction simulated by the simulation unit, and is stored in the memory according to the simulation result. Update the time information that shows the progress of the time,
    When the suspending unit starts simulating the execution of an instruction involving access to the shared resource by the simulating unit, the progress of time in the plurality of elements indicated by the time information stored in the memory becomes the same Until now, the simulation method of controlling the simulation unit so as to simulate the execution of the instruction in another element by interrupting the simulation of the instruction execution in the element selected by the simulation unit.
  7. 　プログラムの命令を個別に実行する複数の要素と前記複数の要素からアクセスされる共有リソースとを有するシステムの並列処理の動作を模擬するシミュレーションプログラムであって、
    　コンピュータに、
    　前記複数の要素の中から要素を１つずつ繰り返し選択し、選択した要素における命令の実行を模擬する処理と、
    　模擬された命令の実行に合わせて、選択された要素における時間の進行を模擬し、模擬の結果に応じて、メモリに格納され前記複数の要素における時間の進行度を示す時間情報を更新する処理と、
    　前記共有リソースへのアクセスを伴う命令の実行の模擬が開始された場合、前記メモリに格納された時間情報が示す前記複数の要素における時間の進行度が同じになるまで、選択された要素における命令の実行の模擬を中断して別の要素における命令の実行を模擬する処理と
    を実行させるシミュレーションプログラム。     A simulation program for simulating a parallel processing operation of a system having a plurality of elements that individually execute program instructions and a shared resource accessed from the plurality of elements,
    On the computer,
    A process of repeatedly selecting elements one by one from the plurality of elements and simulating execution of instructions in the selected elements;
    A process of simulating the progress of time in the selected element in accordance with the execution of the simulated instruction and updating time information indicating the degree of progress of time in the plurality of elements stored in the memory according to the simulation result When,
    When simulation of execution of an instruction involving access to the shared resource is started, the instruction in the selected element until the time progress in the plurality of elements indicated by the time information stored in the memory becomes the same The simulation program which performs the process which interrupts the simulation of execution and simulates the execution of the instruction in another element.
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