JP2579191B2 - Oscillation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit, and more particularly, to an inverter and a flip-flop capable of obtaining two oscillation outputs of a low-speed clock signal and a high-speed clock signal. And a clock oscillation circuit using the same.

[Prior Art] As this kind of conventional clock signal oscillation circuit, there is a third type.
A circuit as shown in the figure can be mentioned.

In this configuration, an inverter 3 is connected to the reset terminal R side of a flip-flop 10 formed by cross-connecting two NOR circuits 1 and 2, and the input side of the inverter 3 and the set terminal S of the flip-flop 10 are shared. The input terminal 5 is connected to the input terminal 5 and the output side of the NOR circuit 2 is connected to the output terminal 6 via the inverter 4 to provide an externally mounted circuit between the input terminal 5 and the output terminal 6, for example, a ceramic resonance circuit. A clock signal is obtained by oscillating a predetermined frequency by connecting a resonance circuit including a capacitor and a capacitor or a time constant circuit including a CR element.

[Problem to be Solved] In such a conventional oscillation circuit, FIG.
As shown in (b), when the feedback input signal falls from the increased high voltage and is inverted by the inverter 3,
The NOR circuit 2 performs an inverting operation and its output goes from a high level (hereinafter “H”) to a low level (hereinafter “L”). Until the inversion operation is performed, the NOR circuit 2 does not perform the inversion operation corresponding to the output of the inverter 3. This is the 2 of NOR circuit 2.
This is because the NOR circuit 2 does not generate the inverted output "H" unless both inputs become "L". That is, the oscillation frequency is determined including the operation of the NOR circuit 1, and when the time constant of the external feedback circuit is large, the oscillation is performed at the corresponding low frequency, and FIG.
As shown in (2), when the time constant of the external feedback circuit is small, oscillation occurs at a relatively high frequency corresponding thereto.

However, the oscillation frequency in this case is limited by the operation speed of the flip-flop and cannot be too high.

In such a circuit, one oscillation frequency is usually selected, and when a low frequency and a somewhat high frequency are required, two circuits are provided respectively.

An object of the present invention is to solve such a problem of the prior art, and an object of the present invention is to provide an oscillation circuit capable of selecting two operation modes of high oscillation and lower oscillation.

[Means for Solving the Problems] A feature of the oscillation circuit according to the first invention for achieving such an object is that the oscillation circuit includes first and second logic circuits that invert each other, and A flip-flop in which the input of the circuit is connected to the reset terminal and the input of the second logic circuit is connected to the set terminal; a first inverter whose output side is connected to the reset terminal and whose input side is connected to the set terminal; A second inverter that receives an output signal of the first logic circuit and generates an oscillation output signal, and a feedback circuit that feeds back the oscillation output signal to the input side of the first inverter. Before the voltage fed back to the input reaches the predetermined inversion level of the second logic circuit when the time constant is selected to be equal to or less than the predetermined value, the first inverter and the first inverter are connected to each other.
The threshold level of the first logic circuit is made different from the threshold level of the second inverter so that the logic circuit and the second inverter perform an inversion operation, and the first logic circuit performs the inverter operation. Second on the side
The output of the second inverter is fed back before the output level of the logic circuit of FIG.
Forming an oscillation circuit with the logic circuit and the second inverter,
When the time constant of the feedback circuit is set to the predetermined value or more, the first and second logic circuits form an oscillating circuit that performs an inverting operation as a flip-flop.

Also, a feature of the second invention is that the input of the first logic circuit of the flip-flop is connected to a set terminal and the input of the second logic circuit is connected to a reset terminal.

[Operation] As described above, the threshold level of the output of the first logic circuit of the flip-flop is made different from the threshold level of the output-side inverter receiving the output and the other second logic circuit forming the flip-flop. Since the inversion operation of the inverter occurs first, the feedback is fast when the output of the next inversion operation is generated from the first logic circuit before the second logic circuit starts the inversion operation. When the constant feedback circuit is installed as an external circuit, the second logic circuit does not participate in the operation, and the first logic circuit of the flip-flop operates as an inverter, and an oscillation circuit composed of only the inverter is provided. can do. As a result, a high-frequency oscillation mode can be set.

On the other hand, when the time constant of the external feedback circuit is large, the difference in threshold between the inverter and the other second logic circuit has no effect. Oscillation mode.

Therefore, oscillation that can be selected by the time constant of a feedback circuit that externally mounts the two oscillation modes becomes possible.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1A is a block diagram of an oscillator circuit according to an embodiment to which the present invention is applied, FIG. 1B is an explanatory diagram for explaining a threshold level thereof, and FIG. 2 is an operation thereof. 6 is a timing chart for explaining FIG.

Components similar to those in FIG. 3 are denoted by the same reference numerals.

In FIG. 1 (a), the difference from the conventional one is that the threshold level of the inverter 8 receiving the output of the NOR circuit 2 in the flip-flop 11 is different from the threshold level of the NOR circuit 7.

The inverter 8 corresponds to the conventional inverter 4 and has a NOR
The circuit 7 corresponds to the conventional NOR circuit 1. However, as shown in FIG. 1 (b), the threshold level is different from the conventional level, and the threshold level Vin of the inverter 8 is It is at a higher position on the power supply voltage VDD side than the threshold level Vna of the NOR circuit 7. Note that GND is a ground level.

The difference between these thresholds is determined by the threshold level Vin when the time constant of the feedback circuit 9 is small.
Is set to be longer than the time required for the NOR circuit 2 to operate again by an input signal that is fed back by the time constant of the external resonance circuit. In other words, as shown in the timing chart of FIG. 2B, when a resonance circuit having a time constant that is fed back faster than the time required for the voltage to fall from the threshold level Vin to the threshold level Vna is connected to the outside. In this oscillation, the output of the NOR circuit 7 remains locked near the "L" level in the initial state, and the NOR circuit 7 does not contribute to the oscillation operation. At this time, N
Since the output of the OR circuit 7 is locked to “L”, one input of the NOR circuit 2 becomes “L” and the output is inverted according to the other input. Therefore, the oscillating operation is performed by the inverter 3, the NOR circuit 2 performing the inverter operation, and the inverter 8, and the input signal that is simply fed back is inverted and amplified.

That is, as shown in FIG. 2 (b), when the feedback signal from the feedback circuit 9 goes from the power supply voltage VDD to "L" via "H" at the start of oscillation, the set input of the NOR circuit 7 is in the initial state. Becomes “H” and the reset input of the NOR circuit 2 becomes
Since it is "L" in the initial state, the output of the NOR circuit 7 becomes "L". When the output of the NOR circuit 7 is "L", the NOR circuit 2 performs an inverter operation on the other input.

At first, since the "H" output of the NOR circuit 2 exceeds the Vin of the inverter 8, the inverter 8 performs an inverting operation and its output decreases from "H" to "L". Therefore, the feedback voltage of the feedback circuit 9 also decreases as shown in FIG. 2 (b). Produces the output of The NOR circuit 2 receiving this signal performs an inverter operation to generate an “L” output. As a result, "L" is input to the inverter 8, and the output of the inverter 8 changes from "L" to "H".

Here, the "H" output of the NOR circuit 2 is connected to the inverter 8
Is longer than the time when the inverter 8 starts changing from “L” to “H”, the feedback voltage of the feedback circuit 9 decreases from “H” to “L” and the NOR circuit The level of the inversion level Vna of the NOR circuit 7 and the time constant of the feedback circuit 9 are set so as to be performed before reaching the inversion level Vna of 7.

As a result, the next inversion operation is continuously performed according to the change in the output of the inverter 8. That is, when the output of the inverter 8 starts to change from “L” to “H”, the feedback voltage of the feedback circuit 9 also increases from “L” to “H”. At this time, since the output of the NOR circuit 2 is in the “L” state, the input of the NOR circuit 2 receiving the output of the NOR circuit 7 is locked in the “L” state. As long as the output of the NOR circuit 7 is “L”, the output of the NOR circuit 2 operates as an inverter, and the output “L” generated in the inverter 3 by the feedback input “H” is changed to “H”.
And outputs it to the inverter 8. Then, the inverter 8 changes its output from "H" to "L" as before.

On the other hand, as shown in the timing chart of FIG. 2A, when a resonance circuit having a time constant that is fed back at a speed slower than the time required to fall from the threshold level Vin to the threshold level Vna is connected to the outside, In this oscillation, the output of the NOR circuit 2 first exceeds the threshold level Vna, which becomes one input of the NOR circuit 7, and thereafter, the other input of the NOR circuit 7 receives the input signal fed back, and Threshold level Vna
, And the NOR circuit 7 is in a state of performing an inversion operation. Therefore, the NOR circuit 2 performs an inverting operation according to the output of the inverter 3.

That is, in this case, the time constant of the feedback circuit 9 such as an externally mounted resonance circuit is relatively large, and the feedback circuit has a time constant that is fed back later than the time from when the threshold level Vin drops to the threshold level Vna. 9
Is connected to the outside, the other input of the NOR circuit 2 exceeds the threshold level Vna and becomes equal to or higher than the inversion level before the feedback input signal reaches the inversion level, so that the NOR circuit 7 and the inverter 8 The difference between the thresholds has no effect. As a result, the oscillation operation mode including the conventional flip-flop operation is set. In this manner, an oscillation circuit that can select one of the two oscillation modes by the time constant of a resonance circuit that is externally mounted can be provided.

Therefore, by selecting the externally mounted resonance circuit, oscillation can be performed in two oscillation modes as shown in the timing charts of FIGS. 2A and 2B.

Looking at the oscillation operation in the case where the time constant of the external feedback circuit 9 is small among these two oscillation modes, as shown in FIG. 2 (b), until the voltage falls from the threshold level Vin to the threshold level Vna. It can be understood that the oscillation of a frequency higher than the conventional oscillation frequency is performed faster than the above-mentioned time.

As described above, in the embodiment, the inverter is inserted on the reset terminal side of the flip-flop, but this may be on the set terminal side, and the flip-flop is limited to the NOR circuit configuration. Not something.

[Effects of the Invention] As can be understood from the above description, according to the present invention, for the output of the first logic circuit of the flip-flop, an output-side inverter receiving this output and the flip-flop constitute the other. Since the threshold level of the second logic circuit is different from that of the second logic circuit so that the inversion operation of the inverter occurs first, the output of the next inversion operation is output before the second logic circuit starts the inversion operation. When a feedback circuit having a fast time constant such as that generated from the first logic circuit is mounted as an external circuit, the second logic circuit does not participate in the operation, and the first logic circuit of the flip-flop does not operate. An oscillation circuit that operates as an inverter and includes only an inverter can be provided.

 As a result, a high-frequency oscillation mode can be set.

On the other hand, when the time constant of the external feedback circuit is large, the difference in threshold between the inverter and the other second logic circuit has no effect. Oscillation mode.

Therefore, oscillation that can be selected by the time constant of a feedback circuit that externally mounts the two oscillation modes becomes possible.

[Brief description of the drawings]

FIG. 1 (a) is a block diagram of an oscillator circuit according to an embodiment of the present invention, FIG. 1 (b) is an explanatory diagram for explaining a threshold level thereof, and FIG. FIG. 3 is an explanatory diagram of a conventional oscillation circuit, and FIG. 4 is a timing chart for explaining the operation thereof. 1,2,7: NOR circuit, 3, 4, 8 ... Inverter, 5 ... Input terminal, 6 ... Output terminal, 9 ... Feedback circuit, 10,11 ... Flip-flop.

Claims (2)

(57) [Claims] A first logic circuit that inverts each other, an input of the first logic circuit being connected to a reset terminal, and an input of the second logic circuit being connected to a set terminal; A flip-flop, a first inverter having an output connected to the reset terminal, an input having an input connected to the set terminal, and an output signal from the first logic circuit for generating an oscillation output signal. And a feedback circuit that feeds back the oscillation output signal to the input side of the first inverter, and a voltage fed back to the input when a time constant of the feedback circuit is selected to be equal to or less than a predetermined value. Before the first inverter reaches a predetermined inversion level of the second logic circuit, the first inverter, the first logic circuit, and the second inverter perform an inversion operation so that a thread of the first logic circuit performs an inversion operation. Interview the second side hold level is different from the threshold level of the second inverter and said first logic circuit is an inverter operation
The output of the second inverter is fed back before the output level of the logic circuit is inverted, and an oscillation circuit is formed by the first inverter, the first logic circuit, and the second inverter. An oscillation circuit wherein the first and second logic circuits form an oscillation circuit that performs an inversion operation as a flip-flop when a time constant of the circuit is set to be equal to or greater than the predetermined value. 2. The oscillation circuit according to claim 1, wherein in the flip-flop, an input of the first logic circuit is connected to the set terminal, and an input of the second logic circuit is connected to the reset terminal.