JPH01307310A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To attain the oscillation in which the two oscillating modes are selected by a time constant with a feedback circuit mounted externally by differentiating a threshold level of an inverter at the output side receiving an output of a 1st logic circuit comprising a flip-flop and a threshold level of an other 2nd logic circuit comprising a flip-flop. CONSTITUTION:The threshold level of an inverter 8 receiving an output of the 1st logic circuit (NAND circuit) 2 in a flip-flop 11 and the threshold level of the 2nd logic circuit (NAND circuit) 7 are different. That is, the threshold level Vin of the inverter 8 is located at a higher level toward the power voltage VDD than the threshold level Van of the NAND circuit 7. Thus, the oscillation circuit able to select the two operation modes of low and high oscillating levels is obtained.

Description

[Detailed Description of the Invention] [Field of Application in Industry-1] This invention relates to an oscillation circuit, and more specifically, an inverter and a flip-flop that can obtain two oscillation outputs: a low-speed lock signal and a high-speed lock signal. This invention relates to a clock oscillation circuit using a

[Prior Art] As a conventional clock signal oscillation circuit of this type, a circuit as shown in FIG. 3 can be cited.

This is done by connecting the inverter 3 to the reset terminal R side of the flip-flop 10, which is constructed by cross-connecting two NAND circuits 1 and 2, and making the input side of the inverter 3 and the set terminal S of the flip-flop 10 common. The side connected to the NAND circuit 2 is the input terminal 5, the output side of the NAND circuit 2 is connected to the output terminal 6 via the inverter 4, and an external circuit is installed between the input terminal 5 and the output terminal 6, for example. A clock signal is obtained by oscillating at a predetermined frequency by connecting a ceramic resonator and a resonant circuit consisting of a capacitor or the like or a time constant circuit consisting of a CR element.

[Problem to be solved] In such a conventional oscillation circuit, (a) and (b) in FIG.
), when the feedback input signal drops from the raised high voltage and is inverted by inverter 3, the NA
The ND circuit 2 performs an inverting operation and its output becomes a HIGH level (hereinafter referred to as "H") and a low level (hereinafter referred to as "L"), but when the input signal that is fed back rises next time, the NAN
Until D circuit 1 performs inversion operation, NAND circuit 2 is
Does not perform inversion operation corresponding to the output of inverter 3.

That is, the oscillation frequency is determined including the operation of the NAND circuit l, and when the time constant of the external feedback circuit is large, it oscillates at a correspondingly low frequency, as shown in Figure 4 (b). Furthermore, when the time constant of the external feedback circuit is small, it oscillates at a correspondingly relatively high frequency.

However, the oscillation frequency in this case is limited by the operating speed of the flip-flop, and cannot be made very high.

Further, in such a circuit, one oscillation frequency is normally selected, and when a low frequency and a somewhat high frequency are required, two circuits are provided respectively.

The present invention solves the problems of the prior art, and aims to provide an oscillation circuit that can select between two operating modes: high oscillation and lower oscillation.

[Means for Solving the Problems] The means in the oscillation circuit of the present invention for achieving the above object are as follows. A first inverter is connected to the input side of a first logic circuit of a flip-flop having a second logic circuit, and the output of the first logic circuit is supplied to both the second inverter and the second logic circuit. and an oscillation circuit that feeds back the output of the second inverter to the input of the first inverter and the input of the second logic circuit via a feedback circuit.
The threshold levels of the second inverter and the second logic circuit are made different so that the second inverter or the second logic circuit performs an inversion operation before the second inverter or the second logic circuit. The oscillation circuit formed by the logic circuit and the second inverter can be selected later by an external feedback circuit.

[Operation] In this way, for the output of the first logic circuit of the flip-flop, the threshold level of the inverter on the output side that receives this output and the other second logic circuit that constitutes the flip-flop are made different. , since the inverter's inversion operation occurs first, the second logic circuit performs the inversion operation.

When a feedback circuit with a fast feedback time constant is installed as an external circuit so that the output of the next inversion operation is generated from the first logic circuit before entering the circuit, the second logic circuit is involved in the operation. Therefore, the first logic circuit of the flip-flop operates as an inverter, making it possible to create an oscillation circuit consisting of only inverters. As a result, a high frequency oscillation mode can be set.

On the other hand, when the time constant of the external feedback circuit is large, the difference in threshold between the inverter and the other second logic circuit has no effect, so including the corresponding lower conventional flip-flop operation. oscillation mode.

Therefore, oscillation can be performed in which two oscillation modes can be selected using the time constant of the externally attached feedback circuit.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1(a) is a block diagram of an oscillation circuit according to an embodiment of the present invention, FIG. 1(b) is an explanatory diagram illustrating its threshold level, and FIG. 2 is its operation. 2 is a timing chart illustrating.

Components similar to those in FIG. 3 are indicated by the same reference numerals.

In FIG. 1(a), the difference from the conventional one is the threshold level of the inverter 8 which receives the output of the NAND circuit 2 in the flip-flop 11 and the NAND
The difference is that the thread of circuit 7 and the hold level are different.

The inverter 8 corresponds to the conventional inverter 4, and
The D circuit 7 corresponds to the conventional NAND circuit 1, but
As shown in FIG. 1(b), the threshold level is different from the conventional one, and the threshold level V1n of the inverter 8 is higher than the threshold level Vna of the NAND circuit 7 on the power supply voltage VDD side. in position.

Note that GND is the ground level.

The difference between these thresholds is equal to the threshold level VI when the time constant of the feedback circuit 9 is small.
The time it takes for the NAND circuit to fall from n to the threshold level Vna is set to be longer than the time it takes for the NAND circuit 2 to operate again due to the feedback human input signal due to the time constant of the external resonant circuit. In other words, from the threshold level Vln to the threshold level V
When a resonant circuit with a time constant that returns faster than the time it takes to fall to NA is connected externally, this oscillation will occur as shown in the timing chart of FIG. 2(b).
N I) The output of circuit 7 remains locked near the "L" level in the initial state, and NANI) circuit 7
does not contribute to the oscillation operation. The oscillation operation is performed by inverter 3.
This is performed by a NAND circuit 2 that operates as an inverter, and an inverter 4, and the human input signal that is simply fed back is inverted and amplified.

On the other hand, when a resonant circuit with a time constant that is fed back at a slower rate than the time it takes to fall from the threshold level Vln to the threshold level Vna is connected to the outside, as shown in the timing chart of Fig. 2 (a), , this oscillation is caused by the output of the NAND circuit 2 first exceeding the threshold level Vna, which becomes one input of the NAND circuit 7, and then the other input signal of the NAND circuit 7 Thereupon, it exceeds the threshold level Vna, and the NAND circuit 7 enters a state in which it performs an inversion operation. Therefore, the NAND circuit 2 is
The inverting operation is performed in response to the output of the inverter 3.

That is, in this case, the time constant of the feedback circuit 9, such as a resonant circuit installed externally, is relatively large, and the threshold level Vn varies from the threshold level Vin to the threshold level Vn.
When the feedback circuit 9 with a time constant that returns the signal later than the time it takes for the signal to fall to A is externally connected, the other input of the NAND circuit 2 reaches the voltage level before the feedback input signal reaches the inverted level. Since the voltage exceeds the threshold level Vna and becomes equal to or higher than the inversion level, the difference in threshold between the NAND circuit 7 and the inverter 8 has no effect. As a result, the oscillation operation mode including conventional flip-flop and flip operations is achieved. In this way, it is possible to create an oscillation circuit in which two oscillation modes can be selected by the time constant of the externally attached resonant circuit.

Therefore, by selecting an externally attached resonant circuit, it is possible to oscillate in two oscillation modes as shown in the timing charts of FIGS. 2(a) and 2(b).

Of these two oscillation modes, looking at the oscillation operation when the time constant of the external feedback circuit 9 is small, the oscillation operation is shown in (b) in Figure 2.
As shown in FIG. 2, it can be seen that oscillation is performed faster than the time taken to fall from the threshold level Vln to the threshold level Vna, and at a higher frequency than the conventional oscillation frequency.

As explained in L1 below, in the embodiment, an inverter is inserted on the reset terminal side of the flip-flop, but this may also be on the set terminal side, and the flip-flop is
It is not limited to a NAND circuit configuration.

[Effects of the Invention] As can be understood from the above explanation, in this invention, for the output of the first logic circuit of the flip-flop,
The threshold hold level of the inverter on the output side that receives this output and the other second logic circuit constituting the flip-flop is made different so that the inverting operation of the inverter occurs first. When a feedback circuit with a fast feedback time constant is installed as an external circuit so that the output of the next inversion operation is generated from the first logic circuit before the logic circuit enters the inversion operation, the second logic circuit is no longer involved in the operation, and the first logic circuit of the flip-flop operates as an inverter, making it possible to create an oscillation circuit consisting only of the inverter.

As a result, a high frequency oscillation mode can be set.

On the other hand, when the time constant of the external feedback circuit is large, the difference in threshold between the inverter and the other second logic circuit has no effect, so including the corresponding lower conventional flip-flop operation. oscillation mode.

Therefore, oscillation can be performed in which two oscillation modes can be selected using the time constant of the externally attached feedback circuit.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram of an oscillation circuit according to an embodiment of the present invention, FIG. 1(b) is an explanatory diagram for explaining its threshold level, and FIG. 2 is an explanatory diagram for explaining its operation. FIG. 3 is an explanatory diagram of a conventional oscillation circuit, and FIG. 4 is a timing chart illustrating its operation. 1.2.7...NAND circuit, 3.4.8...Inverter, 5...Input terminal, 6...Output terminal, 9...Feedback circuit, 10.11...Flip-flop .

Claims (1)

[Claims] (1) Consisting of two logic circuits that perform mutually inverted operations,
a flip-flop having a set terminal and a reset terminal; a first inverter whose output side is connected to one of the set terminal and the reset terminal, and whose input side is connected to the other of the reset terminal;
a second inverter that receives an output signal from the logic circuit connected to the first inverter and generates an oscillation output signal; and a feedback circuit that feeds back the oscillation output signal to the input side of the first inverter. The threshold level of the logic circuit on the side to which the first inverter is not connected is different from the threshold level of the second inverter, and the second inverter is connected to the side to which the first inverter is not connected. The oscillation circuit is set to perform an inversion operation before the logic circuit of the first inverter, and an oscillation circuit formed of a first inverter, a logic circuit to which the first inverter is connected, and a second inverter can be selected. oscillation circuit.