JP2575049B2 - Serial data receiving device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a serial data receiving device built in a microprocessor.

(Prior Art) Conventionally, a serial data communication device often used in a one-chip microprocessor or the like is composed of a shift register, a shift counter, and a buffer register. A typical example thereof is Japanese Patent Publication No. 60-58482. It is indicated in the gazette.

2. Description of the Related Art In recent years, microprocessors have been remarkably popularized and have been used in many household electric appliances. It is not uncommon for VTRs and the like to use several microprocessors per unit. In a device incorporating many microprocessors, serial communication is frequently used as a means for exchanging information between processors. As a method of transmitting information, a frame in units of 4 bits or 8 bits is transmitted continuously for several blocks, and identification data of a processor to be transmitted is assigned to the first frame.

(Problems to be Solved by the Invention) However, when the amount of mutual communication between the processors increases and information comes and goes without interruption to a common serial communication line, each processor receives the information accurately. In addition, a great deal of effort must be paid to data reception.

That is, each processor starts a serial interrupt process each time reading of one frame of serial data into the serial buffer is completed, and decodes the contents of the serial buffer. Whether or not it exists must be determined in each serial interrupt processing routine. Further, even if the information is sent to another processor, at least processing until decoding of the identification data has to be performed, which is a heavy burden.

For this reason, a method has been proposed in which identification data is identified by hardware without receiving serial data reception by software.In such a case, the identification number differs for each processor. The hardware circuits must have their own identification numbers, and there is a problem in that the flexibility is lost when changing the identification numbers or setting the shared identification numbers.

Furthermore, recently, variable-length data according to the amount of information to be communicated is used, but with this, the number of frames in one communication varies, and the burden on software or hardware increases. there were.

The present invention has been made in view of such a problem,
A first object of the present invention is to realize a receiving apparatus capable of easily processing variable-length data with an address. A second object of the present invention is to provide a receiving apparatus using an interrupt process of a microprocessor. A third object of the present invention is to realize a receiving apparatus capable of processing received data every time reception of a frame is completed. In order to realize a receiving device that can clearly distinguish,
A fourth object of the present invention is to realize a receiving apparatus capable of processing continuous frame data without imposing a load on the processing of a microprocessor.

(Means for Solving the Problems) According to the present invention, there is provided an M which stores a data string of consecutive N frames supplied from a serial data input terminal after converting the data string into parallel.
The reception buffer memory for 1 (M <N) frames, address discrimination means for discriminating whether the address information stored in the reception buffer memory matches the self address, and the reception of data for 1 frame In response to the coincidence signal from the address discriminating means, an update clock generating means for outputting a frame updating clock each time the processing is completed, and an interrupt request signal synchronized with the update clock for a frame period based on the data length information of the received data. A receiving frame number setting means for sending to the processor and a connecting means for sending data stored in the receiving buffer memory to the data bus in accordance with an instruction from the microprocessor based on the interrupt request signal are provided.

(Operation) According to the present invention, the receiving buffer memory responds to the coincidence signal from the address discriminating means, and the receiving frame number setting means sequentially receives the number of frames based on the data length information stored in the memory means. After the data is transmitted to the data bus and the address discriminating means outputs the coincidence signal by the address discriminating means, the interrupt request signal to the microprocessor receives the number of frames based on the data length information stored in the memory means. Until the completion, the output is performed every time the reception of each frame is completed, and the update clock generation means performs a valid address determination only in the first frame in which the determination permission flag outputs the permission signal,
Since the data of the preceding frame is always stored in the memory for storing the data of two frames by the number-of-received-frames setting unit, the data processing time in the microprocessor has a margin.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a serial data receiving apparatus according to an embodiment of the present invention, in which a 4-bit constant-level cyclic shift register A to which a receiving clock is supplied via a serial clock terminal 1 is provided. A 2-bit counter B for counting the number of circulations of the shift register A,
When the parallel data is sent to the data bus 2 of the microprocessor, the data at the bit position decoded by the outputs of the shift register A and the counter B is supplied from the serial data input terminal 3 to the 16-bit reception buffer memory C ( Hereinafter, referred to as “memory C”), a digital comparator D for comparing comparison data supplied from the data bus 2 with data stored in the memory C, and a frame update clock every time reception of one frame of data is completed. And a reception frame number setting block E for sending variable length data to the data bus by counting update clocks by the number of frames based on the data length information stored in the memory C. The main part is configured.

The first bit of the output signal of the first bit of the output signal and the counter B of the shift register A and, via the AND gates A _1, is supplied to the D terminal of the frame update flip-flop 4.

Number of received frame setting block E supplies a second frame counter E ₁ bit, an OR gate E ₂ the output signal of each bit of the frame counter E ₁ is supplied to the input terminal, a preset signal to the frame counter E ₁ AND gate E ₃ and O
The interrupt request flip-flop E ₄ the output of the R gate E ₂ is supplied to the D terminal, a determination permission flag E ₅ the input of the reset side is an edge-operation, the inverter E _6, AN
It is constituted by a D gate E _7.

The output signal of the frame update flip-flop 4, as a clock signal, a clock terminal of the frame counter E _1, a clock terminal of the interrupt request flip-flop E _4, an input terminal of the AND gate E _3, an input terminal of the inverter E ₆ is supplied to the output signal of the inverter E ₆ is supplied to the reset terminal of the determination permission flag E _5. Discrimination permission flag
The output signal of the E ₅ is an input terminal of the AND gate E _3, are supplied to the output enable terminal OE of the digital comparator D, the output signal of the digital comparator D via the OR gate 5, the AND gate E ₃ 3 input terminal. The output signal of the interrupt request flip-flop E ₄ is supplied to the serial interrupt signal output terminal 6.

The reset terminal 7 is supplied with an initialization signal, and the clear terminal 8 is supplied with a software reset signal.

Signal from the serial data input terminal 3 through the inverter 9 and the inverter 10 of the Schmitt format, is supplied to the serial data input terminal C ₁₀ of the memory C.

The timing signal generated by the timing signal generation circuit F based on the clock signal from the serial clock terminal 1 and the clock signal from the system clock input terminal 11 is supplied to a serial data read clock input terminal _C30 of the memory C.

The output signal of the memory C is a 16-bit bus switcher G
And a select signal for reading the parallel output of the memory C to the data bus 2 from the block select terminal 12 to the bus switcher G.

The data of the most significant bit D15 of the memory C is supplied to the input terminal of the OR gate 5, the 5-bit data of D14 to D10 of the memory C is supplied to the digital comparator D as address information, and the data of D1 and D0 of the memory C are 2-bit data is supplied to the frame counter E ₁ as preset data.

The operation of the serial data receiving apparatus thus configured will be described with reference to the explanatory diagram of the serial data frame in FIG. 2 and the timing chart of the main part in FIG.

First, FIG. 2 shows a format of a data string supplied to the serial data input terminal 3. The first to fourth frames are each composed of an 8-bit data string.

B0 of lower 2 bits of the first frame which is the first frame
And B1 represent the number of succeeding frames, 5 bits from B2 to B6 represent a designated address, and B7 of the most significant bit is serving information for each block receiving serial data, or B2 to B6 These bits are used as identification bits for distinguishing whether or not the information is for a specific block represented by the five bits. When B7 of the most significant bit is "1", it indicates that the following data is common information.

The second to fourth frames each include information to be received.

Next, in FIG. 3, A is the serial clock terminal 1
B, the reset signal waveform supplied from the reset terminal 7, C, D, E, and F each represent the output signal waveform of each bit of the shift register A,
The output signal waveforms of each bit of G and H are both counters B, I is the output signal waveform of frame update flip-flop 4, J is an output signal waveform of the determination permission flag E _5, K is the frame counter E ₁ the first bit of the output signal waveform, L is the second bit of the output signal waveform of the frame counter E _1, M
Is an output signal waveform of the AND gates E _3, N is the output signal waveform of the interrupt request flip-flop E _4, O is the timing data supplied from the serial data input terminal 3 is loaded into memory C, respectively.

When serial data reception is started according to the present embodiment, the level of the reset terminal 7 is shifted to “1”,
The state of the shift register A is reset to [0001], and the counter B and the frame update flip-flop 4 are reset. In this case, the reset terminal 7 is generally supplied with a reset signal by software or a signal indicating a transmission start position of serial data.

Then, if a receiving clock signal is supplied to the serial clock terminal 1, the parallel output value of the shift register A is shown by C to F in FIG. 3 every time the leading edge (leading edge) of the clock signal arrives. So, [1000], [01
[0000], and the number of circulations of the output value is counted.

Then, the output state of the counter B also changes to G and H in FIG.
, The bit position of the data written from the serial data input terminal 3 to the memory C is also sequentially switched from the most significant bit to the least significant bit.

As described above, the timing signal generation circuit F transfers the memory C
When the timing signal supplied to the input terminal becomes active, the received data is written to the selected bit position. That is, the shift register A outputs the parallel output value [000
1], when the output of the first bit of the counter B becomes “0”, the level of the D terminal of the frame update flip-flop 4 shifts to “1”, so that the clock signal supplied from the serial block terminal 1 When the trailing edge of ( ₁ ) arrives at time t1, the output level of the frame update flip-flop 4 shifts to "1" as shown by I in FIG.

Meanwhile, the output signal of the frame update flip-flop 4 is a clock signal of the frame counter E ₁ and interrupt request flip-flop E _4, when the output of the frame counter E ₁ is [00], the OR gate E ₂ output Level is also "0"
Since the output level of the frame counter E ₁ and interrupt request flip-flop E ₄ is not changed.

On the other hand, the output level of the determination permission flag E ₅ is is "1", the digital comparator D is a self-address data via the data bus 2 so far has been supplied to one input terminal group CH _A comparing the address information supplied from the memory C to the other input terminal group CH _B. When they match, the output level from the comparison output terminal CMP of the digital comparator D shifts to “1”, so that the output level of the AND gate E ₃ shifts to “1” and the frame counter E ₁ It is preset to a value supplied from the memory C.

For example, at time t _1, if preset data supply [10] from the memory C, the frame counter E ₁
The count value of [1] as shown by K and L in FIG.
0].

Further, at time t _2, the the trailing edge of the clock signal supplied from the serial clock terminal 1 arrives, the processing proceeds to the output level of the frame update flip-flop 4 is "0", the preset period of the frame counter E ₁ finish.

Meanwhile, 8-bit data of the second frame from the time t ₁ is gradually stored in the lower byte of the memory C, but time
In t _3, when the trailing edge of the clock signal supplied from the serial clock terminal 1 arrives, the time t ₁
As in the case of (1), the output level of the frame update flip-flop 4 shifts to "1". However, since the output level of the OR gate E ₂ is made at this time "1", the frame counter E ₁ went down count, frame counter
The output of the E ₁ together with becomes [01], the interrupt request output level of the flip-flop E ₄ is shifted to "1", an interrupt request signal is sent to the microprocessor, the microprocessor starts the interrupt processing routine. Then, the output level of the clear terminal 8 is shifted temporarily to "1" by the interrupt processing routine, the interrupt request with the flip-flop E ₄ is reset, goes to the output level of the block select terminal 12 is "1" Therefore, the bus switcher G reads the received data from the memory C via the data bus.

Further, at time t _4, the trailing edge of the clock signal supplied from the serial clock terminal 1 arrives, as in the case of time t _3, the output level of the interrupt request flip-flop E ₄ is shifted to "1" Then, the microprocessor starts an interrupt processing routine. At the same time, since the count value of the frame counter E ₁ becomes [00], thereafter as long as the initialization signal is not supplied from the reset terminal 7, the interrupt processing request signal is not output.

That is, since the frame counter E ₁ counts the number of update clocks from the frame update flip-flop 4 by the number of frames based on the data length information read into the memory C, it is possible to easily process variable-length data of an arbitrary number of frames. Can be.

On the other hand, the result of the comparison of the address of the digital comparator D at time t _1, if no address match, does not change from the AND output level of the gate E ₃ is "0", the interrupt request flip-flop E ₄ interrupts Does not output request signal.

In contrast, in the first frame of the head of the serial data, if the data stored in the most significant bit D15 of the memory C is "1", the comparison result of the output level of the AND gate E ₃ is a digital comparator D Regardless of this, it becomes "1" and the same processing as when the addresses match is performed.

Thus, according to this embodiment, on enable easy processing of the variable length data with addresses, the interrupt request flip-flop E ₄ generates an interrupt request signal to the microprocessor, interrupt processing thus one frame Every time the reception of the received data is completed. Of course, if the capacity of the memory C is large, the processing of the received data can be performed all at once after the reception of several frames is completed.

Moreover, distinction according to the present embodiment, the determination permission flag E ₅ and the top frame of the serial data and the succeeding frame,
That is, since the address portion and the data portion can be clearly distinguished from each other, there is no possibility that the address information and the general information intersect and cause a malfunction.

Further, according to the present embodiment, if the memory C has a capacity capable of storing data for two frames, the microprocessor can perform data processing of consecutive frames without burden.

For example, in Figure 3, the reading of the data of the second frame received during the period from the time t ₁ to time t _3, the time t ₄
It is only necessary to do so until the load on the microprocessor is reduced. Therefore, the interrupt request flip-flop
By replacing E ₄ to the normal event flag, it is also possible to process the received data interrupt a program that does not use.

Further, according to the present embodiment, the odd-numbered frame data and the even-numbered frame data of the serial data are used by the counter B to store the first storage area from D15 to D8 of the memory C and the second storage area from D7 to D0. And is stored separately.

FIG. 4 is a circuit diagram showing a specific configuration of the memory C.
Unit memory cell includes an inverter C _1, is constituted by a 3-state inverter C _2.

For example, at the level of the serial data read clock input terminal C ₃₀ of FIG. 1 is "1", the level of the AND gate C ₃ in which the output signal of the parallel output signals and the counter B is supplied from the shift register A "1" Then, a three-state inverter
C ₄ becomes the active state, data SDA from the serial data input terminal 3 is written into the memory cell via the SI terminal of Figure 4.

Incidentally, the timing signal generation circuit F is used to set the timing at which data from the serial data input terminal 3 is read into the memory C. However, since the specific configuration is not the gist of the present invention, FIG. 5 shows a specific configuration of the timing signal generation circuit, and FIG. 6 shows only a timing chart of the timing signal generation circuit of FIG.

In the present embodiment, determination permission flag E ₅ is and the input of the reset side becomes an edge-operated, but which can also be easily realized, because the specific configuration is not the gist of the present invention 7 shows only a specific circuit configuration of the discrimination permission flag.

(Effect of the Invention) As described above, continuous N supplied from the serial data input terminal 3
A reception buffer memory C for M frames (two frames in the present embodiment) in which a data string of a frame (four frames in the present embodiment) is converted in parallel and stored, and the address information stored in the reception buffer memory C is a self-address. Address discriminating means (digital comparator D in this embodiment) for judging whether or not the data coincides with an update clock generating means (in this embodiment, outputting a frame updating clock every time reception of one frame of data is completed). An update flip-flop 4) and, in response to a coincidence signal from the address determination means, a reception frame number setting means for sending an interrupt request signal synchronized with the update clock to the microprocessor for a frame period based on the data length information of the reception data to the microprocessor (In the present embodiment, the reception frame number setting block E) and the interrupt request signal. Ku connection means for transmitting the data stored in the receiving buffer memory to the data bus by the instruction from the microprocessor (bus switcher G in this embodiment)
According to the present invention, since it is possible to clearly distinguish between the address portion and the data portion, processing of variable-length data with an address can be easily performed, and
Since the interrupt processing of the microprocessor is repeated every time reception of one frame is completed, the microprocessor has a special effect that data processing of continuous frames can be performed without burden.

[Brief description of the drawings]

FIG. 1 is a block diagram of a serial data receiving apparatus according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a frame of serial data, FIG. 3 is a timing chart of main parts of an embodiment of the present invention, FIG. 4 is a circuit diagram showing the configuration of the memory, and FIG.
FIG. 13 is a circuit diagram showing a configuration of a timing signal generation circuit, and FIG.
FIG. 7 is a timing chart of the timing signal generation circuit of FIG. 5, and FIG. 7 is a circuit diagram showing a configuration of the discrimination permission flag. 3 ... serial data input terminal, 4 ... frame update flip-flop, B ... counter, C ... memory, D ...
… Digital comparator, E… Reception frame number setting block, E ₄ … Interrupt request flip-flop, E ₅ …
... A determination permission flag.

Claims (1)

(57) [Claims] 1. An M converter for parallel-converting and storing a data sequence of N consecutive frames supplied from a serial data input terminal.
A reception buffer memory for a frame (where 1 <M <N); an address discrimination means for discriminating whether or not the address information stored in the reception buffer memory coincides with a self-address; Update clock generating means for outputting a frame update clock every time the processing is completed; and an interrupt request synchronized with the update clock for a frame period based on data length information of received data in response to a coincidence signal from the address determination means. Means for setting the number of received frames for transmitting a signal to a microprocessor; and connecting means for transmitting data stored in the reception buffer memory to a data bus in accordance with an instruction from the microprocessor based on the interrupt request signal. Receiver.