JP2573295B2 - Electrostatic withstand voltage evaluation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to, for example, applying an electrostatic surge to a semiconductor device in a package charging method, and then removing a charge on the semiconductor device to thereby remove static electricity from the semiconductor device. The present invention relates to an electrostatic withstand voltage evaluation method for evaluating withstand voltage.

(Prior art) Conventionally, technologies in such a field include “Monthly Semico
nductor World ”, (198
7-8) There was one described in Press Journal Co., Ltd., “Electrostatic Discharge Model and Test Method”, pp. 75-81. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a block diagram showing an electrostatic withstand voltage evaluation method of the conventional electrostatic withstand voltage evaluation device in the package charging method, and FIG. 3 is a perspective view of the electrostatic withstand voltage evaluation device of FIG.

The electrostatic withstand voltage evaluation device includes a high voltage power supply 2 for applying a high voltage to the semiconductor device 1, an electrode 3, a discharge bar 4, and a static elimination bar 5, and a resistance between the static elimination bar 5 and the ground 6. 7
Is provided. With the electrostatic withstand voltage evaluation apparatus thus configured, an electrostatic withstand voltage evaluation test of the semiconductor device 1 (ie,
The electrostatic withstand voltage evaluation method is performed in the following sequence (1) to (8).

(1) The semiconductor device 1 is placed on the electrode 3 and the semiconductor device 1 is fixed by the IC presser 8.

(2) Apply a DC voltage from the high voltage power supply 2.

(3) The discharge bar 4 is moved by an XY table (not shown) and brought into contact with the terminal under test 1-1 of the semiconductor device 1 to perform a discharge test.

(4) Discharge bar 5 is connected to terminal under test 1-1 of semiconductor device 1
To all the terminals 1-2 including.

(5) Raise the discharge bar 4 and separate it from the terminal under test 1-1.

(6) Cut off the high voltage power supply 2 and set it to the ground potential.

(7) The failure of the semiconductor device 1 is determined via the static elimination bar 5.

(8) Separate the static elimination bar 5 from all the terminals 1-2.

In the above-described sequence of the package charging method, when the discharge bar 4 comes into contact with the terminal under test 1-1, a discharge phenomenon occurs between the two, and a charge transfer occurs. Next, when the static elimination bar 5 contacts all the terminals 1-2, the semiconductor device 1
Since both the charge removing bar 5 and the charge removing bar 5 are at the ground potential, no charge moves. Next, when the high voltage power supply 2 is cut off to the ground potential, the electric charges charged in the semiconductor device 1 are removed from the charge removing bar 5.
The electric charge guided to the application electrode 3 side moves to the high-voltage power supply 2 side via the. At the time of this charge transfer, the power supply potential is set at an appropriate falling speed so as not to apply stress to the semiconductor device 1, and a resistance 7 of about 1 MΩ is inserted in series in the static elimination bar 5.

Further, as described in the above-mentioned document, the electrostatic withstand voltage evaluation apparatus has the configuration shown in FIGS. 2 and 3 in order to eliminate the effects of the stray capacitance of the semiconductor device 1 and the wiring capacitance of the test circuit. It is designed to faithfully reproduce the electrostatic breakdown phenomenon in the market field.

(Problems to be Solved by the Invention) However, according to the conventional electrostatic withstand voltage evaluation method, the above-described electrostatic withstand voltage evaluation is performed for a semiconductor device whose destruction phenomenon and destruction characteristics change due to various types of sealing packages. However, there is a problem that it is difficult to perform the same test sequence equally. Hereinafter, the problem will be described with reference to FIGS.

FIG. 4 is a configuration diagram showing a conventional method for evaluating electrostatic withstand voltage of an IC card, FIG. 5 is data on breakdown voltage with respect to the length of the discharge bar tip, and FIGS. 6 (a) and (b) are shape diagrams of the discharge bar. 7A shows a DIP-type discharge bar and FIG. 7B shows a flat-type discharge bar. FIG. 7 is a block diagram showing a method for evaluating the electrostatic withstand voltage of a flat package type semiconductor device. FIG. FIG.

In FIG. 4, on the electrode 11 of the electrostatic withstand voltage evaluation device,
An IC card 13 having a terminal 12 is fixed. When performing the above-described sequences (3) and (4) of the electrostatic withstand voltage evaluation test on the IC card 13, the tip length L of the discharge bar 14
And the height H from the tip of the static elimination bar 15 to the IC card 13, both cause electrical and mechanical interference.

That is, if the length L is long, high breakdown voltage data of the IC card 13 is obtained, and it becomes impossible to accurately simulate an electrostatic breakdown model of a semiconductor device by the original package charging method.
For example, as shown in FIG. 5, when the length L exceeds about 2 mm, the destruction withstand voltage value sharply increases, and the actual state is not reflected. Therefore, the normal length L is limited to 2 mm or less, and depending on the form of the sealed package of the semiconductor device to be tested, for example, discharges of various shapes as shown in FIGS. The bar has been devised. These are set so as not to cause a difference in breakdown voltage as much as possible.

If the height H is low, a discharge may occur between the static elimination bar 15 and the terminal 12 while the high-voltage power supply 16 is being applied. Therefore, it is necessary to take a sufficient height H, but the vertical drive stroke of the static elimination bar 15 is also limited, and is usually about 5 mm.

Thus, the tip length L of the discharge bar 14 and the static elimination bar 15
It is extremely difficult to contact the fine terminals 12 with each other so as not to interfere with each other, and it is difficult to realize the sequences (3) and (4). there were.

Similar problems also existed in the static withstand voltage evaluation test of the flat package type semiconductor device shown in FIGS. 7 and 8. In the figure, a static elimination bar 19 has a structure capable of simultaneously contacting all terminals 20 of the flat package type semiconductor device 18 fixed on an electrode 17 by circular motion.

In this case, the flat length Lf of the terminal 20 is 0.5 to 1
mm, and the diameter D of the tip of the discharge bar 21 is 0.6 m.
m, the discharge bar 21 is placed on the extremely narrow flat portion of the terminal 20 when the above-mentioned sequences (3) and (4) are performed.
And the static elimination bar 19 coexist almost without margin. Therefore, mechanical interference between the discharge bar 21 and the static elimination bar 19 may be caused, and the static elimination bar 19 may be deformed. Further, when the charge removing bar 19 also functions as a test terminal for failure determination of the semiconductor device 18, there is a problem that accurate failure determination cannot be performed due to poor contact caused by the deformation.

An object of the present invention is to provide a static elimination method in which a static elimination bar is simultaneously contacted with all terminals of a semiconductor device. Accordingly, it is an object of the present invention to provide an electrostatic withstand voltage evaluation method that solves the difficulty in performing an electrostatic withstand voltage evaluation test that faithfully reproduces an electrostatic breakdown phenomenon.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a method for evaluating an electrostatic withstand voltage, comprising the steps of: A discharge bar contacting step of contacting a terminal to be tested among the power supply terminal, the ground terminal, and the input / output terminal with a discharge bar to which a second voltage has been applied; In a state where the discharge bar is kept in contact with the terminal under test in the bar contact step, at least one of the power terminal, the ground terminal, and the input / output terminal, excluding the terminal under test, Contacting the static elimination bar with the semiconductor device; and applying the first voltage applied to the semiconductor device contacted by the static elimination bar.
And removing the electric charges charged in the semiconductor device via the static elimination bar, and determining the failure of the semiconductor device.

(Operation) According to the present invention, after a first voltage is applied to, for example, a package of a semiconductor device by a high-voltage power supply, in a discharge bar contacting step, the discharge bar to which the second voltage is applied is connected to the semiconductor device. For example, a discharge test is performed in which the semiconductor device is brought into contact with a terminal to be tested and charge is accumulated in the semiconductor device. After performing the discharge test, the static elimination bar is brought into contact with terminals other than the terminal under test in the semiconductor device while maintaining the state where the discharge bar is in contact with the terminal under test. At this time, since the discharge bar and the static elimination bar do not contact the same terminal, no mechanical interference occurs between the two bars. Then, for example,
The discharge bar is separated from the terminal under test, the first voltage applied to the semiconductor device is reduced, and the charge on the semiconductor device is removed via the charge removing bar, and then the failure of the semiconductor device is determined.

(Embodiment) FIGS. 1A and 1B show an electrostatic withstand voltage evaluation method of an electrostatic withstand voltage evaluation apparatus according to an embodiment of the present invention. FIG. 1A is a plan view and FIG. ) Is a block diagram.

This electrostatic withstand voltage evaluation method is performed for the package charging method, and the electrostatic withstand voltage evaluation device includes a high-voltage power supply device 31, an electrode 32, a discharge bar 33, and a charge removing bar. The high-voltage power supply 31 has a high-voltage power supply 31-1 and a control device (not shown). The high-voltage power supply 31-1 is connected to the electrode 32 and grounded.

The static elimination bar 34 includes, for example, four static elimination bars 34-1 to 34-34.
-4, each of which can be driven independently. The static elimination bars 34-1 to 34-4 are grounded via resistors 35, respectively.

In the electrostatic withstand voltage evaluation method using the electrostatic withstand voltage evaluation device having the above configuration, the static elimination method includes a power supply terminal of the semiconductor device 36, a ground terminal, and an input / output terminal having a protection circuit between the power supply terminal and the ground terminal. The static elimination is performed from at least one terminal, and the voltage drop speed of the high-voltage power supply 31-1 is controlled by the control device of the high-voltage power supply device 31 at the time of static elimination, so that stress is not applied to the oxide film of the semiconductor element that is vulnerable to electrostatic breakdown. It is like that. An electrostatic withstand voltage evaluation test using such a static elimination method (that is, an electrostatic withstand voltage evaluation method) is performed in the following sequences (i) to (ix).

(I) The semiconductor device 36 is fixed on the electrode 32 and the discharge bar 33
Is moved by an XY table (not shown) to align with the terminal under test 36-1 of the semiconductor device 36.

(Ii) DC high voltage is applied by the high voltage power supply 31-1.

(Iii) The discharge bar 33 is lowered to contact the terminal under test 36-1, and a discharge test is performed.

(Iv) On the four sides of the semiconductor device 36,
At least one of the static elimination bars 34-2 to 34-4 corresponding to the three sides not including 1 is connected to the terminal of the semiconductor device 36.
Contact 36-2. At this time, the static elimination bar contacts at least one of the power terminal, the ground terminal, and the input / output terminal of the semiconductor device 36.

(V) Raise the discharge bar 33 and separate it from the terminal under test 36-1.

(Vi) The high voltage power supply 31-1 is set to the ground potential at a predetermined voltage drop rate by the control device of the high voltage power supply 31.

(Vii) Contact the static elimination bar that is not in contact with the terminal 36-2, and bring all the static elimination bars 34-1 to 34-4 into contact with all the terminals 36-2 including the terminal under test 36-1.

(Viii) The failure of the semiconductor device 36 is determined via all the static eliminating bars 34-1 to 34-4.

(Ix) All the static elimination bars 34-1 to 34-4 are detached from the terminal 36-2 of the semiconductor device 36.

In the above sequence, the discharge bar 33 and the static elimination bar
When the discharge bar 33 is in contact with the terminal under test 36-1 and the discharge bar 33 is in contact with the other terminal 36-2, the discharge bar 34 does not contact the terminal under test 36-1 at the same time.
Are separated from the ten. Therefore, there is no risk of mechanical interference between the discharge bar 33 and the static elimination bar 34, and the above sequence can be easily performed.

In the above electrostatic withstand voltage evaluation test, the high voltage power supply 31-1
The voltage drop speed at the time of cutoff is determined by the following method. Hereinafter, a method of determining the voltage drop speed will be described with reference to FIGS. 9 to 11.

FIG. 9 is a circuit diagram of an input / output terminal of a MOS semiconductor device having a protection circuit, and FIG. 10 is a diagram showing a case where a semiconductor device having the semiconductor device of FIG. 9 is subjected to an electrostatic withstand voltage evaluation test by a package charging method. And FIG. 11 shows a control function of the voltage drop rate.

In FIG. 9, the semiconductor element has a power supply terminal V _DD and a ground terminal V _SS, and has an input / output terminal 42 provided with a protection circuit 41 between them. The protection circuit 41 includes, for example, a diode 43 and a protection resistor 44. MOS like this
In the evaluation of the electrostatic withstand voltage of the structural semiconductor device, the breakdown mode largely depends on the breakdown of the oxide film of the semiconductor device. The equivalent circuit obtained by performing the package charging test on the semiconductor device of FIG. It can be considered as shown in the figure. Therefore, the power supply terminal V _DD , ground terminal V _SS and input / output terminal
The stress at the time of static elimination using any of the methods 42 will be discussed with reference to FIG.

In FIG. 10, when discharging to the input / output terminal, the equivalent resistance of the diode D1 is sufficiently smaller than the total resistance R obtained by combining the protection resistance 44 and the other resistances. Is considered to be maximum after the response time τ of the diode D1. When this maximum voltage is larger than the maximum electric field strength of the oxide film, it is considered that the oxide film is broken.

Therefore, when the high-voltage power supply 45 is cut off, a resistor having a certain magnitude is inserted into this closed loop circuit. Since it involves a semiconductor device, accurate evaluation cannot be performed. Also, if only a resistor is inserted, stress may be applied to the semiconductor element due to the coupling due to the stray capacitance of the discharge circuit.

Therefore, the voltage applied to the oxide film at the time of static elimination may be reduced to the maximum electric field strength or less by controlling the voltage drop rate of the high voltage power supply 45.

Now, assuming that the falling speed of the high-voltage power supply 45 is controlled by V (t) = kt (k: proportional constant), the voltage Vox applied to the oxide film when the high-voltage power supply is cut off is the response time τ of the diode D1.
At time t, which is Is represented by Here, Cp is the package capacity of the semiconductor device.

In equation (1), for example, oxide film capacitance Cox = 0.5F, package capacitance Cp = 5pF, total resistance R = 50Ω, proportional constant k
= -6000 kV / sec and the breakdown voltage Vb of the oxide film Vb = 50 V, the time t required for the voltage Vox applied to the oxide film to reach the breakdown voltage value Vb is t = 5.5 μsec. This time t is sufficiently longer than the response time τ ≦ 5 nsec of the diode D1, and the voltage value of the oxide film at t = 5 nsec is Vox = 2.
71 × 10 ^-2 V.

Thus, the protection circuit between the power supply terminal V _DD and the ground terminal V _SS
The charge elimination method for the semiconductor device having the input / output terminal 42 into which the 41 is inserted makes it possible to reduce the stress on the oxide film due to the relationship between the voltage drop speed and the response speed of the diode D1. The static elimination method via the power supply terminal V _DD and the ground terminal V _SS has no problem because the impedance is very large.

As described above, when the voltage drop rate V (t) = kt, the proportionality constant k that satisfies | Vb | ≫ | Vox | with respect to the breakdown voltage value Vb of the oxide film is obtained, as shown in FIG. V (t) | ≧ | U
If the voltage drop rate at the time of high-voltage power supply cutoff is controlled by the monotonically increasing function U (t) that satisfies (t) |, static electricity can be removed without applying a large stress to the semiconductor element.

As described above, in the present embodiment, the static elimination bar 34 does not approach or contact the discharge bar 33, and therefore, there is no possibility of mechanical interference between the discharge bar 33 and the static elimination bar 34. Moreover, by controlling the voltage drop rate when the high-voltage power supply 31-1 is shut off, it is possible to eliminate static electricity without applying a large stress to the semiconductor element. Therefore, it is possible to cope with semiconductor devices having various types of sealing packages, and it is possible to accurately and easily reproduce the electrostatic breakdown phenomenon.

FIG. 12 is a configuration diagram showing a modification of the electrostatic withstand voltage evaluation method of the present embodiment.

This electrostatic withstand voltage evaluation method uses an IC card 51 having a protection circuit.
In contrast, the discharge bar 52 also serves as a charge elimination bar. The electrostatic withstand voltage evaluation device in this case includes a discharge bar 52,
A high-voltage power supply 53, an electrode 54, and a test bar 55 are provided. The high-voltage power supply 53 includes a high-voltage power supply 53-1 and a control device (not shown). The test bar 55 does not need to be provided when it is not used for failure determination of the IC card 51.

A test sequence by the electrostatic withstand voltage evaluation apparatus is performed as follows.

 The IC card 51 is fixed on the electrode 54.

 A high voltage is applied by the high voltage power supply 53.

The discharge test is performed by bringing the discharge bar 52 into contact with the terminal under test 51-1 of the IC card 51.

The high voltage power supply 53-1 is set to the ground potential at a predetermined voltage drop rate by the control device.

Raise the discharge bar 52 and separate it from the terminal under test 51-1.

The test bar 55 is brought into contact with all the terminals 51-2 including the terminal under test 51-1 of the IC card 51, and the failure of the IC card 51 is determined.

In this manner, substantially the same operations and advantages as those of the electrostatic withstand voltage evaluation method shown in FIGS. 1A and 1B can be obtained.
By allowing the discharge bar 52 to also serve as a static elimination bar,
The configuration and the static elimination operation of the electrostatic withstand voltage evaluation apparatus can be simplified.

The present invention is not limited to the illustrated embodiment, and various modifications are possible, for example, the following modifications.

(A) In FIGS. 1 (a), (b) and FIG. 12, the high voltage power supplies 31 and 53 having the control device are provided, but if a device capable of controlling the voltage drop rate is used. ,
Only the high voltage power supplies 31-1 and 53-1 may be provided.

(B) In FIGS. 1 (a) and 1 (b), the static elimination bar 34 is divided into four parts.
It may be divided into more than or less than the division.

(C) If the semiconductor device has the protection circuit 41, the ninth
It is not limited to the illustrated one. In addition, the protection circuit 41
Is not limited to that shown in the figure, and the present invention can be applied to various semiconductor devices having protection circuits of different configurations.

(Effects of the Invention) As described above in detail, according to the present invention, the test of the semiconductor device is performed while the discharge bar is kept in contact with the terminal to be tested in the discharge bar contact step. The static elimination bar is brought into contact with at least one terminal excluding the terminal to reduce the first voltage applied to the semiconductor device. Therefore, when the static elimination bar contacts the terminal of the semiconductor device, the discharge bar is in contact with the terminal to be tested, so that charges are not accumulated in the semiconductor device, and a highly accurate test can be performed. In addition, since the discharge bar and the static elimination bar do not contact the same terminal, no mechanical interference occurs between the two bars.

Therefore, it is possible to accurately and easily perform an electrostatic withstand voltage evaluation test on semiconductor devices having a variety of sealing package forms, and to faithfully reproduce an electrostatic breakdown phenomenon of a semiconductor device that occurs in a market field.

[Brief description of the drawings]

1 (a) and 1 (b) show an electrostatic withstand voltage evaluation method of an electrostatic withstand voltage evaluation device according to an embodiment of the present invention. FIG. 1 (a) is a plan view and FIG. 1 (b) is a block diagram. 2 is a block diagram showing an electrostatic withstand voltage evaluation method of the conventional electrostatic withstand voltage evaluation device, FIG. 3 is a perspective view of the electrostatic withstand voltage evaluation device of FIG. 2, and FIG. FIG. 5 is a structural diagram showing the evaluation method, FIG. 5 is a breakdown voltage data diagram with respect to the length of the discharge bar tip, FIGS. 6 (a) and (b) are shape diagrams of the discharge bar, and FIG.
The P type and FIG. 7B show a flat type,
FIG. 1 is a configuration diagram showing a method for evaluating the electrostatic withstand voltage of a conventional flat package type semiconductor device. FIG. 8 is an enlarged view of a portion A in FIG.
9 is a circuit diagram of a semiconductor device having a protection circuit, FIG. 10 is an equivalent circuit diagram when an electrostatic withstand voltage evaluation test is performed on the semiconductor device having the semiconductor device of FIG. 9, and FIG. FIG. 12 is a configuration diagram showing a modification of the electrostatic withstand voltage evaluation method according to the embodiment of the present invention. 31,53 high-voltage power supply device, 31-1 to 53-1 high-voltage power supply, 32,54 electrode, 33,52 discharge bar, static elimination bar, 36 semiconductor device 36-1, 51-1 ... terminal under test, 36-2, 51-2 ... terminal, 41 ... protection circuit, 42 ... input / output terminal, V _DD ... power supply terminal, V _SS ... ground terminal , 51 ……
IC card.

Claims (1)

(57) [Claims] A step of applying a first voltage to a semiconductor device having a power supply terminal, a ground terminal, and an input / output terminal by a high-voltage power supply; A discharge bar contact step of contacting a discharge bar to which a second voltage is applied with the terminal under test, and a state in which the discharge bar is kept in contact with the terminal under test in the discharge bar contact step, Contacting a static elimination bar with at least one of the power supply terminal, the ground terminal, and the input / output terminal except for the terminal under test; and applying the static elimination bar to the semiconductor device contacted by the static elimination bar. Lowering a first voltage to remove a charge on the semiconductor device through the static elimination bar, and determining a failure of the semiconductor device.