JP2570459B2 - Pin connection structure - Google Patents
Pin connection structureInfo
- Publication number
- JP2570459B2 JP2570459B2 JP2082707A JP8270790A JP2570459B2 JP 2570459 B2 JP2570459 B2 JP 2570459B2 JP 2082707 A JP2082707 A JP 2082707A JP 8270790 A JP8270790 A JP 8270790A JP 2570459 B2 JP2570459 B2 JP 2570459B2
- Authority
- JP
- Japan
- Prior art keywords
- multilayer wiring
- wiring board
- ceramic multilayer
- substrate
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はピン接続構造、特にセラミック多層配線基板
の外部接続用のピン接続構造に関する。Description: TECHNICAL FIELD The present invention relates to a pin connection structure, and more particularly to a pin connection structure for external connection of a ceramic multilayer wiring board.
従来、この種のピン接続構造は、セラミック基板の表
面に直接ランドを形成し、その上にピンをろう付けなど
により接続させる構造となっている。Conventionally, this type of pin connection structure has a structure in which lands are formed directly on the surface of a ceramic substrate, and pins are connected thereon by brazing or the like.
上述した従来のピン構造は、セラミック基板上に直接
にランドを付けているので、ランドあるいはランド上の
ろう材とセラミックとの熱膨張係数の違いにより、ろう
付け部分にストレスが発生し、セラミック基板の表面、
特に窒化アルミ基板、ガラスセラミック基板のような強
度の小さな基板にクラックが入りやすいという欠点があ
る。In the conventional pin structure described above, since the land is directly provided on the ceramic substrate, stress is generated in the brazed portion due to a difference in thermal expansion coefficient between the land or the brazing material on the land and the ceramic. Surface,
In particular, there is a disadvantage that a crack is easily formed on a substrate having a small strength such as an aluminum nitride substrate or a glass ceramic substrate.
本発明のピン接続構造は、セラミック多層配線基板の
表面に露出し、この基板内部の導電パターンに接続して
内部が導電材料で充填されたスルーホールと、このスル
ーホールに接続される位置に外部接続ピンと前記セラミ
ック多層配線基板との間の熱膨張係数を持つ前記セラミ
ック多層配線基板上のポリイミド樹脂層と、このポリイ
ミド樹脂層の表面のヴィアホール上にヴィアホールを覆
って形成されたランドと、このランド上に外部接続ピン
を接続するろう材とを有することにより構成される。The pin connection structure of the present invention has a through-hole exposed on the surface of a ceramic multilayer wiring board, connected to a conductive pattern inside the board and filled with a conductive material, and an external part at a position connected to the through-hole. A polyimide resin layer on the ceramic multilayer wiring board having a thermal expansion coefficient between the connection pin and the ceramic multilayer wiring board, and a land formed over the via hole on the via hole on the surface of the polyimide resin layer; And a brazing material for connecting external connection pins on the land.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。１はセ
ラミック多層配線基板で、基板内部の導体パターン２が
LSI実装面と外部接続用ピン７の実装面とを結ぶスルー
ホール３に接続されて、スルーホール３は外部接続用ピ
ン７を実装する基板表面に露出している。セラミック多
層配線基板１の熱膨張係数は4.2×10-6/℃である。スル
ーホール３の直径は100〜300μｍであり、スルーホール
ピッチは2.54mmである。スルーホール３および導体パタ
ーン２の材料はタングステン、モリブデン金、銀−パラ
ジウム等が用いられる。基板表面にはポリイミド樹脂層
４が形成されていて、ポリイミド樹脂層４の厚さは２〜
15μｍであり、熱膨張係数は基板とろう材６との間の値
10×10-6/℃のものを選択してある。この樹脂層はスピ
ンコーティングにより基板表面に塗布され、フォトリそ
グラフィーィ技術によりセラミック多層配線基板１の対
応するスルーホール３の位置にヴィアホールが形成され
ている。このときポリイミド樹脂層４のヴィアホール位
置をすべてセラミック多層配線基盤１のスルーホール３
の位置に合わせるのは、セラミック多層配線基板１の焼
成工程での収縮率のばらつきにより大面積の基板ほど難
しくなるため、１辺が2cm以上の基板ではヴィアホール
を基板面内で分割して形成してゆくか、露光用のガラス
マスクのヴィアホールのピッチを基板の収縮率のばらつ
きに合わせて用意するかのどちらかの方法を取らなけれ
ばならない。ポリイミド樹脂層４の膜厚は、厚いほど熱
膨張係数の違いを吸収しやすいのであるが、ヴィアホー
ル部へのヴィアフィルを行わないのでポリイミド樹脂層
４の表面のランド５との接続を確実にするためにも15μ
ｍ以下がよい。ポリイミド樹脂層４の表面に形成された
ランド５は直径1.3mmとなっている。ランド５はスパッ
タ膜のみ、もしくは通常の薄膜導体パターンの形成法に
より、金、銅、ニッケル等のメッキで形成される。スパ
ッタ膜のみでランドを形成する場合は、クロムを1000
Å、パラジウムを4000〜6000Å付けるのがよい。パラジ
ウムの厚さがこれ以下であるとクロムの拡張が進んだ場
合に、クロムがパラジウムの表面まで出てきて外部接続
用ピン７のろう付け時に、ろう材のぬれが悪くなる恐れ
がある。スパッタ膜をランド５の部分だけに選択的に形
成する方法は、スパッタ膜形成時にメタルマスクで表面
をマスキングし必要部分以外にスパッタが付かないよう
にするか、スパッタ膜を全面につけた後にレジストを塗
布し、フォトリソグラフィーにより形成するかである。
メッキにより形成する場合は、この後即ちスパッタ膜を
ランドの形状に形成した後、ランドに接続しているセラ
ミック多層配線基板１のスルーホール３を利用して基板
の裏側からメッキの電極を取っておこなうか、無電解メ
ッキで行うかである。ろう材６は外部接続用ピン７をラ
ンド５に固着させるためのものである。ろう材料は金／
錫:80/20（wt％）の共晶合金（熱膨張係数18×10-6/
℃）が好ましいが、ポリイミドにダメージを与えない範
囲の温度（400℃以下）に融点を持つろう材料ならば何
でも使用できる。ろう材の量はランドの大きさにより変
える必要があるが、上記のランドでは0.8〜0.9mgであ
る。外部接続用ピン７のネイルヘッド部分の直径は0.7m
m、ピン部分の直径は0.35mmである。FIG. 1 is a longitudinal sectional view of one embodiment of the present invention. 1 is a ceramic multilayer wiring board, and a conductor pattern 2 inside the board is
The through-hole 3 is connected to the through-hole 3 connecting the LSI mounting surface and the mounting surface of the external connection pin 7, and the through-hole 3 is exposed on the surface of the substrate on which the external connection pin 7 is mounted. The coefficient of thermal expansion of the ceramic multilayer wiring board 1 is 4.2 × 10 −6 / ° C. The diameter of the through holes 3 is 100 to 300 μm, and the pitch of the through holes is 2.54 mm. Tungsten, molybdenum gold, silver-palladium, or the like is used as the material of the through hole 3 and the conductor pattern 2. A polyimide resin layer 4 is formed on the substrate surface, and the thickness of the polyimide resin layer 4 is 2 to
The coefficient of thermal expansion is a value between the substrate and the brazing material 6.
10 × 10 -6 / ° C is selected. This resin layer is applied to the substrate surface by spin coating, and via holes are formed at the positions of the corresponding through holes 3 of the ceramic multilayer wiring substrate 1 by photolithography. At this time, the positions of the via holes of the polyimide resin layer 4 are all changed to the through holes 3 of the ceramic multilayer wiring board 1.
It is difficult to adjust to the position of the substrate of large area due to the variation of the shrinkage ratio in the firing process of the ceramic multilayer wiring substrate 1. Therefore, in the case of a substrate having one side of 2 cm or more, the via hole is divided in the substrate plane. Or a method of preparing the pitch of the via hole of the glass mask for exposure in accordance with the variation in the contraction rate of the substrate. As the thickness of the polyimide resin layer 4 increases, the difference in the coefficient of thermal expansion can be easily absorbed. However, since the via hole is not filled, the connection of the surface of the polyimide resin layer 4 to the land 5 is ensured. 15μ also to
m or less is good. The land 5 formed on the surface of the polyimide resin layer 4 has a diameter of 1.3 mm. The lands 5 are formed by plating of gold, copper, nickel, or the like, using only a sputtered film or a normal thin film conductor pattern forming method. If lands are formed only with a sputtered film, chrome should be 1000
4000, 4000 ~ 6000 palladium is good. If the thickness of the palladium is less than this, when the expansion of the chromium proceeds, the chrome may come out to the surface of the palladium and the brazing material may be poorly wet when the external connection pins 7 are brazed. A method of selectively forming a sputtered film only on the land 5 is to mask the surface with a metal mask when forming the sputtered film so that spattering is not applied to portions other than necessary portions, or to apply a resist after applying the sputtered film over the entire surface. It is applied or formed by photolithography.
In the case of forming by plating, after this, that is, after forming the sputtered film in the shape of a land, the plated electrode is removed from the back side of the substrate using the through hole 3 of the ceramic multilayer wiring board 1 connected to the land. Or electroless plating. The brazing material 6 is for fixing the external connection pins 7 to the lands 5. The brazing material is gold /
Tin: 80/20 (wt%) eutectic alloy (coefficient of thermal expansion 18 × 10 -6 /
° C) is preferred, but any brazing material having a melting point at a temperature (400 ° C or less) that does not damage the polyimide can be used. The amount of brazing material must be changed depending on the size of the land, but is 0.8 to 0.9 mg in the above-mentioned land. The diameter of the nail head of the external connection pin 7 is 0.7m
m, the diameter of the pin part is 0.35 mm.
なお本実施例ではセラミック多層配線基板１と外部接
続用ピン７とのろう付け部の間に熱膨張係数を調整した
ポリイミド樹脂層４を設け、ろう付け部のストレスを緩
和したのであるが、熱膨張係数をセラミック多層配線基
板１とろう材６との間を必ずしも調整しなくても、ポリ
イミドの持つ弾性によりろう付け部のストレスを少なく
することはできる。In this embodiment, the polyimide resin layer 4 having a controlled thermal expansion coefficient is provided between the brazed portions of the ceramic multilayer wiring board 1 and the external connection pins 7 to reduce the stress of the brazed portions. Even if the expansion coefficient is not necessarily adjusted between the ceramic multilayer wiring board 1 and the brazing material 6, the stress of the brazing portion can be reduced by the elasticity of the polyimide.
以上述べたように本発明は、セラミック多層配線基板
と外部接続用ピンとのろう付け部の間にポリイミド層を
設け、しかもその熱膨張係数を調整することによりセラ
ミック多層配線基板とろう付け部との熱膨張係数の差に
よるストレスの発生を緩和させることができ、基板にク
ラックの生じないピン接続構造を提供できる効果があ
る。As described above, the present invention provides a polyimide layer between the brazing portion of the ceramic multilayer wiring board and the external connection pin, and furthermore, adjusts the coefficient of thermal expansion of the polyimide multilayer wiring board and the brazing portion. It is possible to alleviate the occurrence of stress due to the difference in thermal expansion coefficient, and to provide a pin connection structure that does not cause cracks in the substrate.
第１図は本発明の一実施例の縦断面図である。 １…セラミック多層配線基板、２…導体パターン、３…
スルーホール、４…ポリイミド樹脂層、５…ランド、６
…ろう材、７…外部接続用ピン。FIG. 1 is a longitudinal sectional view of one embodiment of the present invention. 1. Ceramic multilayer wiring board 2. Conductor pattern 3.
Through hole, 4 ... polyimide resin layer, 5 ... land, 6
... brazing material, 7 ... pins for external connection.
Claims (1)
この基板内部の導電パターンに接続して内部が導電材料
で充填されたスルーホールと、このスルーホールに接続
される位置にヴィアホールを配した外部接続ピンと前記
セラミック多層配線基板との間の熱膨張係数を持つ前記
セラミック多層配線基板上のポリイミド樹脂層と、この
ポリイミド樹脂層の表面のヴィアホール上にヴィアホー
ルを覆って形成されたランドと、このランド上に外部接
続ピンを接続するろう材とを有することを特徴とするピ
ン接続構造。1. A method according to claim 1, which is exposed on a surface of a ceramic multilayer wiring board.
Thermal expansion between a through hole connected to a conductive pattern inside the substrate and filled with a conductive material, and an external connection pin having a via hole at a position connected to the through hole and the ceramic multilayer wiring board A polyimide resin layer on the ceramic multilayer wiring board having a coefficient, a land formed over the via hole on the surface of the polyimide resin layer to cover the via hole, and a brazing material for connecting external connection pins on the land. A pin connection structure comprising:
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082707A JP2570459B2 (en) | 1990-03-29 | 1990-03-29 | Pin connection structure |
| CA002036771A CA2036771A1 (en) | 1990-02-22 | 1991-02-20 | Multilayer ceramic wiring substrate and pin connecting structure |
| EP19910102547 EP0443578B1 (en) | 1990-02-22 | 1991-02-21 | Multilayer ceramic wiring substrate and pin connecting structure |
| DE1991612097 DE69112097T2 (en) | 1990-02-22 | 1991-02-21 | Multi-layer ceramic wiring substrate and pin connection structure. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2082707A JP2570459B2 (en) | 1990-03-29 | 1990-03-29 | Pin connection structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03283274A JPH03283274A (en) | 1991-12-13 |
| JP2570459B2 true JP2570459B2 (en) | 1997-01-08 |
Family
ID=13781877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2082707A Expired - Lifetime JP2570459B2 (en) | 1990-02-22 | 1990-03-29 | Pin connection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2570459B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ES2375115T3 (en) | 2005-03-31 | 2012-02-24 | Suntory Holdings Limited | EMULSION OF WATER OIL CONTAINING A LIGNANE COMPOSITE AND COMPOSITION THAT INCLUDE THE SAME. |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01100958A (en) * | 1987-10-14 | 1989-04-19 | Hitachi Ltd | Resin-coated ceramic wiring board |
-
1990
- 1990-03-29 JP JP2082707A patent/JP2570459B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03283274A (en) | 1991-12-13 |
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