JP2569874B2 - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JP2569874B2
JP2569874B2 JP5411890A JP5411890A JP2569874B2 JP 2569874 B2 JP2569874 B2 JP 2569874B2 JP 5411890 A JP5411890 A JP 5411890A JP 5411890 A JP5411890 A JP 5411890A JP 2569874 B2 JP2569874 B2 JP 2569874B2
Authority
JP
Japan
Prior art keywords
circuit
hybrid integrated
integrated circuit
circuit board
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5411890A
Other languages
Japanese (ja)
Other versions
JPH03255651A (en
Inventor
直治 仙波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5411890A priority Critical patent/JP2569874B2/en
Publication of JPH03255651A publication Critical patent/JPH03255651A/en
Application granted granted Critical
Publication of JP2569874B2 publication Critical patent/JP2569874B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路に関する。Description: FIELD OF THE INVENTION The present invention relates to a hybrid integrated circuit.

〔従来の技術〕[Conventional technology]

一般的な混成集積回路について、図面を参照して説明
する。A general hybrid integrated circuit will be described with reference to the drawings.

第３図は平面図、第４図は第３図のＣ−Ｄ断面図であ
る。FIG. 3 is a plan view, and FIG. 4 is a sectional view taken along line CD of FIG.

回路基板１は42合金（Fe:58％,Ni:42％）または銅合
金（Cu 99％以上に強度を増すための微量のSn,Ni,Znな
どを添加したもの）からなるヒートシンクに、厚さ18〜
35μｍの銅箔回路が形成されたガラスエポキシ板を貼り
合わせたものである。The circuit board 1 is provided with a heat sink made of 42 alloy (Fe: 58%, Ni: 42%) or copper alloy (Cu to which 99% or more is added with a small amount of Sn, Ni, Zn, etc.) 18 ~
A glass epoxy plate on which a 35 μm copper foil circuit is formed is attached.

チップ状の抵抗、コンデンサ、コイルなどの受動素子
は、半田付けによって回路基板へのマウントと回路パタ
ーンへのボンディング（結線）とを兼用していることが
多い。Passive elements such as chip-shaped resistors, capacitors, and coils often serve both as mounting on a circuit board by soldering and as bonding (connection) to a circuit pattern.

ダイオード、トランジスタ、モノリシックICなどの能
動素子は、導電性の銀ペーストまたは絶縁性ペーストで
回路基板にマウントしてから、150℃以下の温度でAu細
線を用いたUS・NTCボンディングされているのが普通で
ある。Active elements such as diodes, transistors, and monolithic ICs are mounted on a circuit board with conductive silver paste or insulating paste, and then are subjected to US / NTC bonding using Au thin wires at a temperature of 150 ° C or less. Normal.

このように受動・能動素子４が搭載され、半田や金属
細線５などにより結線したのち、エポキシ樹脂などから
なる外装樹脂６がトランスファーモールド法、ディップ
法、ポッティング法などで形成されている。After the passive / active elements 4 are mounted and connected by solder or thin metal wires 5, an exterior resin 6 made of epoxy resin or the like is formed by a transfer molding method, a dip method, a potting method, or the like.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

従来の混成集積回路においては、回路基板と外装樹脂
との密着性や回路基板の材質によっては、回路基板中に
水分が浸透して、回路パターンや受動・能動素子を酸化
したり腐蝕するなどの問題があり、信頼性が極めて低か
った。In conventional hybrid integrated circuits, depending on the adhesion between the circuit board and the exterior resin and the material of the circuit board, moisture may penetrate into the circuit board and oxidize or corrode circuit patterns and passive / active elements. There was a problem and the reliability was extremely low.

本発明の目的は、回路基板を追加加工することによ
り、混成集積回路の耐湿性を改善して、信頼性を向上を
計るものである。An object of the present invention is to improve the moisture resistance of a hybrid integrated circuit and improve the reliability by additionally processing a circuit board.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の構成は、回路基板に受動・能動素子を搭載し
て、半田や金属細線などにより結線したのち、外装樹脂
封止した混成集積回路において、前記回路基板の樹脂封
止領域内の外部回路接続用端子の近傍に千鳥状に配列し
た開口部が設けられ、これら開口部間の間隙を狭くする
と共に、その間隙に内部回路から前記外部回路接続用端
子へ接続する配線が設けられたことを特徴とする。In a hybrid integrated circuit in which a passive / active element is mounted on a circuit board and connected by solder or a thin metal wire, and then externally sealed in a resin-encapsulated region of the circuit board, Openings arranged in a zigzag pattern are provided in the vicinity of the connection terminals, narrowing the gap between these openings, and providing wiring for connecting the internal circuit to the external circuit connection terminal in the gap. Features.

〔実施例〕〔Example〕

本発明の一実施例について、図面を参照して説明す
る。An embodiment of the present invention will be described with reference to the drawings.

第１図は平面図、第２図は第１図Ａ−Ｂ断面図であ
る。FIG. 1 is a plan view, and FIG. 2 is a cross-sectional view of FIG. 1A-B.

回路パターン２を形成した回路基板１には、外部回路
接続用端子７の近傍に千鳥状に配列した複数の開口部３
が設けられている。In the circuit board 1 on which the circuit pattern 2 is formed, a plurality of openings 3 arranged in a zigzag pattern near the external circuit connection terminals 7 are provided.
Is provided.

この開口部３の配列は、回路パターン２に含まれるス
ルーホールなどの配列とは違って回路によって制約を受
けることが少ないので、同一規模の混成集積回路につい
ては標準化することが可能であり、回路基板１の加工に
必要な打抜金型を共通にすることができる。The arrangement of the openings 3 is unlikely to be restricted by the circuit unlike the arrangement of through holes and the like included in the circuit pattern 2, so that a hybrid integrated circuit of the same scale can be standardized. A punching die required for processing the substrate 1 can be shared.

〔発明の効果〕〔The invention's effect〕

混成集積回路に含まれる回路基板の外部回路接続用端
子の近傍に、千鳥状に開口部を配列して、外装樹脂封止
することにより、回路基板に水分が浸透することによる
劣化を防ぎ、信頼性の向上を計ることができた。The openings are arranged in a zigzag pattern near the external circuit connection terminals of the circuit board included in the hybrid integrated circuit, and are sealed with an exterior resin to prevent deterioration due to the penetration of moisture into the circuit board, thereby improving reliability. I was able to improve the sexuality.

本発明の効果は、金属ヒートシンク貼り付けプリント
基板のエポキシ樹脂封止に限定されることなく、セラミ
ック製や硬質ガラス製の回路基板のシリコン樹脂封止な
どにも適用範囲を拡げることが可能である。The effect of the present invention is not limited to the epoxy resin sealing of the printed circuit board to which the metal heat sink is attached, but can also be applied to a silicone resin sealing of a circuit board made of ceramic or hard glass. .

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明の一実施例を示す平面図、第２図は第１
図のＡ−Ｂ断面図、第３図は従来技術を示す平面図、第
４図は第３図のＣ−Ｄ断面図。 １……回路基板、２……回路パターン、３……開口部、
４……受動・能動素子、５……金属細線、６……外装樹
脂、７……外部回路接続用端子。FIG. 1 is a plan view showing an embodiment of the present invention, and FIG.
FIG. 3 is a sectional view taken along the line AB in FIG. 3, FIG. 3 is a plan view showing the prior art, and FIG. 4 is a sectional view taken along the line CD in FIG. 1 ... circuit board, 2 ... circuit pattern, 3 ... opening,
4 Passive / active element, 5 Metal thin wire, 6 Exterior resin, 7 External circuit connection terminal.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】回路基板に受動・能動素子を搭載して、半
田や金属細線などにより結線したのち、外装樹脂封止し
た混成集積回路において、前記回路基板の樹脂封止領域
内の外部回路接続用端子の近傍に千鳥状に配列した開口
部が設けられ、これら開口部間の間隙を狭くすると共
に、その間隙に内部回路から前記外部回路接続用端子へ
接続する配線が設けられたことを特徴とする混成集積回
路。1. A hybrid integrated circuit in which passive and active elements are mounted on a circuit board and connected by soldering or thin metal wires, and then externally connected in a resin-sealed region of the circuit board in a resin-sealed hybrid integrated circuit. Openings are provided in the vicinity of the terminals for staggering, the gaps between these openings are narrowed, and the gaps are provided with wiring for connecting the internal circuit to the external circuit connection terminals. A hybrid integrated circuit.
JP5411890A 1990-03-05 1990-03-05 Hybrid integrated circuit Expired - Lifetime JP2569874B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5411890A JP2569874B2 (en) 1990-03-05 1990-03-05 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5411890A JP2569874B2 (en) 1990-03-05 1990-03-05 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPH03255651A JPH03255651A (en) 1991-11-14
JP2569874B2 true JP2569874B2 (en) 1997-01-08

Family

ID=12961683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5411890A Expired - Lifetime JP2569874B2 (en) 1990-03-05 1990-03-05 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JP2569874B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57178449U (en) * 1981-05-06 1982-11-11

Also Published As

Publication number Publication date
JPH03255651A (en) 1991-11-14

Similar Documents

Publication Publication Date Title
US6002165A (en) Multilayered lead frame for semiconductor packages
US5467252A (en) Method for plating using nested plating buses and semiconductor device having the same
KR0184588B1 (en) Multi-layer lead frames for integrated circuit packages
US20060148317A1 (en) Semiconductor device
JPH0445981B2 (en)
US7102211B2 (en) Semiconductor device and hybrid integrated circuit device
US6297964B1 (en) Semiconductor device, method of fabricating the same film carrier tape, circuit board, and electronic apparatus
WO2004114405A1 (en) Micro lead frame package and method to manufacture the micro lead frame package
JP2569874B2 (en) Hybrid integrated circuit
JPH0232558A (en) Resin-sealed multi-chip hybrid integrated circuit
JP3396541B2 (en) Circuit board mounted with hybrid integrated circuit device
JP2798108B2 (en) Hybrid integrated circuit device
JP3297959B2 (en) Semiconductor device
JPS58178544A (en) Lead frame
JP3576228B2 (en) Surface mount type semiconductor device
US20220396474A1 (en) Semiconductor package with metal column mold barrier
JP2737332B2 (en) Integrated circuit device
JPS63146453A (en) Semiconductor package and manufacture of same
KR100235496B1 (en) Semiconductor package
JP2652222B2 (en) Substrate for mounting electronic components
JPH0529539A (en) Multi-chip module
JP2822446B2 (en) Hybrid integrated circuit device
JP4296916B2 (en) Semiconductor device
JP3193788B2 (en) Substrate for mounting electronic components
JPH0451488Y2 (en)