JP2569577B2 - Line quality monitoring device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a line quality monitoring device for a digital transmission line in operation.

[Prior Art] Conventionally, the line quality of a digital transmission line in operation is monitored by parity.

Generally, it is expected that the line quality during line operation is quite good, and in this state, the bit error rate (Bit Error
In order to obtain (Rate), it is necessary to accumulate parity errors over a long period of time. On the other hand, when the line quality is rapidly deteriorated due to fading, in order to obtain a correct bit error rate, it is necessary to separately perform calculation and derivation separately when the line quality is good and when the line quality is deteriorated.

In addition, a state in which the line quality is poor generally does not last for a long time. Therefore, when obtaining the bit error rate, it is necessary to change the monitoring cumulative time according to the line quality. As a method of easily realizing this, there is a method of terminating the accumulation when the accumulation of the detected parity errors exceeds a set value.

[Problems to be Solved] However, in the method of terminating the accumulation when the accumulation of the detected parity errors exceeds a set value, if the line is stable, the parity errors are averaged within the accumulation time. Occurs, and the correct bit error rate can be obtained.However, if fading occurs during accumulation of parity errors and the line quality deteriorates, the parity errors increase rapidly due to fading. When the bit error rate exceeds the value, the bit error rate becomes an average value between the good state and the bad state of the line quality, and there is a disadvantage that the value is not correct.

The present invention has been made in view of the above problems,
It is an object of the present invention to provide a line quality monitoring apparatus that can obtain a correct bit error rate value by obtaining a bit error rate in a case where the line quality is good and a bit error rate in a case where the line quality is deteriorated while minimizing the influence of each.

[Means for Solving the Problems] In order to achieve the above object, the line quality monitoring apparatus of the present invention connects multiple stages of parity error adders having different upper limits of the accumulated time, and adds adders having a shorter upper limit of the accumulated time. The result is constituted by an adder which is added to an adder having a long upper limit of the accumulated time.

More specifically, a parity error counting circuit, a time base oscillator for generating a counting unit time, and a parity error adder for cumulatively adding the parity errors output from the counting circuit are connected in series, and the time base oscillator Means for cascade-connecting an accumulative time adder for accumulatively adding the counting unit time output from the unit, and further adding a result to the next-stage adder of the parity error and the accumulative time every time the accumulative time exceeds a certain value. When the cumulative number of parity error adders in each stage exceeds a certain value or when the total cumulative time exceeds a certain value, the calculation of the bit error rate is started from the result of each adder. .

Example Next, an example of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of one embodiment of the present invention.

Reference numeral 1 denotes a parity error pulse input terminal. 2 is a counter for counting the number of parity error pulses from the input terminal. Reference numeral 3 denotes a time base oscillator that generates a counting unit time of the accumulated time. 4-1 to 4-4 are parity error adders. Reference numerals 5-1 to 5-4 denote cumulative time adders. 6-
Reference numerals 1 to 6-4 denote comparators.
, And 5-4 are compared with a fixed value, and when the content of the adder 5-n exceeds the fixed value, the parity error adder 4-n and the accumulated time adder 5-n respectively add the next stage. Container 4- (n +
1) Add the addition result to 5 (n + 1). At this time, the previous-stage adders 4-n and 5-n are reset.

Reference numeral 7 denotes a switch for monitoring the results of the parity error adders 4-1 to 4-4. The contents of the adders 4-1 to 4-4 are input to the comparator 8. Here, the cumulative number of parity errors is compared with a fixed value, and when the cumulative number exceeds the fixed value, the calculation of the bit error rate is started. 9 is a bit error rate calculator, and 10 is a storage device for the result.

 Next, the operation of the above-described quality monitoring device will be described.

First, it is assumed that the line quality is good. The number of parity errors is accumulated in the adder 4-1 and the accumulated time is accumulated in the adder 5-1. When the accumulated time exceeds a certain value, the accumulated result of the parity error is added to the adder 4-2, and the accumulated time is added to the adder 5-2. As described above, the result is successively added to the next-stage adder, and is finally accumulated in the adders 4-4 and 5-4. When the accumulated time exceeds a certain value, the bit error rate is calculated and stored.

Next, a case will be described with reference to FIG. 2 assuming a case where the line quality has rapidly deteriorated from a good state due to fading.

FIG. 2 (a) shows the contents of the cumulative time adder when the line quality suddenly deteriorates from a good state, and FIG. 2 (b)
Indicates the contents of the parity error adder.

Due to the rapid deterioration of the line quality, a large amount of parity errors are accumulated in the adder 4-2 despite the short-time accumulation. This state is compared and detected by the comparator 8 via the switch 7, and the calculation of the bit error rate is started. The calculation of the bit error rate is performed by adding the cumulative result in a state of good line quality to the adder 4-3,
4-4, 5-3, and 5-4 are performed first, and then, the accumulation results in a state where the channel quality is deteriorated are obtained from the adders 4-2 and 5-2. The results separately calculated in this way are stored in the storage device 10.

Although the embodiment shown here is realized by hardware, it is also possible to realize this hardware by using a microcomputer and replacing it with software logic.

[Effects of the Invention] As described above, the present invention cascade-connects adders in which the accumulated time of parity error monitoring is changed stepwise so that the case where the line quality is good and the case where the line quality is deteriorated are It is possible to monitor and record the line quality while minimizing the influence of each, and it is possible to obtain a correct bit error rate.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention, FIG. 2 (a) is an explanatory diagram of an accumulated time adder in a state where the line quality is rapidly deteriorated from a good state, and FIG. FIG. 3 is an explanatory diagram of a parity error adder. 2: Calculator, 3: Time base oscillator 4-1 ..., 4-4: Parity error adder 5-1 ......, 5-4: Cumulative time adder 6-1 ......, 6-4 : Comparator 8: Comparator, 9: Bit error calculator

Claims (1)

(57) [Claims] A parity error counting circuit, a time base oscillator for generating a counting unit time, and a parity error adder for cumulatively adding parity errors output from the counting circuit are connected in series, and a time base oscillator is provided. A cumulative time adder for cumulatively adding the count unit time output from the oscillator is connected in series, and each time the cumulative time exceeds a certain value, the result is added to the next-stage adder for the parity error and the cumulative time. Means for starting calculation of the bit error rate from the result of each adder when the cumulative number of parity error adders in each stage exceeds a certain value or when the total cumulative time exceeds a certain value. A line quality monitoring device characterized by the following.