JPS5935531B2 - Nonlinear D/A converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides pulse code modulation (PC) with nonlinear stretching characteristics.
The present invention relates to a nonlinear D/A converter for M).

Conventionally, D/A converters used in PCM communications etc. have used analog signal processing networks such as resistive networks or capacitive networks, so it takes an extremely large number of circuits to perform accurate A/A conversion. It had the disadvantage of requiring a switch.

Furthermore, each resistor or each capacitor had to have an accurately defined value and not react to temperature changes.

However, in order to eliminate these drawbacks, a counting type D/A converter as shown in FIG. 1 has been proposed.

In the figure, 11 is an input device consisting of an n-bit register, P
is a reference pulse source, Z is a sawtooth signal source, 12 is a logic digital comparator, 13 is a counter, and S is a switching device.

This D/A converter starts a reference pulse source P at a terminal T, counts pulses from the reference pulse source P using a counter 13, and sends this result to the state of an input register 11 via a digital comparator 12. When the two states match, the digital comparator 12 sends out a control signal,
The switching device S is activated, and when the switching device S is turned on by the signal from the digital comparator 12, the instantaneous value of the sawtooth signal source Z activated at the same time as the reference pulse source P is transferred to the capacitor C via the terminal T, and is transferred to the output terminal. It is output from U as an analog signal.

However, this circuit configuration has the drawback that it is not possible to correct errors in analog output values when D/A conversion is performed.

Therefore, circuits having an error correction function have been proposed in the past, but such conventional circuits have a drawback of having a complicated circuit configuration.

In order to eliminate these drawbacks, the present invention uses a programmable code conversion device as an input device that converts an n-bit digital input signal into a (n0m)-bit digital signal, thereby simplifying the circuit configuration and reducing errors. The purpose of this is to improve the conversion accuracy of the D/A converter by providing a correction function.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, and...
・■ is an input terminal for a digitally encoded signal, 21 is a programmable read-only memory PROM (Programmab 1eRead) as a programmable code conversion circuit whose input terminal is n bits and whose output terminal is n-1-m bits.
0-n1y Memory).

22 is a digital comparator, 23 is a counter, both of which are n
+m bits, 24 is a reference pulse source, 25 is a high-speed reference pulse source that generates a pulse having a frequency sufficiently higher than the pulse frequency of the reference pulse source, 26
is a switch, 27 is an integration circuit, 28 is a sample holding circuit, 2
9 and 29' are clock pulse input terminals, and 30 is an analog signal output terminal.

FIG. 3 is an explanatory diagram of timing during operation of the present invention.

The operating principle of the constituent circuit which is the basis of the present invention will be explained below with reference to FIGS. 2 and 3.

First, at time t=o, a digitally encoded signal is input to the input terminals (1) to (4) of the PROM 21.

At the same time, as shown in FIG. 3, from the input terminal 29,
The reference pulse source 24 is activated by inputting the clock pulse P1, and the pulses generated from the reference pulse source 24 are counted by the counter 23.

On the other hand, the high-speed reference pulse generated from the high-speed reference pulse source 25 which is started simultaneously with the clock pulse P1 is integrated by the integrating circuit 27 via the switch 26, and its output waveform is integrated as shown in FIG. 3a. Since the signal is a pulse that turns off at high speed, the charging characteristic shown in the curve 31 shows a sawtooth waveform as a whole while repeatedly charging and discharging in small steps.

Then, at time t1 when the digital code of the counter 23 matches the output digital processing of the PROM 21, as shown in FIG.
As shown in FIG.
A pulse P1' is sent out, which opens the switch 26 and cuts off the input of the high speed reference pulse to the integrating circuit 27.

At this time, the analog output of the integrating circuit 27 has a value determined at time t1, and immediately after that, this analog value follows the downward curve shown by the smooth exponential discharge characteristic of curve 32 in FIG. 3a. The clock pulse p// shown in FIG. 3d is input from the input terminal 29' at time tc, which is a certain period of time after time to, and the sample holding circuit 28 is activated to sample the level of the descending curve 32. and hold it.

Then, an analog signal PAits corresponding to the input digital encoded signal of the D/A converter is taken out from the output terminal 30 as shown in FIG. 3e.

Then, from the clock pulse input terminal 29, the time tc+△
td As shown in FIG. 3, the pulse P2 is input and the integration circuit 27 is reset, and the same thing happens to the next input digital encoded signal at time P4. P4'・・・・・・
It is repeated in

The D/A converter of the present invention resets the integrating circuit 27 by selecting the integration time t of the high-speed reference pulse in the integrating circuit 27 to be an integral multiple of a certain unit minute time Δt, and the digitally encoded signal is input. Then pulse P1, P2...
・Integrator circuit 2 that is sampled after a certain period of time after is obtained
Since the descending curve 32 of the output of No. 7 shows non-linearity, an elongation characteristic can be obtained.

The clock pulses from the lock pulse input terminals 29 and 29' are delayed by a certain time △tc from the input terminal 29', so the clock pulses from the lock pulse input terminals 29 and 29' are delayed by a certain period of time △tc. It can be realized using one clock pulse generator.

Further, in the present invention, even if the input digital encoded signal is n bits, the digital processing system including the digital comparator 22 and the counter 23 processes it as n+m bits.

In other words, the count number of the counter 23 is the maximum (2n+m
1).

On the other hand, in the conventional example shown in Figure 1, the maximum count number is (2n-1)
becomes.

By the way, if the analog output in both FIGS. 1 and 2 is performed at a fixed time tc after the input of the digitally encoded signal, then in the conventional example shown in FIG. Since digital processing is performed on 2n levels within time tc, and n+m bits in the embodiment shown in FIG. 2, analog values of 2n+m levels can be sampled.

In this case, if each count period is T in the conventional example of FIG. 1, it becomes T/2m in FIG. 2.

Therefore, in this embodiment, 2n levels closest to the ideal analog level corresponding to the input digitally encoded signal are selected from 2n+m possible analog levels.
It can be specified by the memory contents of M21.

FIG. 4 is an output level diagram specifically explaining the effect of the above correction method. ideal output levels (Ll, L2, -L2n)
, b is the actual output level diagram for a, and C is the digital n+m digital processing system in FIG. 2n+m)
In the diagram shown in FIG. 1, d is an actual output level diagram for C.

Although a shows the ideal output level for each input digital encoded signal, it is assumed that the actual output level includes an error as shown by b.

Next, if the digital processing system is (n+m) bits, there are 2n+m ideal output levels as shown by C as explained above.

However, since the actual output level at this time includes an error, it is assumed that it is represented by d, which indicates a value that deviates from the ideal value.

Find the level closest to each dotted line drawn horizontally from each ideal output level in Figure 4a, and correspond to it in C (n
+m)-bit digitally encoded signal is written into the PROM in contrast to the n-bits digitally encoded signal.

Therefore, of the levels that can be represented by (n-hn) bits, only 20 digitally encoded signals having the least error level for a predetermined n-bit output are written in the FROM.

For example, the output level closest to the ideal output level indicated by level L2n-1 at a is the output level marked Δ at d.

Therefore, to output the level marked Δ, use C to output the level L'
The (n+m)-bit digital encoded signal represented by 2n+m-.1 is written in PROL in comparison with the n-bit digital encoded signal represented by level L2n-1 at a.

Conversely, if an n-bit digital encoded signal indicating level L2n-1 at point a is input to the D/A converter of the present invention, it will indicate level L'2n0m-1 in PROM (n
+m) bits are converted into a digitally encoded signal, and a corresponding analog output with less error is sent out.

What must be noted here is that even if the output level of b is equal to the ideal output level, the output level of d is not necessarily equal to the ideal output level.

In other words, by adding m bits (m<n), it is possible that an error may occur at an output level that originally had no error.

However, if m = n, this problem is solved because the same level exists as when n bits are not added, but the output error that occurs when m < n is greater than the error that existed before adding n bits. It is obvious that it can be made smaller.

The extent to which this output error is a problem depends on the application, and if the conversion accuracy is to be increased, m may be increased.

In this embodiment, FROM was used as the code conversion circuit, but the programmable logic array circuit PLA (Program
It can also be realized by a mmable Logic Array).

In addition, in the above embodiment, the high speed reference pulse source 25
is used as the reference voltage source, but other constant voltage sources can be used as the reference voltage source.

As explained above, in the present invention, since a programmable code conversion circuit is used as an input device, the output error is minimized by using a digital processing system of (n+m) bits for an n-bit input digital encoded signal. There is an advantage that a desired high-precision D/A converter can be realized by performing code conversion so as to obtain an analog output as follows.

Furthermore, even if a large output error occurs due to deterioration of the component elements during use, the D/A converter of the present invention corrects the code conversion using the programmable code conversion circuit, and continues to maintain the desired high output. It has the advantage of being able to be used as a precision/A converter.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional counting type D/A converter, Fig. 2 is a block diagram of an embodiment of the present invention using a FROM having n-1-m bit output lines, and Fig. 3. 2 is an explanatory diagram of the timing of FIG. 2, and FIG. 4 is an explanatory diagram of level correction. 11 is an input device, 12.22 is a logic digital comparator,
13. 23 is a counter, 21 is a striped PROM, P, 24 is a reference pulse source, 25 is a high-speed reference pulse source, 26 is a switch, 27 is an integrating circuit, 28 is a sample holding circuit, 29, 29
' is a clock pulse input terminal, U, 30 is an analog output terminal, S is a switching device, Z is a sawtooth wave signal source,
C is a capacitor.

Claims (1)

[Claims] 1 a counter that counts reference pulses from a reference pulse source;
A programmable code conversion circuit that converts an n-bit digital input signal into an (n+m)-bit digital signal such that an output error is minimized, and compares the count content of the counter with the code conversion output of the programmable code conversion circuit. A comparator, a reference voltage source, and the integration of the voltage from the reference voltage source are started at the same time as the counter starts counting, and the integration is stopped at the comparison match signal of the comparator to generate a signal according to predetermined discharge characteristics. A nonlinear D characterized by comprising an integrating circuit that outputs an output, and a sample holding circuit that samples and holds the output of the integrating circuit after a certain time from the start of counting of the counter.
/A converter.