RU2733809C9 - Method and apparatus for debugging serdes connection parameter and computer data medium - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to a serial application of a serialiser/deserialiser (SerDes). Encoding/decoding (codec) mode is determined according to the clock of the connection and the channel characteristic. Method for direct error correction (FEC) and verification code is determined. Range of predistortion parameters is determined and high-speed SerDes to be debugged according to a range of predistortion parameters, on the transmitting side, the FEC method and the verification code are prepared to obtain a predistortion configuration parameter. After determining the predistortion configuration parameter, preparing a correction parameter on the receiving side of high-speed SerDes to be debugged to obtain a self-adaptive configuration parameter.

EFFECT: technical result consists in improvement of accuracy and stability of data transmission.

11 cl, 3 dwg

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is governed by and claims the priority of Chinese Patent Application No. 201710386821.7, filed May 26, 2017, the entire contents of which are incorporated herein by reference.

FIELD OF TECHNOLOGY

The present invention relates to the field of a serializer / deserializer (SerDes) communication application, and in particular to a method and apparatus for debugging a SerDes connection parameter, and a computer storage medium.

BACKGROUND OF THE INVENTION

As the demand for bandwidth and service levels increases, so does the demand for highly efficient data transmission. Ensuring the stability of data transmission on a high speed channel is the key to realizing highly efficient data transmission.

SerDes stands for Serializer / Deserializer. SerDes is a time division multiplexing (TDM) and point-to-point (P2P) serial transmission technology. The technology involves converting multipath, low-rate parallel signals into high-speed serial signals at the transmitting end. High-speed serial signals travel through a transmission medium (such as optical fiber or copper wire) and are converted to low-speed parallel signals at the receiving end. P2P serial technology fully utilizes the bandwidth of the media channel to reduce the required number of transmission channels and device leads, so that communication costs are significantly reduced. The technology is widely applied to a variety of scale switches and routing devices. However, the improvement in transmission quality is accompanied by careful precise control, so it is very important to ensure or even improve the transmission stability at high speed by strictly controlling the deviation of SerDes during operation caused by the environment and devices.

BRIEF DESCRIPTION OF THE INVENTION

In order to overcome the disadvantages of the prior art, the present invention is expected to provide a method and apparatus for debugging a SerDes connection parameter, as well as a computer storage medium, to provide or even improve the stability of high-speed data transmission.

To achieve the above object, the present invention provides a method for debugging a SerDes connection parameter. The method includes the steps described below.

The encoding / decoding (codec) mode is determined according to the connection clock and channel characteristics, and the direct error correction (FEC) method and check code are determined.

A range of predistortion parameters is determined, and a high-speed SerDes to be debugged according to a range of predistortion parameters, an FEC method, and a check code to obtain a predistortion configuration parameter are prepared on the transmitting side.

After determining the predistortion configuration parameter, preparation of the correction parameter on the receiving side of the high-speed SerDes to be debugged is carried out to obtain the self-adaptive configuration parameter.

In an embodiment, the codec mode provides at least one codec mode of 8B codec mode, 10B codec mode, 64B codec mode, or 66B codec mode.

In an embodiment, the FEC method is a Reed-Solomon FEC (RS-FEC) method, and the check code is a cyclic redundancy check code (CRC) 16.

In an embodiment, the step where preparation is performed on the transmitting side of the high-speed SerDes to be debugged according to the predistortion parameter range, the FEC method, and the check code includes the steps described below.

The predistortion parameter selection range is set, and the predistortion parameter group is selected from the predistortion parameter selection range as the configuration parameter of the transmitting side of the high-speed SerDes to be debugged.

Resuming and checking are performed according to the FEC method on the receiving side of the high speed SerDes to be debugged. If a CRC error occurs during resume and check, it is determined that the selected group of predistortion parameters is not available. The operation of returning to a new preparation direction opposite or parallel to the preparation direction is performed, another group of predistortion parameters is selected as the configuration parameter of the transmitting side of the high-speed SerDes to be debugged according to the new preparation direction, and the resuming and checking according to the FEC method on the receiving side of the high-speed SerDes is performed. to be debugged until there is no CRC error during resume and validation.

All predistortion parameters in a range of predistortion parameters are scanned, a group of predistortion parameters with no CRC error during resume and check is recorded and determined as an available predistortion parameter group.

All SerDes connections are scrolled, the set of available predistortion parameter groups in all SerDes connections is obtained, and the set of predistortion parameters available for all SerDes connections as a predistortion configuration parameter is searched in the set of available predistortion parameter groups.

In the embodiment, after selecting a group of predistortion configuration parameters as the predistortion configuration parameter of the transmitting side of the high-speed SerDes to be debugged each time, and before the resumption and verification are performed on the receiving side of the high-speed SerDes to be debugged, a delay operation is performed for a predetermined period time. The preset time period has a duration of 200 microseconds to 300 microseconds.

In an embodiment, during the determination of the predistortion configuration parameter and the self-adaptive configuration parameter, the method further includes performing time monitoring for the SerDes connection using the communication link. Performing time control includes the steps described below.

The notification of the start of the predistortion configuration of the transmitting side of the SerDes connection is sent to the SerDes connection using the communication link.

After selecting a group of predistortion configuration parameters as the predistortion configuration parameter of the transmitting side of the SerDes connection, a delay operation is performed for a predetermined period of time, and the notification of the start of the self-adaptive configuration of the parameter of the receiving side of the SerDes connection is sent to the receiving side of the SerDes connection using the communication link.

After determining the predistortion configuration parameter, the correction parameter is prepared on the receiving side of the SerDes connection to obtain the self-adaptive configuration parameter.

In an embodiment, if a CRC error occurs on the receiving side of the SerDes connection after viewing all the predistortion parameters, and also if the CRC error still occurs during resumption and verification after performing the preparation of the equalization parameter on the receiving side, the SerDes connection is marked as unavailable.

The present invention further provides a device for debugging a SerDes connection parameter. The device contains a determination block, a first preparatory block and a second preparatory block.

The determining unit is configured to determine the codec mode according to the connection clock and channel characteristics, determine the FEC method and the check code, and determine the range of the predistortion parameters.

The first preparatory unit is configured to prepare, on the transmitting side, a high-speed SerDes to be debugged according to a range of predistortion parameters, an FEC method, and a check code to obtain a predistortion configuration parameter.

The second preparatory block is configured, after the first preparatory block has determined the predistortion configuration parameter, prepares the correction parameter on the receiving side of the high-speed SerDes to be debugged, with the self-adaptive configuration parameter being obtained.

In an embodiment, the first preparatory unit is configured to adjust the predistortion parameter selection range and select the predistortion parameter group from the predistortion parameter selection range as a configuration parameter of the transmission side of the high-speed SerDes to be debugged; performing resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged; if a CRC error occurs during resuming and checking, determination of the selected predistortion parameter group is not available, return to a new preparation direction opposite or parallel to the preparation direction, selection of another predistortion parameter group as the configuration parameter of the transmission side of the high-speed SerDes to be debugged according to the new preparation direction , and performing resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged until there is no CRC error during resuming and checking; viewing all predistortion parameters in the range of predistortion parameters, recording and defining a group of predistortion parameters with no CRC error during resumption and checking as an available group of predistortion parameters; browse all SerDes connections, get the set of available predistortion parameter groups in all SerDes connections, and search for the set of available predistortion parameter groups for a predistortion parameter group available for all SerDes connections as a predistortion configuration parameter.

The present invention further provides a device for debugging a SerDes connection parameter. The device contains a processor and memory. The memory device is configured to store computer programs capable of executing on a processor. The processor, when executing computer programs, performs the steps of the SerDes connection parameter debugging method described in the present invention.

The present invention further provides a computer storage medium. Instructions executed on a computer are stored on a computer storage medium. Instructions executed on the computer are configured to perform the SerDes connection parameter debugging method described in the present invention.

According to the method and device for debugging the SerDes connection parameter, as well as to the computer storage medium proposed in the present invention, the predistortion parameter is prepared on the transmitting side, and the correction parameter is prepared and adjusted on the receiving side. Interference caused by the two-way communication of a connection is prevented by strict control of the configuration parameter, so that deviation during configuration of the connection parameter is prevented, the accuracy of the configured connection parameter is ensured, and transmission stability is ensured or even improved. The present invention is suitable for various router backplanes and implements automatic debugging of the parameters of each of the high speed SerDes connections.

BRIEF DESCRIPTION OF THE GRAPHIC MATERIALS

The drawings are used to provide a deeper understanding of the present invention, form part of the specification, explain the present invention in combination with embodiments of the present invention, and do not limit the present invention. On graphic materials:

in fig. 1 is a flowchart of a method for debugging a SerDes connection parameter according to an embodiment of the present invention;

in fig. 2 is a schematic diagram of the return of the preparation direction at the transmitting side according to the present invention; and

in fig. 3 is a schematic diagram of a time control process according to the present invention.

DETAILED DESCRIPTION

The preferred embodiments of the present invention will be described in conjunction with the drawings, and it should be understood that the embodiments described later in this document are intended solely to describe and explain the present invention, and do not limit the present invention.

FIG. 1 is a flow chart of a method for debugging a SerDes connection parameter according to an embodiment of the present invention. As shown in FIG. 1, the method includes the steps described below.

In step 1, the codec mode is determined according to the connection clock and channel characteristics, and the FEC method and check code are determined.

In step 2, a range of predistortion parameters is determined, and a high-speed SerDes to be debugged according to a range of predistortion parameters, an FEC method and a check code to obtain a predistortion configuration parameter is prepared on the transmitting side (i.e., the TX side).

In step 3, after the predistortion configuration parameter has been determined, an equalization parameter is prepared on the receiving side (i.e., the RX side) of the high-speed SerDes to be debugged to obtain the self-adaptive configuration parameter.

A method for debugging a SerDes connection parameter in an embodiment of the present invention can be applied to a test device. Before the method for debugging the SerDes connection parameter in the embodiment of the present invention is performed, it is first necessary to set the test device and the high-speed SerDes to be debugged.

In an embodiment, the connection clock and channel are taken into account to ensure that the data stream does not change and that it is not interfered with during data transmission. The codec mode includes at least one of an 8B codec mode, a 10B codec mode, a 64B codec mode, or a 66B codec mode. As an implementation option, the 64B / 66B codec mode may be selected. Compared with the 8B / 10B codec mode, the 64B / 66B codec mode can ensure data length integrity and high data coding efficiency, and can also meet the bandwidth requirements of scale switches and routing devices under the condition of high-speed data transmission, and reduce data loss during transmission. data.

The FEC method can be an RS-FEC method. RS stands for Reed-Solomon in Reed-Solomon codes. The check code may be a CRC 16 code. The RS-FEC method is selected to interoperate with the CRC 16 code to improve flexibility and robustness against data failures. In an embodiment, the data length of each frame of RS codes may be 528 bits, including 514 information bits. According to the RS-FEC method, it is possible to correct a packet with a continuity of 10 bits or even a maximum of 70 bits during the transmission of data of one frame.

In the data transmitted by the TX side, a check mark (such as a CRC mark) is applied in the data of each frame according to the content of the data stream of the frame and the above rule. Possible data changes during transmission are corrected by an FEC method (such as an RS-FEC method) during a high speed serial transmission of the connection. On the RX side, the frame data is checked according to a check code (such as CRC code 16) to check the integrity of the frame data. If it is not possible to provide integrity and correct the frame length data by correcting the RS codes, the frame data is discarded according to the CRC mechanism.

Consider FIG. 2, which illustrates a schematic diagram of the preparation and return directions in the embodiment, the step in which preparation is performed on the transmitting side of the high-speed SerDes to be debugged according to the predistortion parameter range, the FEC method and the check code, to obtain the predistortion configuration parameter, provides the steps described below.

In step 201, the predistortion parameter selection range is adjusted, and the predistortion parameter group is selected from the predistortion parameter selection range as the configuration parameter of the transmission side of the high-speed SerDes to be debugged. The transmitting side transmits the packet based on the configuration parameter and the specific codec mode.

In step 202, the packet is reconstructed and checked according to the FEC method on the receiving side of the high speed SerDes to be debugged; if a CRC error occurs during resume and check, it is determined that the selected predistortion parameter group is not available, an operation is performed to return to a new preparation direction opposite or parallel to the selected predistortion parameter group, the process goes to step 201, another predistortion parameter group is selected as a parameter configurations of the transmitting side of the high-speed SerDes to be debugged according to the new preparation direction, and also resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged; if there is no CRC error during resume and validation, the process proceeds to step 203.

In step 203, all of the predistortion parameters in the range of predistortion parameters are monitored according to step 201 and step 202, and a group of predistortion parameters with no CRC error during resume and verification is recorded and determined as an available predistortion parameter group.

In step 204, all SerDes connections are scanned based on steps 201-203, a plurality of available predistortion parameter groups in all SerDes connections are obtained, and obtained as a predistortion configuration parameter. As an embodiment, if the number of the plurality of available predistortion parameter groups used as the predistortion configuration parameter is at least two, the plurality of available predistortion parameter groups may be searched for the predistortion parameter group as the predistortion configuration parameter.

During the practical debugging of SerDes, whether or not a CRC error occurs while checking and calculating the error correction by the FEC method on the RX side as a result of an irregular change caused by a trace or the like, is considered a criterion for determining the quality of the connection. The criterion is that an ERR label is created if the SerDes condition does not obey a regular change in the ontology algorithm, but changes in the direction of deterioration. In this case, the predistortion parameter group does not satisfy the requirement, and the predistortion parameter group is recorded as unused. In this case, another group of predistortion parameters is selected for adjustment in the opposite or parallel direction. This regulatory process is a reverse process. A group of SerDes predistortion parameters suitable for all connections is found and used as the final pre-emphasis configuration parameter by selecting the return algorithm after viewing all connections.

In an embodiment, the step of preparing an equalization parameter on the receiving side of the high-speed SerDes to be debugged comprises the steps described below.

According to the configuration of the AC capacitive coupling, the receiving side of the SerDes connection, matching the preparation mode of the decision feedback compensator (DFE), the insertion loss of the different channels, the voltage requirement at high speed transmission power consumption, and whether or not the real signal on the receiving side is intact and convergent, a group of parameters for correcting the self-adaptive configuration is selected.

Capacitive coupling can cause voltage fluctuations in the receiving side and cause interference after receiving a signal, and can easily lead to clock instability. Different backplane connection traces can cause different link insertion loss. A signal with high or low power on the transmitting side can lead to incorrect preparation of the gain on the receiving side.

Therefore, if capacitive coupling exists in the backplane design, then the receive side can be configured to terminate capacitive coupling at high impedance to remove the capacitance effect, otherwise it may not be configured to terminate capacitive coupling at high impedance.

If the backplane trace is too short, correcting for high link strength can adversely affect the parallel convergence of all self-adaptive algorithms. The self-adaptive DAC algorithm of the connection can be closed and the correction parameter is manually adjusted to provide convergence and smoothness of the signal.

If the signal sampling is incomplete and not smooth, the gain control and peak control may be closed and the gain parameter and peak value are manually adjusted to adjust to the proper equalization parameter.

If a periodic CRC error occurs on the receiving side, the DFE preparation mode can be adopted, and the adjustment and improvement is realized through the configuration and preparation of the sequencing parameter.

If high-speed signal transmission requires power consumption, the power management function of the receiving side may be disabled.

FIG. 3 shows two SerDes connections, namely a Lane_A connection and a Lane_B connection with a communication link. During the determination of the predistortion configuration parameter and the self-adaptive configuration parameter, as shown in FIG. 3, the method further includes performing time control. Performing time control includes the steps described below.

In step a, the Lane_A connection provides notification of the start of the predistortion configuration of the transmitting side of the Lane_A connection to the Lane_B connection using the communication link. Meanwhile, the Lane_B connection provides notification of the start of the predistortion configuration of the transmitting side of the Lane_B connection to the Lane_A connection.

In step b, the predistortion configuration parameter of the transmission side of the Lane_A connection and the predistortion configuration parameter of the transmission side of the Lane_B connection are determined according to the order of steps 201-204. After completing the predistortion configuration and before preparing the self-adaptive equalization, resuming and checking are performed on the respective receiving sides of the Lane_A connection and the Lane_B connection, a delay operation may be performed for a predetermined period of time (such as 200 microseconds to 300 microseconds), respectively. The notification about the beginning of the self-adaptive configuration of the parameter of the receiving side of the SerDes connection is sent to the opposite side (namely, the receiving side of the SerDes connection using the communication link).

In step c, the Lane_A connection and the Lane_B connection start to correct the respective connections, and the corresponding self-adaptive configuration parameters of the Lane_A connection and the Lane_B connection are obtained according to the above step 3.

Finally, the predistortion configuration parameters of the respective transmitting sides of the Lane_A connection and the Lane_B connection are selected and counted according to the criterion for determining whether a CRC error occurs after the respective receiving sides of the Lane_A connection and Lane_B connection by the FEC.

This time control mode can ensure that the transmitting side is valid in the first place and slows down slightly. Then the parameter of the receiving side is adjusted. In the high-speed router backplane, it is possible for thousands of SerDes connections to implement the limiting configuration of the transmit-side pre-emphasis parameter and the receive-side self-adaptive parameter in series, and the integral stable effect of the backplane can be improved.

An embodiment of the present invention has the following advantages: starting from a frame of high speed data transmitted by a SerDes connection, the packet connection error is corrected by coding and error correction on the connection. The burst error is handled in a timely manner and the error data is corrected, so that the transmission efficiency of the data frame is improved. The SerDes self-adaptive receive-side throttling function is used to implement arbitrary sufficient convergence of the received data code stream. The converted codestream is the complete transmit packet without bit confusion or modification. Thus, the goals of no error in the packet, no interference or signal loss during the transmission of the connection, and highly efficient stable reception of frame data are achieved. In addition, the method further ensures data accuracy and integrity by means of a CRC at the receiving end and prevents frame loss caused by misjudgment during data processing and validation.

An embodiment of the present invention further provides a device for debugging a SerDes connection parameter. The device contains a determination block, a first preparatory block and a second preparatory block.

The determining unit is configured to determine the codec mode according to the connection clock and channel characteristics, determine the FEC method and the check code, and determine the range of the predistortion parameters.

The first preparatory unit is configured to prepare, on the transmitting side, a high-speed SerDes to be debugged according to a range of predistortion parameters, an FEC method, and a check code to obtain a predistortion configuration parameter.

The second preparatory block is configured, after the first preparatory block has determined the predistortion configuration parameter, prepares the correction parameter on the receiving side of the high-speed SerDes to be debugged, with the self-adaptive configuration parameter being obtained.

In an embodiment, the codec mode provides at least one codec mode of 8B codec mode, 10B codec mode, 64B codec mode, or 66B codec mode. The FEC method can be an RS-FEC method, and the check code can be a CRC 16 code.

As an embodiment, the first preparatory unit is configured to perform the following operations. The predistortion parameter selection range is set, and the predistortion parameter group is selected from the predistortion parameter selection range as the configuration parameter of the transmitting side of the high-speed SerDes to be debugged. Resuming and checking are performed according to the FEC method on the receiving side of the high-speed SerDes to be debugged. If a CRC error occurs during resuming and checking, it is determined that the selected group of predistortion parameters is not available, an operation is performed to return to a new preparation direction opposite or parallel to the preparation direction, another group of predistortion parameters is selected as the configuration parameter of the transmitting side of the high-speed SerDes to be debugged. according to the new direction of preparation, and also resume and check according to the FEC method on the receiving side of the high-speed SerDes to be debugged until there is no CRC error during the resume and check. All predistortion parameters in a range of predistortion parameters are scanned, a group of predistortion parameters with no CRC error during resume and check is recorded and determined as an available predistortion parameter group. All SerDes connections are scrolled, the set of available predistortion parameter groups in all SerDes connections is obtained, and the set of predistortion parameters available for all SerDes connections as a predistortion configuration parameter is searched in the set of available predistortion parameter groups.

As an embodiment, the second preparatory unit is configured, after the first preparatory unit selects a group of predistortion configuration parameters as the predistortion configuration parameter of the transmitting side of the high-speed SerDes to be debugged each time, and also before resuming and checking on the receiving side high-speed SerDes to be debugged, performing a delay for a pre-set period of time. The preset time period has a duration of 200 microseconds to 300 microseconds.

As an embodiment, the device further comprises a transmission unit. The transmission unit is configured to send a notification of the start of the predistortion configuration of the transmitting side of the SerDes connection to the SerDes connection using the communication connection.

The first preparatory unit is configured, after selecting a group of predistortion configuration parameters as the predistortion configuration parameter of the transmitting side of the SerDes connection, to perform a delay for a predetermined period of time.

The transmission unit is further configured to transmit a notification of the start of the predistortion configuration of the receiving side of the SerDes connection to the SerDes connection using the communication connection.

The second preparatory block is configured, after the first preparatory block has determined the predistortion configuration parameter, prepares the correction parameter on the receiving side of the high-speed SerDes to be debugged, with the self-adaptive configuration parameter being obtained.

In practice, the determination unit, the first preparatory unit and the second preparatory unit may be implemented by a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), a field programmable gate array (FPGA), or the like.

It should be noted that the device for debugging the SerDes connection parameter provided in the above embodiment is only given as an example by separating the program modules when performing the connection parameter debugging. In practice, the above processing placement can be completed by different software modules as needed, in other words, the internal structure of the SerDes connection parameter debugging device is divided into different software modules to complete all or part of the processing described earlier. In addition, the SerDes connection parameter debugger and the SerDes connection parameter debugging method proposed in the above embodiment refer to the same concept, and the process of their concrete implementation is described in the method in the embodiment that is not repeated herein.

An embodiment of the present invention further provides a device for debugging a SerDes connection parameter. The device contains a processor and memory. The memory device is configured to store computer programs capable of executing on a processor. The processor is configured, when executing computer programs, to perform the following operations: the codec mode is determined according to the connection clock and channel characteristics, and the FEC method and check code are determined; determining a range of predistortion parameters, and preparing on the transmitting side a high-speed SerDes to be debugged according to a range of predistortion parameters, an FEC method and a check code to obtain a predistortion configuration parameter; After determining the pre-emphasis configuration parameter, the preparation of the correction parameter on the receiving side of the high-speed SerDes to be debugged is carried out to obtain the self-adaptive configuration parameter.

As an embodiment, the processor is configured to perform the following operations when executing computer programs: a selection range of predistortion parameters is set, and a group of predistortion parameters is selected from a selection range of predistortion parameters as a configuration parameter of the transmission side of the high-speed SerDes to be debugged; resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged; if a CRC error occurs during resume and check, it is determined that the selected group of predistortion parameters is not available, an operation is performed to return to a new preparation direction opposite or parallel to the preparation direction, another group of predistortion parameters is selected as the configuration parameter of the transmitting side of the high-speed SerDes to be debugged according to the new preparation direction, resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged until there is no CRC error during resuming and checking; all predistortion parameters in the range of predistortion parameters are viewed, and a group of predistortion parameters with no CRC error during resumption and verification is recorded and determined as an available predistortion parameter group; all SerDes interconnects are scanned, the set of available predistortion parameter groups in all SerDes interconnects are retrieved, and the set of predistortion parameters available for all SerDes interconnects is searched in the set of available predistortion parameter groups as a predistortion configuration parameter.

As an embodiment, the processor is configured, when executing computer programs, to perform the following operations: after selecting a group of predistortion configuration parameters as a predistortion configuration parameter of the transmitting side of the high-speed SerDes to be debugged each time, and also before the resumption and check at the receiving on the side of the high-speed SerDes to be debugged, a delay operation is performed for a predetermined period of time. The preset time period has a duration of 200 microseconds to 300 microseconds.

As an embodiment, the processor is configured, when executing computer programs, to perform the following operations: notification of the start of the predistortion configuration of the transmitting side of the SerDes connection is transmitted to the SerDes connection using the communication link; after selecting the predistortion configuration parameter group as the predistortion configuration parameter of the transmitting side of the SerDes connection, a delay operation is performed for a predetermined period of time, and the notification of the start of the self-adaptive configuration of the parameter of the receiving side of the SerDes connection is transmitted to the receiving side of the SerDes connection using the communication link; after defining the predistortion configuration parameter, the correction parameter is prepared on the receiving side of the SerDes connection to obtain the self-adaptive configuration parameter.

As an embodiment, the processor is configured, when executing computer programs, to perform the following operations: in the event of a CRC error on the receiving side of the SerDes connection after viewing all the predistortion parameters, and also if a CRC error still occurs during resumption and verification after preparation correction parameter on the receive side, the SerDes connection is marked as unavailable.

In practical application, the memory device can be implemented by any type of volatile or nonvolatile storage device, or a combination thereof. Nonvolatile memory can be read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), ferromagnetic random access memory (FRAM), flash -memory, magnetic surface storage device, disk or CD-ROM with read-only memory (CD-ROM). The magnetic surface storage device may be a magnetic disk drive or a magnetic tape drive. Volatile memory can be random access memory (RAM), which is used as external cache memory. Many kinds of RAM are available as an example and not a limitation, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM) ), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), Direct Dynamic Random Access Memory Rambus (DRRAM). It is assumed that the storage device described in the embodiment of the present invention includes, but is not limited to, these and any other suitable type of storage device.

A mass storage device is used to store various types of data to support device operations to debug the SerDes connection parameter. Examples of different types of data include any computer program that runs on a device to debug the SerDes connection parameter. The operating system includes various system programs, such as the shell layer, the base library layer, and the storage layer, to implement various basic services and handle hardware tasks. An application can include various applications such as a media player and a browser to implement various application services. Programs for implementing the method in an embodiment of the present invention may be included in an application.

The processor in the SerDes connection parameter debugger may be an integrated circuit chip with signal processing capability. In the implementation process, various steps of the method described above may be performed by an integrated logic circuit (IC) hardware or software instructions in a processor. The aforementioned processor can be a general-purpose processor, DSP or other programmable logic devices, discrete logic gates or transistor logic devices, discrete hardware components, etc. A processor may implement or execute various methods, steps, and logic block diagrams disclosed in an embodiment of the present invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in an embodiment of the present invention may be directly implemented by a hardware decoding processor, or may be implemented by a combination of hardware and software modules in a decoding processor. The software modules can be disclosed in a storage medium in a storage device. The processor reads the information in the memory and completes the steps of the method described above in conjunction with the processor hardware.

In illustrative embodiments, a device for debugging a SerDes connection parameter may be implemented by at least one of an application specific integrated circuit (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD), FPGA, general purpose processor, controller, MCU or microprocessor to perform the above method.

An embodiment of the present invention further provides a computer storage medium. Instructions executed on a computer are stored on a computer storage medium. Instructions executed on the computer are configured to perform the following operations: the codec mode is determined according to the connection clock and channel characteristics, and the FEC method and verification code are determined; determining a range of predistortion parameters, and preparing on the transmitting side a high-speed SerDes to be debugged according to a range of predistortion parameters, an FEC method and a check code to obtain a predistortion configuration parameter; after determining the predistortion configuration parameter, the correction parameter is prepared on the receiving side of the high-speed SerDes to be debugged, with the self-adaptive configuration parameter being obtained.

As an embodiment, instructions executed on a computer are configured to perform the following operations: a selection range of predistortion parameters is set, and a group of predistortion parameters is selected from a selection range of predistortion parameters as a configuration parameter of the transmission side of the high-speed SerDes to be debugged; resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged; if a CRC error occurs during resuming and checking, it is determined that the selected group of predistortion parameters is not available, an operation is performed to return to a new preparation direction opposite or parallel to the preparation direction, another group of predistortion parameters is selected as the configuration parameter of the transmitting side of the high-speed SerDes to be debugged according to the new preparation direction, resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged until there is no CRC error during resuming and checking; all the predistortion parameters in the range of the predistortion parameters are viewed, the predistortion parameter group with no CRC error during resume and check is recorded and determined as an available predistortion parameter group; all SerDes interconnects are scanned, the set of available predistortion parameter groups in all SerDes interconnects are retrieved, and the set of predistortion parameters available for all SerDes interconnects is searched in the set of available predistortion parameter groups as a predistortion configuration parameter.

As an embodiment, the instructions executed on the computer are configured to perform the following operations: after selecting a group of predistortion configuration parameters as the predistortion configuration parameter of the transmitting side of the high-speed SerDes to be debugged each time, and also before resuming and checking on the receiving side high-speed SerDes to be debugged, a delay operation is performed for a predetermined period of time. The preset time period has a duration of 200 microseconds to 300 microseconds.

As an embodiment, the instructions executed on the computer are configured to perform the following operations: notification of the start of the predistortion configuration of the transmitting side of the SerDes connection is transmitted to the SerDes connection using the communication link; after selecting the predistortion configuration parameter group as the predistortion configuration parameter of the transmitting side of the SerDes connection, a delay operation is performed for a predetermined period of time, and the notification of the start of the self-adaptive configuration of the parameter of the receiving side of the SerDes connection is transmitted to the receiving side of the SerDes connection using the communication link; after defining the predistortion configuration parameter, the correction parameter is prepared on the receiving side of the SerDes connection to obtain the self-adaptive configuration parameter.

As an option, the instructions executed on the computer are configured to perform the following operations: in the event of a CRC error on the receiving side of the SerDes connection after viewing all the predistortion parameters, and also if the CRC error still occurs during resume and verification after the parameter preparation correction on the receiving side, the SerDes connection is marked as unavailable.

In the embodiments of the present invention, it should be understood that the disclosed devices and method may be implemented differently. The embodiments of the devices described above are purely illustrative. For example, division into blocks is only a functional-logical division, and in practice division into blocks can be implemented differently. For example, several blocks or components may be combined or integrated into another system, or some elements may be excluded or not implemented. In addition, communications, direct communications, or communications connections between the illustrated or discussed components may be indirect communications or communications connections through interfaces, between devices or units, and may be electrically, mechanically, or otherwise.

The blocks described above as separate components may or may not be physically separated. Blocked components may or may not be physical blocks, that is, they may reside in one location or may be distributed across multiple network blocks. All or part of these blocks can be selected according to practical requirements to achieve the goals of the solutions in the embodiments of the present invention.

Moreover, various functional blocks in the embodiments of the present invention may be integrated into one processing unit, or each unit may be used as a separate unit, or two or more units may be integrated into one unit. An integrated block can be implemented by hardware, or can be implemented by hardware and a software function block.

It should be understood by those skilled in the art that all or part of the steps in the embodiment of the method described above may be implemented by hardware related to program instructions, these programs may be stored in a computer-readable storage medium and, when executed, these programs execute steps including an embodiment of the method described above. The above storage medium provides various media capable of storing program codes, such as a removable storage device, ROM, RAM, magnetic disk, or optical disk.

Alternatively, the aforementioned integrated unit according to the present invention can also be stored in a computer-readable storage medium if it is implemented as a software function and is sold or used as an independent product. Based on this interpretation, a technical solution proposed in an embodiment of the present invention, essentially, or a part contributing to the prior art, can be implemented as a software product. The computer program product is stored in a storage medium and contains several instructions for enabling a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the method provided in embodiments of the present invention. The above storage medium provides various media capable of storing program codes, such as a removable storage device, ROM, RAM, magnetic disk, or optical disk.

The above are only specific embodiments of the present invention, which are not intended to limit the present invention. Modifications or substitutions can easily be suggested by those skilled in the art within the technical scope disclosed in the present invention. These modifications or replacements are within the scope of the present invention. Therefore, the scope of the present invention is determined by the scope of the appended claims.

INDUSTRIAL APPLICABILITY

According to the technical solution of the present invention, starting from a frame of high speed data transmitted by a SerDes connection, a packet connection error is corrected by coding and error correction on the connection. The burst error is handled in a timely manner and the error data is corrected, so that the transmission efficiency of the data frame is improved. The SerDes self-adaptive receive-side throttling function is used to implement arbitrary sufficient convergence of the received data code stream. The converted codestream is the complete transmit packet without bit confusion or modification. Thus, the goals of no error in the packet, no interference or signal loss during the transmission of the connection, and highly efficient stable reception of frame data are achieved. In addition, the method further ensures data accuracy and integrity by means of a CRC at the receiving end and prevents frame loss caused by misjudgment during data processing and validation.

Claims (26)

1. A way to debug the serializer / deserializer connection parameter (SerDes), including: determining the encoding / decoding mode (codec) according to the connection clock and channel characteristics, and determining the direct error correction (FEC) method and the check code; determining a range of predistortion parameters and performing preparation on the transmitting side of the high-speed SerDes to be debugged according to the range of predistortion parameters, the FEC method, and the check code to obtain a predistortion configuration parameter; and after determining the predistortion configuration parameter, preparing the correction parameter on the receiving side of the high-speed SerDes to be debugged to obtain the self-adaptive configuration parameter. 2. The method according to claim 1, characterized in that the codec mode provides at least one codec mode from the group consisting of: 8-bit / 10-bit (8B / 10B) codec mode and 64-bit / 66-bit (64B / 66B). 3. The method according to claim 1, wherein the FEC method is a Reed-Solomon FEC (RS-FEC) method and the check code is a cyclic redundancy check code (CRC) 16. 4. The method according to claim 3, characterized in that performing preparation on the transmitting side of the high-speed SerDes to be debugged according to the predistortion parameter range, the FEC method, and the check code to obtain the predistortion configuration parameter comprises: setting a predistortion parameter selection range and selecting a predistortion parameter group from the predistortion parameter selection range as a configuration parameter of the transmission side of the high-speed SerDes to be debugged; performing resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged; in response to the determination of the occurrence of a CRC error during resumption and verification, determining that the selected group of predistortion parameters is not available, returning to a new preparation direction opposite or parallel to the preparation direction, selecting another group of predistortion parameters as the configuration parameter of the transmitting side of the high-speed SerDes, to be debugged according to the new preparation direction, and performing resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged until there is no CRC error during resuming and checking; viewing all predistortion parameters in a range of predistortion parameters, recording and defining a group of predistortion parameters with no CRC error during resumption and checking as an available group of predistortion parameters; and browse all SerDes connections, get the set of available predistortion parameter groups in all SerDes connections, and search the set of available predistortion parameter groups for the predistortion parameter group available for all SerDes connections as a predistortion configuration parameter. 5. The method according to claim 4, characterized in that after selecting the group of predistortion configuration parameters as the predistortion configuration parameter of the transmitting side of the high-speed SerDes to be debugged each time, and also before resuming and checking on the receiving side of the high-speed SerDes to be debugging, there is a delay for a predetermined period of time, the predetermined period of time having a duration of 200 microseconds to 300 microseconds. 6. The method of claim 5, wherein during the determination of the predistortion configuration parameter and the adaptive configuration parameter, the method further comprises: performing time control for SerDes connection using communication link, in this case, the implementation of time control provides for: sending a notification of the start of the predistortion configuration of the transmitting side of the SerDes connection to the SerDes connection using the communication link; after selecting a group of predistortion configuration parameters as a predistortion configuration parameter of the transmitting side of the SerDes connection, delaying for a predetermined period of time and transmitting a notification of the start of self-adaptive configuration of the parameter of the receiving side of the SerDes connection to the receiving side of the SerDes connection using the communication link; and after determining the predistortion configuration parameter, preparation of the equalization parameter on the receiving side of the SerDes connection to obtain the self-adaptive configuration parameter. 7. The method according to claim 6, characterized in that in response to the determination of the occurrence of a CRC error on the receiving side of the SerDes connection after viewing all the predistortion parameters, and also if the CRC error still occurs during resumption and verification after the preparation of the correction parameter on the receiving to the side, the SerDes connection is marked as unavailable. 8. Device for debugging the serializer / deserializer connection parameter (SerDes), containing the definition block, the first preparatory block and the second preparatory block, the determining unit is configured to determine the encoding / decoding (codec) mode according to the connection clock and channel characteristics, determine the direct error correction (FEC) method and the check code, and determine the range of the predistortion parameters; the first preparatory unit is configured to prepare, on the transmitting side, a high-speed SerDes to be debugged according to a range of predistortion parameters, an FEC method, and a check code to obtain a predistortion configuration parameter; and the second preparatory unit is configured, after the first preparatory unit has determined the predistortion configuration parameter, preparation of the correction parameter on the receiving side of the high-speed SerDes to be debugged to obtain the self-adaptive configuration parameter. 9. The device according to claim 8, characterized in that the first preparatory unit is configured to adjust the selection range of the predistortion parameters and select a group of predistortion parameters from the selection range of the predistortion parameters as a configuration parameter of the transmitting side of the high-speed SerDes to be debugged; performing resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged; in response to determining that a CRC error occurs during resuming and checking, determining that the selected group of predistortion parameters is not available, returning to a new preparation direction opposite or parallel to the preparation direction, selecting another group of predistortion parameters as the configuration parameter of the transmitting side of the high speed SerDes to be debugged according to the new preparation direction, and performing resuming and checking according to the FEC method on the receiving side of the high-speed SerDes to be debugged until there is no CRC error during resuming and checking; viewing all predistortion parameters in the range of predistortion parameters, recording and defining a group of predistortion parameters with no CRC error during resumption and checking as an available group of predistortion parameters; browse all SerDes connections, get the set of available predistortion parameter groups in all SerDes connections, and search for the set of available predistortion parameter groups for a predistortion parameter group available for all SerDes connections as a predistortion configuration parameter. 10. Device for debugging the serializer / deserializer connection parameter (SerDes), characterized in that it contains a processor and a memory device, wherein the memory device is configured to store computer programs capable of being executed in the processor, the processor, when executing computer programs, performs the steps of the method debug the SerDes connection parameter according to any one of paragraphs. 1-7. 11. Computer storage medium, while instructions executed on a computer are stored on a computer storage medium, and instructions executed on a computer are configured to perform a method for debugging a SerDes connection parameter according to any one of claims. 1-7.

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