WO2018214319A1

WO2018214319A1 - Serdes link parameter debugging method and device, and computer storage medium

Info

Publication number: WO2018214319A1
Application number: PCT/CN2017/099278
Authority: WO
Inventors: 李强
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2017-05-26
Filing date: 2017-08-28
Publication date: 2018-11-29
Also published as: CN108933600A; KR20200011488A; KR102230236B1; RU2733809C9; CN108933600B; RU2733809C1

Abstract

Disclosed are a SerDes link parameter debugging method and device, and a computer storage medium. The method involves: based on a link clock and a channel characteristic, determining a codec mode; determining a forward error correction method and a check code; determining a pre-emphasis parameter range, and according to the pre-emphasis parameter range, the forward error correction method and the check code, training a sending side of a high-speed serial-to-parallel/parallel-to-serial converter to be debugged so as to obtain a pre-emphasis configuration parameter; and after determining the pre-emphasis configuration parameter, carrying out equalization parameter training on a receiving side of the high-speed serial-to-parallel/parallel-to-serial converter to be debugged so as to obtain a self-adaptive configuration parameter.

Description

SerDes link parameter debugging method, device and computer storage medium

Cross-reference to related applications

The present application is based on a Chinese patent application filed on Jan. 26, 2017, the entire disclosure of which is hereby incorporated by reference.

Technical field

The invention belongs to the field of SerDes communication application, and particularly relates to a SerDes link parameter debugging method, device and computer storage medium.

Background technique

With the increase of broadband demand and service scale, higher requirements are put forward for efficient data transmission, and the stability of data transmission in data transmission under high-rate channel is the key to achieve efficient data transmission.

SERDES is an abbreviation for SERializer/DESerializer. It is a Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology, including multiple low-speed parallel signals transmitted to high-speed serial signals at the transmitting end, through a transmission medium (such as fiber optic cable or copper). Line), and finally the high-speed serial signal is reconverted to a low-speed parallel signal at the receiving end. This point-to-point serial communication technology makes full use of the channel capacity of the transmission medium, reduces the number of transmission channels and device pins required, thereby greatly reducing communication costs, and is widely used in various large switches and router devices. However, the improvement of transmission performance is accompanied by strict precision control. Therefore, it is extremely important to strictly control the deviation of the environment and the device caused by Serdes during operation at high speed to ensure or even improve the stability of transmission.

Summary of the invention

In order to solve the deficiencies of the prior art, embodiments of the present invention are expected to provide a SerDes link parameter debugging method, apparatus, and computer storage medium to ensure even improve the stability of high-speed data transmission.

To achieve the above object, an embodiment of the present invention provides a method for debugging a SerDes link parameter, where the method includes:

Determining a codec mode based on a link clock and channel characteristics; determining a forward error correction method and a check code;

Determining a pre-emphasis parameter range, performing training on the transmitting side of the high-speed parallel/parallel-serial converter according to the pre-emphasis parameter range, the forward error correction method, and the check code to obtain a pre-emphasis configuration parameter;

After determining the pre-emphasis configuration parameter, performing equalization parameter training on the receiving side of the high-speed serial/parallel-to-serial converter to be debugged, to obtain an adaptive configuration parameter.

In an embodiment, the codec mode includes at least one of the following codec modes: an 8B codec mode, a 10B codec mode, a 64B codec mode, and a 66B codec mode.

In an embodiment, the forward error correction method is an RS-FEC forward error correction method; and the check code is a CRC16 check code.

In an embodiment, the training according to the pre-emphasis parameter range, the forward error correction method, and the check code to be debugged on the transmitting side of the high-speed serial/parallel-to-serial converter includes:

Setting a selection range of the pre-emphasis parameter, and selecting, according to the training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameter as a transmission side configuration parameter of the high-speed serial/parallel-to-serial converter to be debugged;

On the receiving side of the high speed serial/parallel converter to be debugged, the verification is restored according to the forward error correction method; if a CRC error occurs during the restoration verification, it is determined that the selected combination of pre-emphasis parameters is unavailable. Back to the training direction opposite or parallel to the training direction, according to the new training The training direction selects a combination of another set of pre-emphasis parameters as a transmission side configuration parameter of the high speed serial/parallel converter to be debugged, on the receiving side of the high speed serial/parallel converter to be debugged, according to the The forward error correction method restores the verification; no CRC error occurs during the restoration verification process;

Traversing all of the pre-emphasis parameters in the pre-emphasis parameter range, and recording a combination of the pre-emphasis parameters of the restoration check and no CRC error is determined as a combination of available pre-emphasis parameters;

Traversing the SerDes link, obtaining a combination of pre-emphasis parameters available in the SerDes link, and finding a combination of pre-emphasis parameters available for a set of SerDes links as pre-emphasis configuration parameters.

In an embodiment, each time a combination of a set of pre-emphasis configuration parameters is selected as the pre-emphasis configuration parameter of the transmitting side of the high-speed serial/parallel-to-serial converter to be debugged, Before the receiving side of the string converter performs adaptive equalization training, the preset duration is delayed, and the preset duration is any one of 200 to 300 microseconds.

In an embodiment, in the process of determining the pre-emphasis configuration parameter and the adaptive configuration parameter, the method includes a timing control, and the method includes:

Sending a notification that the link transmitting side starts pre-emphasis configuration to the SerDes link in which the communication relationship exists;

After a combination of a set of pre-emphasis configuration parameters is selected as the pre-emphasis configuration parameter on the transmitting side of the link, the preset duration is extended, and the receiving side of the SerDes link having the communication relationship is sent to the receiving side to start the adaptive parameter configuration. Notice;

After determining the pre-emphasis configuration parameter, performing equalization parameter training on the receiving side of the link to obtain an adaptive configuration parameter.

In an embodiment, after traversing the pre-emphasis parameters in all the selected ranges, the receiving side of any of the SerDes links still has a CRC error, and after the receiving side is trained by the equalization parameter, the restoration verification process still appears. If the CRC reports an error, the SerDes link is marked as unavailable.

The embodiment of the present invention further provides a SerDes link parameter debugging device, where the device includes: a determining unit, a first training unit, and a second training unit; wherein

The determining unit is configured to determine a codec mode based on a link clock and a channel characteristic; determine a forward error correction method and a check code; and further configured to determine a pre-emphasis parameter range;

The first training unit is configured to perform training according to the pre-emphasis parameter range, the forward error correction method, and the check code to debug the transmitting side of the high-speed serial/parallel-to-serial converter, to obtain pre-emphasis configuration parameters;

The second training unit is configured to perform equalization parameter training on the receiving side of the high speed serial/parallel converter to be debugged after the first training unit determines the pre-emphasis configuration parameter, to obtain an adaptive configuration. parameter.

In an embodiment, the first training unit is configured to set a selection range of pre-emphasis parameters, and select, according to the training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameters, as the waiting Debugging a transmission side configuration parameter of the high speed serial/parallel converter; on the receiving side of the high speed serial/parallel converter to be debugged, restoring the verification according to the forward error correction method; A CRC error occurs, determining that the selected combination of pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the current training direction, and selecting a combination of another set of pre-emphasis parameters as the high speed to be debugged according to the new training direction. Transmitting side configuration parameters of the serial/parallel converter, on the receiving side of the high speed serial/parallel converter to be debugged, re-restoring the verification according to the forward error correction method; A CRC error occurs; traversing all pre-emphasis parameters in the range of pre-emphasis parameters, and recording a combination of pre-emphasis parameters of the restoration check without CRC error is determined as a combination of available pre-emphasis parameters; Traversing the SerDes link, obtaining a combination of pre-emphasis parameters available in the SerDes link, and finding a combination of pre-emphasis parameters available for a set of SerDes links as pre-emphasis configuration parameters.

An embodiment of the present invention further provides a SerDes link parameter debugging apparatus, including: a processor and a memory for storing a computer program capable of running on a processor, wherein when the processor is used to run the computer program, The steps of the SerDes link parameter debugging method in the embodiment of the present invention are performed.

The embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the SerDes link parameter debugging method according to the embodiment of the invention.

The method and device for debugging the SerDes link parameters and the computer storage medium provided by the embodiments of the present invention perform training on pre-emphasis parameters on the transmitting side and training adjustment adjustment on the receiving side on the receiving side. By strictly controlling the configuration parameters to avoid interference caused by the two-way communication of the link, the deviation in the link parameter configuration process is avoided, and the accuracy of the set link parameters is further ensured, thereby ensuring and even improving the stability of the transmission. The embodiments of the present invention are applicable to various router backplanes, and implement automatic debugging of each link parameter for a high-rate SerDes link.

DRAWINGS

The drawings are intended to provide a further understanding of the invention, and are intended to be a part of the description of the invention. In the drawing:

1 is a schematic flowchart of a method for debugging a SerDes link parameter according to an embodiment of the present invention;

2 is a schematic diagram of a back-tracking of a training side of a transmitting side according to the present invention;

3 is a schematic diagram of a timing control process of the present invention.

detailed description

The preferred embodiments of the present invention are described in the following with reference to the accompanying drawings.

FIG. 1 is a schematic flowchart of a method for debugging a SerDes link parameter according to an embodiment of the present invention. As shown in FIG. 1, the method includes:

Step 1: determining a codec mode based on a link clock and a channel characteristic; determining a forward error correction method and a check code;

Step 2, determining a pre-emphasis parameter range, according to the pre-emphasis parameter range, the forward correction The wrong method and the check code are used to train the transmitting side (ie, the TX side) of the high speed serial/parallel converter to be debugged, to obtain pre-emphasis configuration parameters;

Step 3: After determining the pre-emphasis configuration parameter, perform equalization parameter training on the receiving side (ie, the RX side) of the high-speed serial/parallel-to-serial converter to be debugged, to obtain an adaptive configuration parameter.

The SerDes link parameter debugging method in the embodiment of the present invention can be applied to a test device. Before performing the SerDes link parameter debugging method in the embodiment of the present invention, it is first necessary to establish a test device and a high-speed SerDes to be debugged.

In this embodiment, based on the consideration of the link clock and the channel, the data stream in the data transmission is not modified and interfered; wherein the codec mode includes at least one of the following codec modes: 8B codec mode, 10B codec mode, 64B codec mode, 66B codec mode. As an embodiment, the codec mode may select a 64B/66B codec mode. Compared with the 8B/10B codec mode, the 64B/66B codec mode can ensure the data length integrity and data encoding efficiency, and can meet the bandwidth requirements of large switches and routers in high-speed data transmission, and reduce the data transmission process. Lost.

The Forward Error Correction (FEC) method can select the RS-FEC forward error correction method, where RS is the abbreviation of the code, and the English is called Reed-Solomon codes. The check code can be selected as a CRC16 check code. RS-FEC forward error correction method and CRC16 check mark can be used to enhance data adaptation and fault tolerance. In this embodiment, the data length of each frame of the RS may be 528 bits, and the information bit is 514 bits. This error correction method can ensure burst error correction capability of 10 bits or even 70 bits continuously in one frame data transmission.

In the data transmitted by the TX side, each frame of data is marked with a check mark (for example, a CRC check mark) according to the above rules according to the contents of the frame data stream. Correcting possible data modification during transmission by a forward error correction method (such as RS-FEC) in high-speed link serial transmission, and verifying the frame data according to a check code (for example, CRC16) on the RX side. Whether the frame data is complete. If the data of the frame length cannot be guaranteed to be complete and error-free through the error correction of the RS code, the CRC checker The frame data will be discarded.

Referring to the training and backtracking direction diagram of FIG. 2, in the embodiment, the transmitting side of the high speed serial/parallel converter to be debugged is performed according to the pre-emphasis parameter range, the forward error correction method, and the check code. Train to get pre-emphasis configuration parameters, including:

Step 201: Set a selection range of the pre-emphasis parameter, and select, according to the training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameter, as the transmitting side of the high-speed serial/parallel converter to be debugged a configuration parameter, where the sending side sends a message based on the configuration parameter and the determined codec mode;

Step 202: On the receiving side of the high-speed serial/parallel-to-serial converter to be debugged, restore and verify the message according to the forward error correction method; if a CRC error occurs during the verification process, determine the selected The combination of pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the combination of the pre-emphasis parameters selected this time, jumping to step 201, selecting a combination of another set of pre-emphasis parameters according to the new training direction as described The transmitting side configuration parameter of the high speed serial/parallel converter to be debugged is re-restored according to the forward error correction method on the receiving side of the high speed serial/parallel converter to be debugged; otherwise, if the restoration is performed If the CRC error does not occur during the verification process, the process proceeds to step 203;

Step 203, traversing the pre-emphasis parameter in the pre-emphasis parameter range according to the method of step 201 to step 202, and recording a combination of the pre-emphasis parameter of the restoration check without CRC error is confirmed as a combination of available pre-emphasis parameters;

Step 204: Based on the method of step 201 to step 203, traverse all the SerDes links, and obtain a combination of pre-emphasis parameters available in all SerDes links as pre-emphasis configuration parameters. As an embodiment, if the combination of available pre-emphasis parameters as pre-emphasis configuration parameters is at least two groups, a combination of one of the available pre-emphasis parameters may be searched for as a pre-emphasis configuration parameter.

In the actual SerDes debugging, due to the irregularity caused by the routing, etc., whether the CRC error is generated during the FEC check error correction calculation on the RX side is the criterion for detecting the link: If the SerDes condition does not follow the regular changes of the ontology algorithm, but develops in the direction of deterioration, an ERR flag is generated. At this time, the combination of the pre-emphasis parameters does not meet the requirements, and the combination of recording the pre-emphasis parameters is not used, and the combination of another set of pre-emphasis parameters is selected in the opposite or parallel direction for adjustment. This adjustment process is a retrospective process. After the selection of the backtracking algorithm and traversing, after traversing all the links, a set of SerDes pre-emphasis parameters suitable for all links is found as the final pre-emphasis configuration parameter.

In this embodiment, the equalization parameter training is performed on the receiving side of the high speed serial/parallel converter to be debugged, including:

According to the AC coupling capacitor configuration of the Serdes link, the matching of the DFE training mode, the insertion loss of different channels, and the voltage power consumption requirements of the high-rate transmission, based on whether the actual signal on the receiving side is complete and convergent, select one. Group-balanced adaptive configuration parameters;

The coupling capacitor will cause voltage fluctuation on the receiving side, which will interfere with the received signal, and the clock will be unstable. The link traces on the backplane will generate different link channel insertion loss; the transmitter will have high-intensity or low-intensity signals. The training that causes the gain on the receiving side will be invalid.

Therefore, if there is a coupling capacitor in the backplane design, the receiving side can set the coupling capacitor to terminate at a high impedance point to eliminate the influence of the capacitor, otherwise it will not be configured;

If the backplane routing is too short, the strong balance of the link itself will have a negative impact on the simultaneous convergence of the adaptive algorithms. The DAC adaptive algorithm of the link itself can be turned off, and the manual configuration equalization parameters are used to ensure the signal. Convergence and smoothing;

If the sampling of the signal itself is incomplete and unsmooth, the gain control can be turned off, the Peaking control, and the appropriate equalization parameters can be adjusted by manually setting the gain parameter and the peaking value;

If an intermittent CRC check error occurs on the receiving side, the DFE training mode can be adjusted, and the improvement is adjusted by the configuration and training of the order parameters;

If the high-rate signal transmission requires power consumption, you can turn off the receiving-side power management function.

FIG. 3 is a schematic diagram of the two sequenced control steps in the process of determining the pre-emphasis configuration parameters and the adaptive configuration parameters in the process of determining the pre-emphasis configuration parameters and the adaptive configuration parameters, including:

Step a, Lane_A reports the notification that the link transmitting side starts pre-emphasis configuration to the Lane_B link in which the communication relationship exists, and Lane_B also reports to Lane_A that the link transmitting side starts pre-emphasis configuration.

Step b: The transmitting side of the Lane_A and Lane_B links are in the order of the foregoing steps 201 to 204, and the transmitting side pre-emphasis configuration parameters of the Lane_A and Lane_B links are completed. After the pre-emphasis configuration is completed, the receiving sides of the Lane_A and Lane_B links are self-contained. Before adapting to the equalization training and the restoration check, the preset duration (for example, 200 to 300 microseconds) may be delayed, and the adaptive receiving parameter of the link receiving side is sent to the opposite end (the receiving side of the SerDes link having the communication relationship). Configured notifications;

In step c, the Lane_A and Lane_B links start to equalize the link, and the adaptive configuration parameters are obtained according to the method described in the foregoing step 3.

Finally, the Lane_A and Lane_B links select and count the pre-emphasis configuration parameters on the transmitting side by using the FCE error correction flag on the receiving side as the criterion for determining whether the CRC error flag is generated.

This timing control mode ensures that the transmitting side is in effect first, and is slightly delayed, and then configures the receiving side parameters. In the high-speed backplane of the router, thousands of Serdes links are guaranteed, and the pre-emphasis parameters of the transmitting side and the adaptive parameters of the receiving side are sequentially implemented to enhance the stability of the backplane as a whole.

The advantages of the embodiments of the present invention are mainly as follows: starting from a high-rate data frame sent by the Serdes link, responding to burst errors of the link by coding and error correction on the link, and processing burst errors and erroneous data in time. Correction is performed to enhance the transmission efficiency of data frames. In the adaptive adjustment function of the receiving side Serdes, the random convergence of the received data stream is achieved. The converged code stream is a complete transmission message without bit disorder or modification, and the message in the link transmission is error-free. ERR, no signal interference or loss for the purpose of efficient and stable frame data reception. Further, this party The method also ensures the accuracy and integrity of the data through the CRC check on the receiving side, and avoids frame loss caused by misjudgment during data processing and verification.

In this embodiment, the codec mode includes at least one of the following codec modes: an 8B codec mode, a 10B codec mode, a 64B codec mode, and a 66B codec mode. The forward error correction method may be an RS-FEC forward error correction method; the check code may be a CRC16 check code.

As an implementation manner, the first training unit is configured to set a selection range of pre-emphasis parameters, and select, according to the training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameters, as the Debugging a transmission side configuration parameter of the high speed serial/parallel converter; on the receiving side of the high speed serial/parallel converter to be debugged, restoring the verification according to the forward error correction method; A CRC error occurs, determining that the selected combination of pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the current training direction, and selecting a combination of another set of pre-emphasis parameters as the high speed to be debugged according to the new training direction. Transmitting side configuration parameters of the serial/parallel converter, on the receiving side of the high speed serial/parallel converter to be debugged, re-restoring the verification according to the forward error correction method; A CRC error occurs; traversing all the pre-emphasis parameters in the pre-emphasis parameter range, and recording the pre-emphasis of the restoration check without CRC error The combination of parameters is determined as a combination of available pre-emphasis parameters; traversing the SerDes link, obtaining a combination of pre-emphasis parameters available in the SerDes link, and finding a combination of pre-emphasis parameters available for a set of SerDes links as a pre-emphasis configuration parameter .

In an embodiment, the second training unit is configured to select, at the first time, the combination of a set of pre-emphasis configuration parameters at the first training unit as the transmitting side of the high-speed serial/parallel converter to be debugged. After the configuration parameter is pre-emphasized, the preset duration is delayed before the restoration check of the high-speed serial/parallel converter to be debugged, and the preset duration is any one of 200 to 300 microseconds. .

As an implementation manner, the apparatus further includes: a sending unit, configured to send, to the SerDes link that has a communication relationship, a notification that the link sending side starts pre-emphasis configuration;

The first training unit is configured to select a combination of pre-emphasis configuration parameters as the pre-emphasis configuration parameter on the transmitting side of the link, and delay the preset duration;

The sending unit is further configured to send, to the receiving side of the SerDes link in which the communication relationship exists, a notification that the link receiving side starts adaptive parameter configuration;

The second training unit is configured to perform the equalization parameter training on the receiving side of the link after the first training unit determines the pre-emphasis configuration parameter, to obtain an adaptive configuration parameter.

In practical applications, the determining unit, the first training unit, and the second training unit may be implemented by a central processing unit (CPU), a microprocessor (MPU, a digital processor unit), and a digital signal in practical applications. Implemented by a processor (DSP, Digital Signal Processor) or a Field Programmable Gate Array (FPGA).

It should be noted that the SerDes link parameter debugging apparatus provided in the foregoing embodiment is only illustrated by the division of each of the foregoing program modules when performing link parameter debugging. In actual applications, the foregoing processing may be assigned differently according to requirements. The program module is completed, that is, the internal structure of the SerDes link parameter debugging device is divided into different program modules to complete all the above descriptions. Or partial processing. In addition, the SerDes link parameter debugging device and the SerDes link parameter debugging method are provided in the same embodiment, and the specific implementation process is described in detail in the method embodiment, and details are not described herein again.

An embodiment of the present invention further provides a SerDes link parameter debugging apparatus, including: a processor and a memory for storing a computer program capable of running on a processor, wherein when the processor is used to run the computer program, Execution: determining a codec mode based on a link clock and channel characteristics; determining a forward error correction method and a check code; determining a pre-emphasis parameter range, according to the pre-emphasis parameter range, the forward error correction method, and a check code Performing training on the transmitting side of the debug high speed serial/parallel converter to obtain pre-emphasis configuration parameters; after determining the pre-emphasis configuration parameters, balancing the receiving side of the high-speed serial/parallel converter to be debugged Parameter training, get adaptive configuration parameters.

In one embodiment, when the processor is configured to run the computer program, performing: setting a selection range of pre-emphasis parameters, and selecting a combination of a set of pre-emphasis parameters from a selection range of the pre-emphasis parameters according to a training direction As a transmission side configuration parameter of the high speed serial/parallel converter to be debugged; on the receiving side of the high speed serial/parallel converter to be debugged, the verification is restored according to the forward error correction method; A CRC error occurs during the restoration check process, and it is determined that the combination of the selected pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the current training direction, and selecting another combination of pre-emphasis parameters according to the new training direction. Transmitting side configuration parameters of the high speed serial/parallel converter to be debugged, on the receiving side of the high speed serial/parallel converter to be debugged, re-restoring the verification according to the forward error correction method; No CRC error occurs during the verification process; traversing all the pre-emphasis parameters in the range of pre-emphasis parameters, and recording the combination of the pre-emphasis parameters of the restoration check without CRC error is determined as A combination of pre-emphasis parameters can be used; the SerDes link is traversed, a combination of pre-emphasis parameters available in the SerDes link is obtained, and a combination of pre-emphasis parameters available for a set of SerDes links is searched for as a pre-emphasis configuration parameter.

As an implementation manner, when the processor is used to run the computer program, perform: Each time a combination of a set of pre-emphasis configuration parameters is selected as the pre-emphasis configuration parameter of the transmitting side of the high-speed serial/parallel-to-serial converter to be debugged, on the receiving side of the high-speed serial/parallel converter to be debugged Before the restoration check is performed, the preset duration is delayed, and the preset duration is any one of 200 to 300 microseconds.

As an implementation manner, when the processor is configured to run the computer program, perform: to a SerDes link having a communication relationship, in determining a pre-emphasis configuration parameter and an adaptive configuration parameter, to a SerDes having a communication relationship The link sends a notification that the transmitting side of the link starts pre-emphasis configuration; after selecting a combination of a set of pre-emphasis configuration parameters as the pre-emphasis configuration parameter of the transmitting side of the link, delaying the preset duration to the SerDes chain having the communication relationship The receiving side of the path sends a notification that the receiving side of the link starts to configure the adaptive parameter. After determining the pre-emphasis configuration parameter, the receiving side of the link is trained on the equalization parameter to obtain an adaptive configuration parameter.

As an implementation manner, when the processor is configured to run the computer program, if: after traversing all pre-emphasis parameters, a CRC error occurs on a receiving side of any one of the SerDes links, and the receiving side is balanced. After the parameter training, the restore verification process is marked as CRC error, indicating that the SerDes link is unavailable.

In an embodiment of the invention, the memory may be implemented by any type of volatile or non-volatile storage device, or a combination thereof. The non-volatile memory may be a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), or an Erasable Programmable Read (EPROM). Only Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, Magnetic Surface Memory , CD-ROM, or Compact Disc Read-Only Memory (CD-ROM); the magnetic surface memory can be a disk storage or a tape storage. The volatile memory may be a random access memory (RAM), which is used as External cache. By way of example and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access (SSRAM). DRAM (Dynamic Random Access Memory), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), enhancement Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory Bus Random Access Memory (DRRAM) ). The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memory.

The memory is used to store various types of data to support the operation of the SerDes link parameter debugging device. Examples of such data include any computer program for operation on a SerDes link parameter debug device. The operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks. The application can include various applications, such as a Media Player, a Browser, etc., for implementing various application services. A program implementing the method of the embodiment of the present invention may be included in an application.

The processor in the SerDes link parameter debugging device may be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above method may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software. The above described processor may be a general purpose processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like. The processor may implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present invention. A general purpose processor can be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiment of the present invention may be directly implemented as a hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, the storage medium being located in the memory, the processor reading the information in the memory, and completing the steps of the foregoing methods in combination with the hardware thereof.

In an exemplary embodiment, the SerDes link parameter debugging device may be configured by at least one Application Specific Integrated Circuit (ASIC), DSP, Programmable Logic Device (PLD), and Complex Programmable Logic Device ( CPLD (Complex Programmable Logic Device), FPGA, general purpose processor, controller, MCU, microprocessor, or other electronic component implementation for performing the aforementioned method.

An embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions for performing: determining a codec mode based on a link clock and a channel characteristic; a method for correcting errors and a check code; determining a range of pre-emphasis parameters, and training the transmitting side of the high-speed serial/parallel-to-serial converter according to the pre-emphasis parameter range, the forward error correction method, and the check code, Obtaining a pre-emphasis configuration parameter; after determining the pre-emphasis configuration parameter, performing equalization parameter training on the receiving side of the high-speed serial/parallel-to-serial converter to be debugged, to obtain an adaptive configuration parameter.

In one embodiment, the computer executable instructions are configured to: set a selection range of pre-emphasis parameters, and select, according to a training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameters, as a transmission side configuration parameter of the high speed serial/parallel converter to be debugged; on the receiving side of the high speed serial/parallel converter to be debugged, the verification is restored according to the forward error correction method; if the verification process is restored A CRC error occurs, determining that the selected combination of pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the current training direction, and selecting another combination of pre-emphasis parameters as the to-be-commissioned according to the new training direction. a transmission side configuration parameter of the high speed serial/parallel converter, on the receiving side of the high speed serial/parallel converter to be debugged, re-restoring the verification according to the forward error correction method; until the restoration verification process No CRC error occurred; A combination of all pre-emphasis parameters in the pre-emphasis parameter range, a record of the pre-emphasis parameter that records the restoration check and no CRC error is determined as a combination of available pre-emphasis parameters; traversing the SerDes link to obtain pre-emphasis available in the SerDes link A combination of parameters that finds a combination of pre-emphasis parameters available for a set of SerDes links as a pre-emphasis configuration parameter.

In one embodiment, the computer executable instructions are configured to: each time select a combination of a set of pre-emphasis configuration parameters as a pre-emphasis configuration parameter of a transmitting side of the high speed serial/parallel converter to be debugged, Before the restoration check of the high-speed serial/parallel converter to be debugged, the preset duration is delayed, and the preset duration is any one of 200 to 300 microseconds.

In one embodiment, the computer executable instructions are configured to: in the process of determining a pre-emphasis configuration parameter and an adaptive configuration parameter for a SerDes link having a communication relationship, sending the present to a SerDes link having a communication relationship The link sending side starts the pre-emphasis configuration notification; after selecting a combination of a set of pre-emphasis configuration parameters as the pre-emphasis configuration parameter of the transmitting side of the link, delaying the preset duration to the receiving side of the SerDes link having the communication relationship Sending a notification that the receiving side of the link starts adaptive parameter configuration; after determining the pre-emphasis configuration parameter, performing equalization parameter training on the receiving side of the link to obtain an adaptive configuration parameter.

As an embodiment, the computer executable instructions are configured to: after traversing all the pre-emphasis parameters, a CRC error occurs on the receiving side of any one of the SerDes links, and the receiving side is trained by the equalization parameter. The restore verification process marks the SerDes link as unavailable due to a CRC error.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, or direct coupling, or communication connection of the various components shown or discussed may be through some interface, device or unit. The indirect coupling or communication connection can be electrical, mechanical or other form.

The units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; The unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to the program instructions. The foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a removable storage device, a ROM, a RAM, a magnetic disk, or an optical disk, and the like, which can store program codes.

Alternatively, the above-described integrated unit of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a standalone product. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a RAM, a magnetic disk, or an optical disk.

The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of protection of the claims.

Industrial applicability

The technical solution of the embodiment of the present invention starts from a high-rate data frame sent by the Serdes link, and responds to a burst error of the link by coding and error correction on the link, and timely processes the burst error and corrects the error data. Enhance the transmission efficiency of data frames. In the adaptive adjustment function of the receiving side Serdes, the random convergence of the received data stream is achieved. The converged code stream is a complete transmission message without bit disorder or modification, and the message in the link transmission is error-free. ERR, no signal interference or loss for the purpose of efficient and stable frame data reception. Further, the method also ensures the accuracy and integrity of the data by the CRC check on the receiving side, and avoids frame loss caused by misjudgment during data processing and verification.

Claims

A method for debugging a SerDes link parameter, the method comprising:

Determining a codec mode based on a link clock and channel characteristics; determining a forward error correction method and a check code;

Determining a pre-emphasis parameter range, performing training on the transmitting side of the high-speed serial/parallel-to-serial converter according to the pre-emphasis parameter range, the forward error correction method, and the check code to obtain a pre-emphasis configuration parameter;

After determining the pre-emphasis configuration parameter, performing equalization parameter training on the receiving side of the high-speed serial/parallel-to-serial converter to be debugged, to obtain an adaptive configuration parameter.
The method of claim 1, wherein the codec mode comprises at least one of a codec mode: an 8B codec mode, a 10B codec mode, a 64B codec mode, and a 66B codec mode.
The method of claim 1, wherein the forward error correction method is an RS-FEC forward error correction method; the check code is a CRC16 check code.
The method according to claim 3, wherein said training according to said pre-emphasis parameter range, said forward error correction method and a check code to debug a high-speed serial/parallel-to-serial converter is performed Add configuration parameters, including:

Setting a selection range of the pre-emphasis parameter, and selecting, according to the training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameter as a transmission side configuration parameter of the high-speed serial/parallel-to-serial converter to be debugged;

On the receiving side of the high speed serial/parallel converter to be debugged, the verification is restored according to the forward error correction method; if a CRC error occurs during the restoration verification, it is determined that the selected combination of pre-emphasis parameters is unavailable. Returning to the training direction opposite or parallel to the current training direction, selecting another combination of pre-emphasis parameters according to the new training direction as the transmission side configuration parameter of the high-speed serial/parallel converter to be debugged, Describe the receiving side of the debug high speed serial/parallel converter, according to The forward error correction method re-restores the verification; no CRC error occurs during the restoration verification process;

Traversing all of the pre-emphasis parameters in the pre-emphasis parameter range, and recording a combination of the pre-emphasis parameters of the restoration check and no CRC error is determined as a combination of available pre-emphasis parameters;

Traversing the SerDes link, obtaining a combination of pre-emphasis parameters available in the SerDes link, and finding a combination of pre-emphasis parameters available for a set of SerDes links as pre-emphasis configuration parameters.
The method of claim 4, wherein each time a combination of a set of pre-emphasis configuration parameters is selected as the pre-emphasis configuration parameter of the transmitting side of the high-speed serial/parallel-to-serial converter to be debugged, Before the restoration side of the high speed serial/parallel converter performs the restoration check, the preset duration is delayed, and the preset duration is any one of 200 to 300 microseconds.
The method according to claim 5, wherein, in the process of determining the pre-emphasis configuration parameter and the adaptive configuration parameter, the sequence control is further included in the process of determining the pre-emphasis configuration parameter and the adaptive configuration parameter.

Sending a notification that the link transmitting side starts pre-emphasis configuration to the SerDes link in which the communication relationship exists;

After a combination of a set of pre-emphasis configuration parameters is selected as the pre-emphasis configuration parameter on the transmitting side of the link, the preset duration is delayed, and the receiving side of the SerDes link having the communication relationship is sent to the receiving side to start adaptive parameter configuration. announcement of;

After determining the pre-emphasis configuration parameter, performing equalization parameter training on the receiving side of the link to obtain an adaptive configuration parameter.
The method according to claim 6, wherein if the CRC error is still present on the receiving side of any of the SerDes links after traversing all the pre-emphasis parameters, and the receiving side is trained by the equalization parameter, the restoration verification process is performed. If a CRC error occurs, the SerDes link is marked as unavailable.
A SerDes link parameter debugging device, the device comprising: a determining unit, a first training unit and a second training unit; wherein

The determining unit is configured to determine a codec mode based on a link clock and a channel characteristic; Determining a forward error correction method and a check code; further configured to determine a range of pre-emphasis parameters;

The first training unit is configured to perform training according to the pre-emphasis parameter range, the forward error correction method, and the check code to debug the transmitting side of the high-speed serial/parallel-to-serial converter, to obtain pre-emphasis configuration parameters;

The second training unit is configured to perform equalization parameter training on the receiving side of the high speed serial/parallel converter to be debugged after the first training unit determines the pre-emphasis configuration parameter, to obtain an adaptive configuration. parameter.
The apparatus according to claim 8, wherein the first training unit is configured to set a selection range of pre-emphasis parameters, and select a combination of a set of pre-emphasis parameters from a selection range of the pre-emphasis parameters according to a training direction As a transmission side configuration parameter of the high speed serial/parallel converter to be debugged; on the receiving side of the high speed serial/parallel converter to be debugged, the verification is restored according to the forward error correction method; A CRC error occurs during the restoration check process, and it is determined that the combination of the selected pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the current training direction, and selecting another combination of pre-emphasis parameters according to the new training direction. Transmitting side configuration parameters of the high speed serial/parallel converter to be debugged, on the receiving side of the high speed serial/parallel converter to be debugged, re-restoring the verification according to the forward error correction method; No CRC error occurs during the verification process; traversing all the pre-emphasis parameters in the range of pre-emphasis parameters, and recording the combination of the pre-emphasis parameters of the restoration check without CRC error is determined to be available Emphasis parameter combination; SerDes link traversal, obtain a combination of pre-emphasis parameter SerDes link available to find a combination of a set of links are available SerDes pre-emphasis parameter, a pre-emphasis configuration parameters.
A SerDes link parameter debugging apparatus, comprising: a processor and a memory for storing a computer program executable on a processor, wherein the processor is configured to execute any one of claims 1 to 7 when the computer program is executed A step of the SerDes link parameter debugging method.
A computer storage medium storing computer executable in the computer storage medium The line of instructions for executing the SerDes link parameter debugging method of any one of claims 1 to 7.