WO2018214319A1 - Procédé et dispositif de débogage de paramètre de liaison serdes et support de stockage informatique - Google Patents

Procédé et dispositif de débogage de paramètre de liaison serdes et support de stockage informatique Download PDF

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Publication number
WO2018214319A1
WO2018214319A1 PCT/CN2017/099278 CN2017099278W WO2018214319A1 WO 2018214319 A1 WO2018214319 A1 WO 2018214319A1 CN 2017099278 W CN2017099278 W CN 2017099278W WO 2018214319 A1 WO2018214319 A1 WO 2018214319A1
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Prior art keywords
emphasis
parameter
parameters
training
combination
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PCT/CN2017/099278
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English (en)
Chinese (zh)
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李强
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深圳市中兴微电子技术有限公司
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Priority to KR1020197038332A priority Critical patent/KR102230236B1/ko
Priority to RU2019143884A priority patent/RU2733809C9/ru
Publication of WO2018214319A1 publication Critical patent/WO2018214319A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Definitions

  • the invention belongs to the field of SerDes communication application, and particularly relates to a SerDes link parameter debugging method, device and computer storage medium.
  • SERDES is an abbreviation for SERializer/DESerializer. It is a Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology, including multiple low-speed parallel signals transmitted to high-speed serial signals at the transmitting end, through a transmission medium (such as fiber optic cable or copper). Line), and finally the high-speed serial signal is reconverted to a low-speed parallel signal at the receiving end.
  • TDM Time Division Multiplexing
  • This point-to-point serial communication technology makes full use of the channel capacity of the transmission medium, reduces the number of transmission channels and device pins required, thereby greatly reducing communication costs, and is widely used in various large switches and router devices.
  • the improvement of transmission performance
  • embodiments of the present invention are expected to provide a SerDes link parameter debugging method, apparatus, and computer storage medium to ensure even improve the stability of high-speed data transmission.
  • an embodiment of the present invention provides a method for debugging a SerDes link parameter, where the method includes:
  • Determining a pre-emphasis parameter range performing training on the transmitting side of the high-speed parallel/parallel-serial converter according to the pre-emphasis parameter range, the forward error correction method, and the check code to obtain a pre-emphasis configuration parameter;
  • the codec mode includes at least one of the following codec modes: an 8B codec mode, a 10B codec mode, a 64B codec mode, and a 66B codec mode.
  • the forward error correction method is an RS-FEC forward error correction method
  • the check code is a CRC16 check code
  • the training according to the pre-emphasis parameter range, the forward error correction method, and the check code to be debugged on the transmitting side of the high-speed serial/parallel-to-serial converter includes:
  • the verification is restored according to the forward error correction method; if a CRC error occurs during the restoration verification, it is determined that the selected combination of pre-emphasis parameters is unavailable.
  • the training direction selects a combination of another set of pre-emphasis parameters as a transmission side configuration parameter of the high speed serial/parallel converter to be debugged, on the receiving side of the high speed serial/parallel converter to be debugged, according to the The forward error correction method restores the verification; no CRC error occurs during the restoration verification process;
  • the method in the process of determining the pre-emphasis configuration parameter and the adaptive configuration parameter, includes a timing control, and the method includes:
  • the preset duration is extended, and the receiving side of the SerDes link having the communication relationship is sent to the receiving side to start the adaptive parameter configuration.
  • the receiving side of any of the SerDes links still has a CRC error, and after the receiving side is trained by the equalization parameter, the restoration verification process still appears. If the CRC reports an error, the SerDes link is marked as unavailable.
  • the embodiment of the present invention further provides a SerDes link parameter debugging device, where the device includes: a determining unit, a first training unit, and a second training unit; wherein
  • the determining unit is configured to determine a codec mode based on a link clock and a channel characteristic; determine a forward error correction method and a check code; and further configured to determine a pre-emphasis parameter range;
  • the first training unit is configured to perform training according to the pre-emphasis parameter range, the forward error correction method, and the check code to debug the transmitting side of the high-speed serial/parallel-to-serial converter, to obtain pre-emphasis configuration parameters;
  • the second training unit is configured to perform equalization parameter training on the receiving side of the high speed serial/parallel converter to be debugged after the first training unit determines the pre-emphasis configuration parameter, to obtain an adaptive configuration. parameter.
  • the first training unit is configured to set a selection range of pre-emphasis parameters, and select, according to the training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameters, as the waiting Debugging a transmission side configuration parameter of the high speed serial/parallel converter; on the receiving side of the high speed serial/parallel converter to be debugged, restoring the verification according to the forward error correction method; A CRC error occurs, determining that the selected combination of pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the current training direction, and selecting a combination of another set of pre-emphasis parameters as the high speed to be debugged according to the new training direction.
  • a CRC error occurs; traversing all pre-emphasis parameters in the range of pre-emphasis parameters, and recording a combination of pre-emphasis parameters of the restoration check without CRC error is determined as a combination of available pre-emphasis parameters; Traversing the SerDes link, obtaining a combination of pre-emphasis parameters available in the SerDes link, and finding a combination of pre-emphasis parameters available for a set of SerDes links as pre-emphasis configuration parameters.
  • An embodiment of the present invention further provides a SerDes link parameter debugging apparatus, including: a processor and a memory for storing a computer program capable of running on a processor, wherein when the processor is used to run the computer program, The steps of the SerDes link parameter debugging method in the embodiment of the present invention are performed.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the SerDes link parameter debugging method according to the embodiment of the invention.
  • the method and device for debugging the SerDes link parameters and the computer storage medium provided by the embodiments of the present invention perform training on pre-emphasis parameters on the transmitting side and training adjustment adjustment on the receiving side on the receiving side.
  • the embodiments of the present invention are applicable to various router backplanes, and implement automatic debugging of each link parameter for a high-rate SerDes link.
  • FIG. 1 is a schematic flowchart of a method for debugging a SerDes link parameter according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a back-tracking of a training side of a transmitting side according to the present invention
  • FIG. 3 is a schematic diagram of a timing control process of the present invention.
  • FIG. 1 is a schematic flowchart of a method for debugging a SerDes link parameter according to an embodiment of the present invention. As shown in FIG. 1, the method includes:
  • Step 1 determining a codec mode based on a link clock and a channel characteristic; determining a forward error correction method and a check code;
  • Step 2 determining a pre-emphasis parameter range, according to the pre-emphasis parameter range, the forward correction
  • the wrong method and the check code are used to train the transmitting side (ie, the TX side) of the high speed serial/parallel converter to be debugged, to obtain pre-emphasis configuration parameters;
  • Step 3 After determining the pre-emphasis configuration parameter, perform equalization parameter training on the receiving side (ie, the RX side) of the high-speed serial/parallel-to-serial converter to be debugged, to obtain an adaptive configuration parameter.
  • the SerDes link parameter debugging method in the embodiment of the present invention can be applied to a test device. Before performing the SerDes link parameter debugging method in the embodiment of the present invention, it is first necessary to establish a test device and a high-speed SerDes to be debugged.
  • the codec mode includes at least one of the following codec modes: 8B codec mode, 10B codec mode, 64B codec mode, 66B codec mode.
  • the codec mode may select a 64B/66B codec mode. Compared with the 8B/10B codec mode, the 64B/66B codec mode can ensure the data length integrity and data encoding efficiency, and can meet the bandwidth requirements of large switches and routers in high-speed data transmission, and reduce the data transmission process. Lost.
  • the Forward Error Correction (FEC) method can select the RS-FEC forward error correction method, where RS is the abbreviation of the code, and the English is called Reed-Solomon codes.
  • the check code can be selected as a CRC16 check code.
  • RS-FEC forward error correction method and CRC16 check mark can be used to enhance data adaptation and fault tolerance.
  • the data length of each frame of the RS may be 528 bits, and the information bit is 514 bits.
  • This error correction method can ensure burst error correction capability of 10 bits or even 70 bits continuously in one frame data transmission.
  • each frame of data is marked with a check mark (for example, a CRC check mark) according to the above rules according to the contents of the frame data stream.
  • a check mark for example, a CRC check mark
  • the transmitting side of the high speed serial/parallel converter to be debugged is performed according to the pre-emphasis parameter range, the forward error correction method, and the check code.
  • Train to get pre-emphasis configuration parameters including:
  • Step 201 Set a selection range of the pre-emphasis parameter, and select, according to the training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameter, as the transmitting side of the high-speed serial/parallel converter to be debugged a configuration parameter, where the sending side sends a message based on the configuration parameter and the determined codec mode;
  • Step 202 On the receiving side of the high-speed serial/parallel-to-serial converter to be debugged, restore and verify the message according to the forward error correction method; if a CRC error occurs during the verification process, determine the selected The combination of pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the combination of the pre-emphasis parameters selected this time, jumping to step 201, selecting a combination of another set of pre-emphasis parameters according to the new training direction as described
  • the transmitting side configuration parameter of the high speed serial/parallel converter to be debugged is re-restored according to the forward error correction method on the receiving side of the high speed serial/parallel converter to be debugged; otherwise, if the restoration is performed If the CRC error does not occur during the verification process, the process proceeds to step 203;
  • Step 203 traversing the pre-emphasis parameter in the pre-emphasis parameter range according to the method of step 201 to step 202, and recording a combination of the pre-emphasis parameter of the restoration check without CRC error is confirmed as a combination of available pre-emphasis parameters;
  • Step 204 Based on the method of step 201 to step 203, traverse all the SerDes links, and obtain a combination of pre-emphasis parameters available in all SerDes links as pre-emphasis configuration parameters.
  • the combination of available pre-emphasis parameters as pre-emphasis configuration parameters is at least two groups, a combination of one of the available pre-emphasis parameters may be searched for as a pre-emphasis configuration parameter.
  • the equalization parameter training is performed on the receiving side of the high speed serial/parallel converter to be debugged, including:
  • the coupling capacitor will cause voltage fluctuation on the receiving side, which will interfere with the received signal, and the clock will be unstable.
  • the link traces on the backplane will generate different link channel insertion loss; the transmitter will have high-intensity or low-intensity signals.
  • the training that causes the gain on the receiving side will be invalid.
  • the receiving side can set the coupling capacitor to terminate at a high impedance point to eliminate the influence of the capacitor, otherwise it will not be configured;
  • the DAC adaptive algorithm of the link itself can be turned off, and the manual configuration equalization parameters are used to ensure the signal. Convergence and smoothing;
  • the gain control can be turned off, the Peaking control, and the appropriate equalization parameters can be adjusted by manually setting the gain parameter and the peaking value;
  • the DFE training mode can be adjusted, and the improvement is adjusted by the configuration and training of the order parameters;
  • FIG. 3 is a schematic diagram of the two sequenced control steps in the process of determining the pre-emphasis configuration parameters and the adaptive configuration parameters in the process of determining the pre-emphasis configuration parameters and the adaptive configuration parameters, including:
  • Step a Lane_A reports the notification that the link transmitting side starts pre-emphasis configuration to the Lane_B link in which the communication relationship exists, and Lane_B also reports to Lane_A that the link transmitting side starts pre-emphasis configuration.
  • Step b The transmitting side of the Lane_A and Lane_B links are in the order of the foregoing steps 201 to 204, and the transmitting side pre-emphasis configuration parameters of the Lane_A and Lane_B links are completed. After the pre-emphasis configuration is completed, the receiving sides of the Lane_A and Lane_B links are self-contained. Before adapting to the equalization training and the restoration check, the preset duration (for example, 200 to 300 microseconds) may be delayed, and the adaptive receiving parameter of the link receiving side is sent to the opposite end (the receiving side of the SerDes link having the communication relationship). Configured notifications;
  • step c the Lane_A and Lane_B links start to equalize the link, and the adaptive configuration parameters are obtained according to the method described in the foregoing step 3.
  • Lane_A and Lane_B links select and count the pre-emphasis configuration parameters on the transmitting side by using the FCE error correction flag on the receiving side as the criterion for determining whether the CRC error flag is generated.
  • This timing control mode ensures that the transmitting side is in effect first, and is slightly delayed, and then configures the receiving side parameters.
  • thousands of Serdes links are guaranteed, and the pre-emphasis parameters of the transmitting side and the adaptive parameters of the receiving side are sequentially implemented to enhance the stability of the backplane as a whole.
  • the advantages of the embodiments of the present invention are mainly as follows: starting from a high-rate data frame sent by the Serdes link, responding to burst errors of the link by coding and error correction on the link, and processing burst errors and erroneous data in time. Correction is performed to enhance the transmission efficiency of data frames.
  • the adaptive adjustment function of the receiving side Serdes the random convergence of the received data stream is achieved.
  • the converged code stream is a complete transmission message without bit disorder or modification, and the message in the link transmission is error-free. ERR, no signal interference or loss for the purpose of efficient and stable frame data reception. Further, this party
  • the method also ensures the accuracy and integrity of the data through the CRC check on the receiving side, and avoids frame loss caused by misjudgment during data processing and verification.
  • the embodiment of the present invention further provides a SerDes link parameter debugging device, where the device includes: a determining unit, a first training unit, and a second training unit; wherein
  • the determining unit is configured to determine a codec mode based on a link clock and a channel characteristic; determine a forward error correction method and a check code; and further configured to determine a pre-emphasis parameter range;
  • the first training unit is configured to perform training according to the pre-emphasis parameter range, the forward error correction method, and the check code to debug the transmitting side of the high-speed serial/parallel-to-serial converter, to obtain pre-emphasis configuration parameters;
  • the second training unit is configured to perform equalization parameter training on the receiving side of the high speed serial/parallel converter to be debugged after the first training unit determines the pre-emphasis configuration parameter, to obtain an adaptive configuration. parameter.
  • the codec mode includes at least one of the following codec modes: an 8B codec mode, a 10B codec mode, a 64B codec mode, and a 66B codec mode.
  • the first training unit is configured to set a selection range of pre-emphasis parameters, and select, according to the training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameters, as the Debugging a transmission side configuration parameter of the high speed serial/parallel converter; on the receiving side of the high speed serial/parallel converter to be debugged, restoring the verification according to the forward error correction method; A CRC error occurs, determining that the selected combination of pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the current training direction, and selecting a combination of another set of pre-emphasis parameters as the high speed to be debugged according to the new training direction.
  • a CRC error occurs; traversing all the pre-emphasis parameters in the pre-emphasis parameter range, and recording the pre-emphasis of the restoration check without CRC error
  • the combination of parameters is determined as a combination of available pre-emphasis parameters; traversing the SerDes link, obtaining a combination of pre-emphasis parameters available in the SerDes link, and finding a combination of pre-emphasis parameters available for a set of SerDes links as a pre-emphasis configuration parameter .
  • the second training unit is configured to select, at the first time, the combination of a set of pre-emphasis configuration parameters at the first training unit as the transmitting side of the high-speed serial/parallel converter to be debugged.
  • the preset duration is delayed before the restoration check of the high-speed serial/parallel converter to be debugged, and the preset duration is any one of 200 to 300 microseconds. .
  • the apparatus further includes: a sending unit, configured to send, to the SerDes link that has a communication relationship, a notification that the link sending side starts pre-emphasis configuration;
  • the first training unit is configured to select a combination of pre-emphasis configuration parameters as the pre-emphasis configuration parameter on the transmitting side of the link, and delay the preset duration;
  • the sending unit is further configured to send, to the receiving side of the SerDes link in which the communication relationship exists, a notification that the link receiving side starts adaptive parameter configuration;
  • the second training unit is configured to perform the equalization parameter training on the receiving side of the link after the first training unit determines the pre-emphasis configuration parameter, to obtain an adaptive configuration parameter.
  • the determining unit, the first training unit, and the second training unit may be implemented by a central processing unit (CPU), a microprocessor (MPU, a digital processor unit), and a digital signal in practical applications.
  • CPU central processing unit
  • MPU microprocessor
  • DSP Digital Signal Processor
  • FPGA Field Programmable Gate Array
  • SerDes link parameter debugging apparatus provided in the foregoing embodiment is only illustrated by the division of each of the foregoing program modules when performing link parameter debugging. In actual applications, the foregoing processing may be assigned differently according to requirements.
  • the program module is completed, that is, the internal structure of the SerDes link parameter debugging device is divided into different program modules to complete all the above descriptions. Or partial processing.
  • the SerDes link parameter debugging device and the SerDes link parameter debugging method are provided in the same embodiment, and the specific implementation process is described in detail in the method embodiment, and details are not described herein again.
  • An embodiment of the present invention further provides a SerDes link parameter debugging apparatus, including: a processor and a memory for storing a computer program capable of running on a processor, wherein when the processor is used to run the computer program, Execution: determining a codec mode based on a link clock and channel characteristics; determining a forward error correction method and a check code; determining a pre-emphasis parameter range, according to the pre-emphasis parameter range, the forward error correction method, and a check code Performing training on the transmitting side of the debug high speed serial/parallel converter to obtain pre-emphasis configuration parameters; after determining the pre-emphasis configuration parameters, balancing the receiving side of the high-speed serial/parallel converter to be debugged Parameter training, get adaptive configuration parameters.
  • a SerDes link parameter debugging apparatus including: a processor and a memory for storing a computer program capable of running on a processor, wherein when the processor is used to run
  • the processor when the processor is configured to run the computer program, performing: setting a selection range of pre-emphasis parameters, and selecting a combination of a set of pre-emphasis parameters from a selection range of the pre-emphasis parameters according to a training direction
  • a transmission side configuration parameter of the high speed serial/parallel converter to be debugged As a transmission side configuration parameter of the high speed serial/parallel converter to be debugged; on the receiving side of the high speed serial/parallel converter to be debugged, the verification is restored according to the forward error correction method;
  • a CRC error occurs during the restoration check process, and it is determined that the combination of the selected pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the current training direction, and selecting another combination of pre-emphasis parameters according to the new training direction.
  • the processor when used to run the computer program, perform: Each time a combination of a set of pre-emphasis configuration parameters is selected as the pre-emphasis configuration parameter of the transmitting side of the high-speed serial/parallel-to-serial converter to be debugged, on the receiving side of the high-speed serial/parallel converter to be debugged Before the restoration check is performed, the preset duration is delayed, and the preset duration is any one of 200 to 300 microseconds.
  • the processor when configured to run the computer program, perform: to a SerDes link having a communication relationship, in determining a pre-emphasis configuration parameter and an adaptive configuration parameter, to a SerDes having a communication relationship
  • the link sends a notification that the transmitting side of the link starts pre-emphasis configuration; after selecting a combination of a set of pre-emphasis configuration parameters as the pre-emphasis configuration parameter of the transmitting side of the link, delaying the preset duration to the SerDes chain having the communication relationship
  • the receiving side of the path sends a notification that the receiving side of the link starts to configure the adaptive parameter.
  • the receiving side of the link After determining the pre-emphasis configuration parameter, the receiving side of the link is trained on the equalization parameter to obtain an adaptive configuration parameter.
  • the processor when configured to run the computer program, if: after traversing all pre-emphasis parameters, a CRC error occurs on a receiving side of any one of the SerDes links, and the receiving side is balanced. After the parameter training, the restore verification process is marked as CRC error, indicating that the SerDes link is unavailable.
  • the memory may be implemented by any type of volatile or non-volatile storage device, or a combination thereof.
  • the non-volatile memory may be a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), or an Erasable Programmable Read (EPROM). Only Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, Magnetic Surface Memory , CD-ROM, or Compact Disc Read-Only Memory (CD-ROM); the magnetic surface memory can be a disk storage or a tape storage.
  • the volatile memory may be a random access memory (RAM), which is used as External cache.
  • RAM Random Access Memory
  • SRAM Static Random Access Memory
  • SSRAM Synchronous Static Random Access Memory
  • SSRAM Dynamic Random Access
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • DDRSDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • ESDRAM enhancement Enhanced Synchronous Dynamic Random Access Memory
  • SLDRAM Synchronous Dynamic Random Access Memory
  • DRRAM Direct Memory Bus Random Access Memory
  • the memory is used to store various types of data to support the operation of the SerDes link parameter debugging device. Examples of such data include any computer program for operation on a SerDes link parameter debug device.
  • the operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks.
  • the application can include various applications, such as a Media Player, a Browser, etc., for implementing various application services.
  • a program implementing the method of the embodiment of the present invention may be included in an application.
  • the processor in the SerDes link parameter debugging device may be an integrated circuit chip with signal processing capability.
  • each step of the above method may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the above described processor may be a general purpose processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like.
  • the processor may implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present invention.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiment of the present invention may be directly implemented as a hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a storage medium, the storage medium being located in the memory, the processor reading the information in the memory, and completing the steps of the foregoing methods in combination with the hardware thereof.
  • the SerDes link parameter debugging device may be configured by at least one Application Specific Integrated Circuit (ASIC), DSP, Programmable Logic Device (PLD), and Complex Programmable Logic Device (CPLD (Complex Programmable Logic Device), FPGA, general purpose processor, controller, MCU, microprocessor, or other electronic component implementation for performing the aforementioned method.
  • ASIC Application Specific Integrated Circuit
  • DSP Digital Signal processor
  • PLD Programmable Logic Device
  • CPLD Complex Programmable Logic Device
  • FPGA general purpose processor
  • controller controller
  • MCU microprocessor
  • An embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions for performing: determining a codec mode based on a link clock and a channel characteristic; a method for correcting errors and a check code; determining a range of pre-emphasis parameters, and training the transmitting side of the high-speed serial/parallel-to-serial converter according to the pre-emphasis parameter range, the forward error correction method, and the check code, Obtaining a pre-emphasis configuration parameter; after determining the pre-emphasis configuration parameter, performing equalization parameter training on the receiving side of the high-speed serial/parallel-to-serial converter to be debugged, to obtain an adaptive configuration parameter.
  • the computer executable instructions are configured to: set a selection range of pre-emphasis parameters, and select, according to a training direction, a combination of a set of pre-emphasis parameters from the selection range of the pre-emphasis parameters, as a transmission side configuration parameter of the high speed serial/parallel converter to be debugged; on the receiving side of the high speed serial/parallel converter to be debugged, the verification is restored according to the forward error correction method; if the verification process is restored A CRC error occurs, determining that the selected combination of pre-emphasis parameters is not available, backtracking to the training direction opposite or parallel to the current training direction, and selecting another combination of pre-emphasis parameters as the to-be-commissioned according to the new training direction.
  • a transmission side configuration parameter of the high speed serial/parallel converter on the receiving side of the high speed serial/parallel converter to be debugged, re-restoring the verification according to the forward error correction method; until the restoration verification process No CRC error occurred;
  • a combination of all pre-emphasis parameters in the pre-emphasis parameter range, a record of the pre-emphasis parameter that records the restoration check and no CRC error is determined as a combination of available pre-emphasis parameters; traversing the SerDes link to obtain pre-emphasis available in the SerDes link
  • the computer executable instructions are configured to: each time select a combination of a set of pre-emphasis configuration parameters as a pre-emphasis configuration parameter of a transmitting side of the high speed serial/parallel converter to be debugged, Before the restoration check of the high-speed serial/parallel converter to be debugged, the preset duration is delayed, and the preset duration is any one of 200 to 300 microseconds.
  • the computer executable instructions are configured to: in the process of determining a pre-emphasis configuration parameter and an adaptive configuration parameter for a SerDes link having a communication relationship, sending the present to a SerDes link having a communication relationship
  • the link sending side starts the pre-emphasis configuration notification; after selecting a combination of a set of pre-emphasis configuration parameters as the pre-emphasis configuration parameter of the transmitting side of the link, delaying the preset duration to the receiving side of the SerDes link having the communication relationship Sending a notification that the receiving side of the link starts adaptive parameter configuration; after determining the pre-emphasis configuration parameter, performing equalization parameter training on the receiving side of the link to obtain an adaptive configuration parameter.
  • the computer executable instructions are configured to: after traversing all the pre-emphasis parameters, a CRC error occurs on the receiving side of any one of the SerDes links, and the receiving side is trained by the equalization parameter.
  • the restore verification process marks the SerDes link as unavailable due to a CRC error.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the various components shown or discussed may be through some interface, device or unit.
  • the indirect coupling or communication connection can be electrical, mechanical or other form.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a removable storage device, a ROM, a RAM, a magnetic disk, or an optical disk, and the like, which can store program codes.
  • the above-described integrated unit of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a standalone product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a RAM, a magnetic disk, or an optical disk.
  • the technical solution of the embodiment of the present invention starts from a high-rate data frame sent by the Serdes link, and responds to a burst error of the link by coding and error correction on the link, and timely processes the burst error and corrects the error data. Enhance the transmission efficiency of data frames.
  • the adaptive adjustment function of the receiving side Serdes the random convergence of the received data stream is achieved.
  • the converged code stream is a complete transmission message without bit disorder or modification, and the message in the link transmission is error-free. ERR, no signal interference or loss for the purpose of efficient and stable frame data reception.
  • the method also ensures the accuracy and integrity of the data by the CRC check on the receiving side, and avoids frame loss caused by misjudgment during data processing and verification.

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Abstract

La présente invention porte sur un procédé et sur un dispositif de débogage de paramètre de liaison SerDes ainsi que sur un support de stockage informatique. Le procédé consiste : sur la base d'une horloge de liaison et d'une caractéristique de canal, à déterminer un mode de codec ; à déterminer un procédé de correction d'erreur sans voie de retour et un code de contrôle ; à déterminer une plage de paramètres de préaccentuation et, en fonction de la plage de paramètres de préaccentuation, du procédé de correction d'erreur sans voie de retour et du code de contrôle, à former un côté d'envoi d'un convertisseur série-parallèle/parallèle-série à grande vitesse à déboguer de sorte à obtenir un paramètre de configuration de préaccentuation ; et après la détermination du paramètre de configuration de préaccentuation, à effectuer un apprentissage de paramètre d'égalisation sur un côté de réception du convertisseur série-parallèle/parallèle-série à grande vitesse à déboguer de sorte à obtenir un paramètre de configuration auto-adaptatif.
PCT/CN2017/099278 2017-05-26 2017-08-28 Procédé et dispositif de débogage de paramètre de liaison serdes et support de stockage informatique WO2018214319A1 (fr)

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KR1020197038332A KR102230236B1 (ko) 2017-05-26 2017-08-28 SerDes 링크 파라미터 디버깅 방법, 장치 및 컴퓨터 기억매체
RU2019143884A RU2733809C9 (ru) 2017-05-26 2017-08-28 Способ и устройство для отладки параметра соединения serdes и компьютерный носитель данных

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CN201710386821.7A CN108933600B (zh) 2017-05-26 2017-05-26 一种SerDes链路参数自动调试方法
CN201710386821.7 2017-05-26

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RU2733809C9 (ru) 2020-12-07
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KR20200011488A (ko) 2020-02-03
CN108933600B (zh) 2020-11-06

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