JPH0766795A - Line quality monitoring device - Google Patents

Abstract

PURPOSE:To provide a line quality monitoring device for quickly calculating a BER by a compact system and monitoring the quality of a line by utilizing the BER calculated in the preceding process when a line state is stable in respect to a line quality monitoring device for a digital transmission line. CONSTITUTION:A subtractor 12 outputs variation width in the number of accumulated error pulses. A comparator 13 compares the variation width with the number (n) of data outputted from a number of data setter 14. A data memory 15 stores variation width in the number of accumulated error pulses capable of regarding a line state as a stable state and BERs corresponding to respective values of the variation width. When a compared result indicating that the variation width is less than the number (n) of data is obtained from the comparator 13, only a BER adder 16 is driven to add the output of the data memory 15 to the preceding BER outputted from a latch circuit 18 without calculating a BER by using a conversion expression.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line quality monitoring device, and more particularly to a line quality monitoring device for digital transmission lines.

Generally, in a digital transmission line, since the line quality may deteriorate due to fading or the like, the transmitting side does not transmit only the data to be transmitted, but an error detection code such as parity together with a predetermined number of data. And an error correction code are added and then modulated by a predetermined modulation method and transmitted. The receiving side receives and demodulates the transmitted data, detects whether there is a data transmission error based on an error detection code such as parity, and generates an error pulse when there is a transmission error. The line quality monitoring device monitors the line quality.

When the error correction code is transmitted, the erroneous data is corrected and restored. In addition, even if the parity is not transmitted, when the error correction code is transmitted, the erroneous data is detected using the error correction code and the data, and the error pulse is output. In such a digital transmission system, since the line quality is constantly monitored by the line quality monitor, it is important to reduce the throughput of the entire system.

[0004]

2. Description of the Related Art FIG. 3 shows a block diagram of an example of a conventional line quality monitoring apparatus. In the figure, the error pulse input to the terminal 1 is supplied to the counter 2 and measured. The counter 2 is reset every unit time by a signal of a constant cycle from the time base oscillator 3. Therefore, the counter 2 outputs the accumulated value of the error pulse at the above-mentioned constant period (every unit time).

This cumulative value is the number of parity errors per unit time (the number of times that there is an error as a result of parity check).
Is supplied to the BER calculator 4 and the BER is calculated for each unit time by using a conversion formula showing the relationship between the number of parity errors and the bit error rate (BER). The calculated BER value is input to and stored in the memory 5. As described above, in the conventional line quality monitoring device, the BER is calculated and calculated for each unit time to monitor the line quality.

[0006]

However, in the above-mentioned conventional line quality monitoring apparatus, the BER by the BER calculator 4 is used.
Since the calculation of (1) includes a floating point calculation, the calculation process requires a large amount of time, but is always calculated for each unit time. For this reason, the BER calculator 4 causes the central processing unit (C
When configured with PU), it requires a fast and expensive CPU to get the time for other required processing.

In order to suppress the BER calculation time, there is also a method of calculating the BER by referring to a data table showing the relationship between the number of parity errors and the BER. In this method, however, the memory for storing the data table is stored. A large capacity is required, and there are problems in downsizing and cost reduction of the system.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a line quality monitoring device that uses a previously calculated BER when the line state is stable to quickly calculate the BER and monitor the line quality in a small system.

[0009]

In order to achieve the above object, the present invention comprises: counting means for counting the cumulative number of error pulses in a unit time; first holding means for holding the cumulative number of error pulses; A subtracter that calculates the fluctuation width of the cumulative error pulse count by subtracting the cumulative error pulse count of the previous time and the cumulative error pulse count of this time counted by the counting means, and the fluctuation width and the predetermined data count. Comparison means for comparing, storage means for storing the bit error rate corresponding to the fluctuation width in advance by the number of data, second holding means for holding the calculated bit error rate, and fluctuation width by the comparison means When the number of data is larger than the number of data, the bit error rate is calculated from the cumulative number of error pulses from the counting means by a conversion formula.
And a calculating means for calculating the current bit error rate based on the previous bit error rate from the holding means and the bit error rate corresponding to the fluctuation range from the storing means.

[0010]

In the digital transmission line, the line quality may be deteriorated due to fading or the like, but the time during which the line state is stable is much longer than the time when the line quality is deteriorated. When the line condition is stable, the cumulative number of the error pulses in a unit time is almost constant, so the bit error rate is also almost constant.

Therefore, in the present invention, when the comparison means detects that the variation width of the cumulative number of error pulses is less than or equal to the data number, it is considered that the line state is stable and the bit error rate is calculated again by the conversion formula. Instead, the bit error rate is calculated by adding the bit error rate corresponding to the fluctuation range of the cumulative number of detected error pulses to the previously calculated bit error rate.

Further, the first and second holding means need only hold the previous number of accumulated error pulses and the previous bit error rate, and the number of data in the comparison means need only be the number at which the line quality can be considered stable. Further, the fluctuation range of the cumulative number of error pulses and the number of bit error rates stored in the storage means can be significantly reduced as compared with the conventional data table for calculating the bit error rate.

[0013]

1 is a block diagram of an embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted. In FIG. 1, the latch circuit 11 constitutes the first holding means, and by inputting the cumulative number of error pulses counted by the counter 2, the output signal of the time base oscillator 5 is input as a latch pulse. , Holds the cumulative number of error pulses per unit time. The subtractor 12 subtracts the current error pulse cumulative number N per unit time from the counter 2 and the previous error pulse cumulative number N ′ per unit time from the latch circuit 11 to obtain the error pulse cumulative number. The fluctuation range of is output.

The comparator 13 compares the fluctuation range of the cumulative number of error pulses from the subtracter 12 with the data number n from the data number setting unit 14 in magnitude. The data number setting unit 14 stores the bit error rate (BER) stored in the data memory 15.
The number n of data is set. The number of data n is also the number of fluctuations in the cumulative number of error pulses that is considered to be stable in the line state, and can be varied according to the size of the system. The comparator 13 and the data number setting device 14 constitute the comparison means.

The data memory 15 constitutes the storage means, and the number of fluctuation widths of the cumulative number of error pulses which is considered to be stable in the line state, and the line quality stabilization in advance corresponding to each value of the fluctuation width. The bit error rate (BER) calculated in the state is stored, the output fluctuation width of the subtractor 12 is input as an address, and the BER corresponding to the input fluctuation width is read in synchronization with the output signal of the time base oscillator 5. Be done.

The BER adder 16 adds the BER from the data memory 15 and the previous BER from the latch circuit 18 in synchronization with the output signal of the time base oscillator 5. The memory 17 stores the BER calculated by the BER calculator 4 using the conversion formula and the BER from the BER adder 16. The latch circuit 18 holds the BER held in the memory 18. The memory 17 and the latch circuit 18 constitute the second holding means.

Further, the BER calculator 4 and the BER adder 16
Means the arithmetic means, and when the comparison result indicating that the fluctuation range is larger than the number of data is input from the comparator 13, the BER adder 16 is prohibited from operating and the BER arithmetic unit is operated. 4 operates, on the other hand, when the comparison result indicating that the fluctuation width is less than the number of data is input from the comparator 13, the BER calculator 4 is prohibited from operating and B
Only the ER adder 16 is controlled to operate.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. The error pulse input to the terminal 1 of FIG. 1 is supplied to the counter 2 and counted. Here, assuming that the above-mentioned error pulse is a pulse generated when it is determined that there is an error in the result data of the parity check, the counter 2 collects the number of parity errors every unit time. (Step S1 in FIG. 2).

The number N of parity errors output from the counter 2 is input to the subtractor 12 while the latch circuit 1
Held by 1. The subtracter 12 subtracts the previously latched parity error number N ′ before the current parity error number is latched in the latch circuit 11 from the current parity error number N from the counter 2, and the subtraction result (N−N ') Is supplied to the comparator 13. The comparator 13 outputs the subtraction result (N-
N ') absolute value and the number of data n from the data number setter 14
And are compared in magnitude (step S2 in FIG. 2).

Assuming that the line is changing rapidly due to fading, the above comparison result is | N-
N ′ |> n, and the BER adder 1 according to the comparison result.
6 is prohibited from operating, and only the BER calculator 4 operates and B
The ER calculator 4 calculates the BER in the same manner as the conventional one from the current parity error number N and the conversion formula (step S3 in FIG. 2). The calculation result from the BER calculator 4 is stored in the memory 17 and held in the latch circuit 18 (step S6 in FIG. 2).

On the other hand, when the line is stable, the comparison result in step S2 of FIG. 2 becomes | NN ′ | ≦ n, which prohibits the operation of the BER calculator 4 and causes only the BER adder 16 to operate. Works. That is, first, the BER corresponding to the value of the subtraction result (NN ′) extracted from the subtracter 12 (corresponding to the fluctuation width of the number of parity errors) is the data memory 1
5 is read (step S4 in FIG. 2). The BER adder 16 adds the positive or negative BER read from the data memory 15 and the previously calculated BER from the latch circuit 18 to calculate the current BER (FIG. 2).
Step S5).

Since this BER adder 16 is a simple addition operation, the BER using the conversion formula by the BER calculator 4 is used.
It is possible to calculate much faster than the calculation operation.
This BER obtained by adding with the BER adder 16
Are stored in the memory 17 and held in the latch circuit 18 (step S6 in FIG. 2).

As described above, according to this embodiment, the number of parity errors is almost constant when the line condition is stable, and therefore the BER is not calculated again by the conversion formula, but is calculated last time. BER adder 16 using BER
Since the BER of this time is calculated by the addition operation of, the total time required for BER calculation can be suppressed and the throughput of the entire system can be reduced.

The present invention is not limited to the above-mentioned embodiment, but may be constructed by software logic using, for example, a microcomputer. Also,
The error pulse is not limited to the one obtained by the parity check, and it goes without saying that an error pulse indicating the presence of a data error generated at the time of error correction using an error correction code can also be used.

[0025]

As described above, according to the present invention,
When the line status is stable, the bit error rate is not calculated again using the conversion formula, and the bit error rate corresponding to the fluctuation range of the cumulative number of detected error pulses is added to the previously calculated bit error rate. Since the bit error rate is calculated by adding, the time during which the line status is stable is much longer than the time when the line quality deteriorates, so the total time required to calculate the bit error rate is shortened. You can
Therefore, since this time reduction can be used for other processing, the throughput of the entire system can be reduced,
Further, in the case of using a microcomputer, a slow and inexpensive one can be used.

Further, according to the present invention, since only the minimum number of bit error data corresponding to the fluctuation range of the cumulative number of error pulses per unit time in which the line state is stable is stored in advance, any error pulse is stored. Compared with the case of storing a data table in which the bit error rate is calculated in advance corresponding to the cumulative number, the memory capacity can be significantly reduced, so that the system can be configured at low cost and in a small size. .

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of one embodiment of the present invention.

FIG. 3 is a block diagram of a conventional example.

[Explanation of symbols]

 1 Error Pulse Input Terminal 2 Counter 4 Bit Error Rate (BER) Calculator 5 Time Base Oscillator 11, 18 Latch Circuit 12 Subtractor 13 Comparator 14 Data Number Setting Device 15 Data Memory 16 BER Adder 17 Memory

Claims (2)

[Claims] 1. A counting unit that counts the cumulative number of error pulses in each unit time for each unit time; a first holding unit that holds the cumulative number of the error pulses counted by the counting unit; A subtractor for subtracting the previous accumulated error pulse count held by the first holding means and the present accumulated error pulse count counted by the counting means to calculate a fluctuation range of the accumulated error pulse count; Comparing means for comparing the fluctuation width and a predetermined number of data in magnitude, storage means for preliminarily storing the bit error rate corresponding to the fluctuation width by the number of data, and a first means for holding the calculated bit error rate. 2 holding means, and when the fluctuation range by the comparing means is larger than the number of data, the bit error rate is calculated from the cumulative number of error pulses from the counting means by a conversion formula. If the fluctuation width is less than or equal to the number of data, the bit error rate of this time is calculated based on the previous bit error rate from the second holding means and the bit error rate corresponding to the fluctuation width from the storage means. And a calculating means for calculating 2. The error pulse accumulation counted by the counting unit only when the comparison unit inputs the comparison result indicating that the fluctuation range is larger than the data number from the comparison unit. Held by the second holding means only when an arithmetic unit for calculating a bit error rate from a number and a comparison result indicating that the fluctuation range is less than or equal to the number of data are input from the comparison means And a bit error rate read out according to the fluctuation range from the storage means to calculate a current bit error rate. The line quality monitoring device according to claim 1.