JP2568167B2 - Facsimile machine - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a facsimile apparatus capable of using a mini-fax mode.

[Prior art]

Facsimile machines are roughly classified into so-called international standard machines having specifications that conform to CCITT (International Telegraph and Telephone Consultative Committee) recommendations and mini-fax type machines of Nippon Telegraph and Telephone Public Corporation. However, since the main purpose of the mini-fax (MFI type) device is to transmit books and books, the standard manuscript was A5 size. Also, since the recording paper that is installed is also A5 size, in communication with the mini fax, only documents of A5 size or smaller can be sent and received in the standard mode or high quality mode,
There was a drawback.

(Object) The present invention has been made in view of the above points, and an object thereof is to provide a facsimile apparatus capable of communicating with a mini-fax type apparatus and recording in A4 size or A5 size with a simple and inexpensive configuration. In a facsimile machine that can use the mini-fax mode, the operator can change the recording paper width to A4 width,
Alternatively, when setting means for setting the A5 width is set and the frequency of the phase synchronization signal of the received image signal is 6 Hz when communicating in the mini-fax mode, the recording paper width set by the setting means is the A5 width. If so, in order to record the received image of A5 width in the fine mode, the data output from the modem is sampled at the first frequency, and if the recording paper width set by the setting means is A4 width, An object of the present invention is to provide a facsimile apparatus characterized by sampling data output from a modem at a second frequency higher than the first frequency in order to record a received image in a standard mode.

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. FIG. 1 shows a block diagram of an embodiment of the facsimile machine according to the invention.

In FIG. 1, reference numeral 2 denotes a telephone network used for data communication and the like, so that the terminal of the line is connected to control connection of the telephone switching network, switch to a data communication path, and loop. Network control unit NCU (Network Contr
ol Unit). The signal line 2a is a telephone line. Signal line 4
When the signal of 0a is the signal level "0 (zero)", the signal line 2a
Is connected to the signal line 2b. When the signal level of the signal line 40a is "1", the signal line 2a is connected to the signal line 2c.

Reference numeral 4 is a circuit for inputting the signal line 2b and generating a pulse on the signal line 4a when a facsimile call signal is detected. Specifically, it is when a 1300 Hz signal is detected for 2.2 seconds or longer.
If you want to make an incoming call automatically using the Facsimile communication network,
The fax machine is activated without ringing the telephone bell by the fax machine call signal (1300Hz).

6 inputs the signal line 2b, and a calling signal for telephone network (16H
z) is a circuit for generating a pulse on the signal line 6a.

Normally, when making an automatic incoming call, a signal of signal level "0" is output to the signal line 40a. The facsimile call signal detection circuit 4 and the telephone network call signal detection circuit 6 operate on standby power. When the facsimile call signal or telephone network call signal is detected, the main power supply is turned on to start an automatic incoming call. However, in this embodiment,
It doesn't focus on working with standby power. Therefore, consider the case where the main power supply is always on.

Reference numeral 8 is a hybrid circuit that separates a transmitted signal and a received signal. The transmission signal is transmitted from the signal line 34a to the signal line 2
It is sent to the telephone line 2a through c. Further, the received signal is output from the telephone line 2a through the signal line 2c to the signal line 8a.

10 inputs the signal of signal line 8a, 0.75 seconds or more 2100Hz
This circuit generates a pulse on the signal line 10a when the signal of is detected. This 2100Hz signal is the Group 2 command signal (GC2) used in the CCITT recommended G2 mode procedure.
Alternatively, it is the phase signal (PHS) or the phase signal (PHS) used in the procedure of the mini focus mode.

12 inputs the signal of the signal line 8a, and this signal level is −
A signal presence / absence detection circuit that outputs a signal with a signal level “1” to the signal line 12a when it is 43 dBm or more, and outputs a signal with a signal level “0” to the signal line 12a when the signal level is −48 dBm or less. is there.

Reference numeral 13 is an automatic gain adjustment circuit (hereinafter referred to as an AGC circuit) which receives a signal from the signal line 8a, amplifies it to a certain level, and outputs it to the signal line 13a. The facsimile signal output from the transmitter is attenuated by the telephone line which is a transmission medium while arriving at the receiver. The amount of attenuation varies every time the line is set, but once the line is connected, the amount of attenuation is constant until the communication ends and the line is disconnected. Therefore, in order to perform facsimile communication, the AGC circuit 1 is used every time a line connection is made, that is, every time communication is performed.
It is necessary to amplify the facsimile signal received by 3 to a certain level. The facsimile signal amplified by the AGC circuit 13 to a constant level is output to the signal line 13a. The signal level of the signal lines 40r, 40s, 40t is "1",
When it is "0" or "0", an operation called a key AGC is performed.
Also, the signal level of the signal lines 40r, 40s, 40t is "0",
When it is "1" or "0", an operation called peak AGC is performed. Also, the signal level of the signal lines 40r, 40s, 40t is "0",
When it is "0" or "1", an operation called hold AGC is performed.

Reference numeral 14 is an AM-PM-VSB demodulator, which is a known circuit.
The demodulator 14 extracts a carrier from the facsimile signal input from the output 13a of the AGC circuit 13, performs synchronous detection, and further performs full-wave rectification to obtain a binarized signal of the received baseband signal. Output to the signal line 14a.

Reference numeral 16 is a circuit for inputting the binarized signal of the signal line 14a and performing phase matching. When a 6 Hz phase signal is detected, signals of signal levels "1" and "0" are output to the signal lines 16a and 16b. When a 9 Hz phase signal is detected, signals of signal levels "0" and "1" are output to the signal lines 16a and 16b. When the signal level "1" is detected after the signal level "0" is continuously detected for 2 mS, a pulse is generated on the signal line 16c. The timing at which this pulse occurs is the end of the lost time of the phase signal. When a pulse is generated on the signal line 400, the signal lines 16a and 16b are cleared (set to "0") and the phase adjustment is performed again.

18 inputs the signal of the signal line 14a in accordance with the clock output to the signal line 22a, and when 8 bits are input, the signal line 18a
It is a serial / parallel conversion circuit that generates a pulse to and outputs byte data to the signal line 18b.

Reference numeral 20 is a reference clock generation circuit used to create a clock for sampling demodulated data and a reference clock (18 Hz [6 Hz for G2]) of a line period. The frequency of the reference clock is 1.24416MHz and the accuracy is ± 5p.
pm. The reference clock is output to the signal line 20a.

22 is a line cycle frequency of 18Hz (6H in G2 mode)
z) and a clock for sampling the binarized demodulated data (10.368 KHz when recording in A5 size standard mode / A4 size standard mode, 6.912 KHz when recording in A5 high quality mode [G2 mode recording 10.368 KHz when performing)))
Is a frequency dividing circuit created by dividing the 1.24416 MHz clock output to the signal line 20a. The output signal obtained by dividing the signal on the signal line 20a by the number output on the signal line 40b is output to 22a. Then, the output signal obtained by dividing the signal on the signal line 22a by the number output on the signal line 40c is output to 22b. 9Hz phase signal detected, ie A5
When recording in the size standard mode, the signal line 40b is 12
0, 576 is output to the signal line 40c. The signal line 22a has 1.
A 10.368 KHz signal obtained by dividing the 24416 MHz signal by 120 is output. The signal line 22b has a frequency of 10.368KHz and a frequency of 576 divided by 18H.
The z signal is output. When a 6 Hz phase signal is detected, it is determined whether the mode is the mini focus mode or the G2 mode, depending on the length of the phase signal. If it is determined to be the mini focus mode, check whether A5 size high quality mode recording or A4 size standard mode recording is selected (described later). And when recording in A5 size high quality mode is selected, 180 on the signal line 40b,
384 is output to the signal line 40c. 1.244 for signal line 22a
A 16.912 KHz signal obtained by dividing the 16 MHz signal by 180 is output. The signal line 22b has a frequency of 10.368KHz and a frequency of 384 divided by 18H.
The z signal is output. When recording in A4 size standard mode is selected, it is the same as when recording in A5 size standard mode. When it is determined to be in the G2 mode, 120 is output to the signal line 40b and 1728 is output to the signal line 40c. The signal line 22a has a frequency of 1.24416 MHz divided by 120 to 10.368 KH.
The z signal is output. A 6 Hz signal obtained by dividing the 10.368 KHz signal by 1728 is output to the signal line 22b.

The 24 can record in A5 size high quality mode and A4 size standard mode when the phase signal sent from the other side equipment is 6 Hz, that is, high quality mode, but the operator can This circuit detects which recording is selected (corresponding to the setting means of the present invention). When recording in the A5 size high quality mode is selected, a signal of signal level "0" is output to the signal line 24a. Also, when recording in the A4 size standard mode is selected, the signal level "1" appears on the signal line 24a.
Signal is output.

26 is a signal line 26a that indicates a reception ready signal (CFR) in the mini focus mode when a pulse is generated on the signal line 40d.
It is a circuit to send to.

Reference numeral 28 is a circuit for sending a reception preparation completion signal (CFR2) in the G2 mode to the signal line 28a when a pulse is generated on the signal line 40e.

30 is group 2 when a pulse is generated on the signal line 40f.
It is a circuit that sends an identification signal (GI2) to the signal line 30a.

Reference numeral 32 is a circuit for transmitting a called station identification signal (CED) to the signal line 32a when the signal line 40g generates a pulse.

Reference numeral 34 is an adder circuit that inputs signals from the signal lines 26a, 28a, 30a, and 32a and outputs the added result to the signal line 34a.

A double buffer memory 36 can store image data for two lines. Name the memory buffers buffer 0 and buffer 1. The data of buffer 0 is input from the signal line 40h and output to the signal line 36a. The data of the buffer 1 is input from the signal line 40i and output to the signal line 36b.

Reference numeral 38 denotes a recording unit, and when a pulse is generated in the signal line 40j, that is, when image signal data is stored in the double buffer 38, a signal of the signal line 40k (when the signal level of the signal line 40k is "0"). , Indicating that image signal data is stored in buffer 0, indicating that image signal data is stored in buffer 1 when the signal level of signal line 40k is “1”), and which buffer It is determined whether the image signal data is stored in. When the data is stored in buffer 0, the signal of the signal line 40l (when the signal level of the signal line 40l is "0", when the signal level of the signal line 40l is "1" instead of the all-white line) , Which represents an all-white line) is input to determine whether the line is an all-white line. If it is an all-white line, the recording paper is conveyed for one line. If it is not an all-white line, the signal on the signal line 36a is input and recording is performed. After that, the recording paper for one line is conveyed. In addition, when data is stored in buffer 1, the signal of the signal line 40m (when the signal level of the signal line 40m is “0”, when the signal level of the signal line 40m is “1”, not the all-white line) , Which represents an all-white line) is input to determine whether the line is an all-white line. If it is an all-white line, the recording paper is conveyed for one line. Signal line 36b if not all white line
Input the signal of and record. After that, the recording paper for one line is conveyed.

Reference numeral 42 is a timer circuit that generates a pulse on the signal line 42a 7 seconds after the pulse is generated on the signal line 40m.

Reference numeral 44 is a timer circuit that generates a pulse on the signal line 44a 30 seconds after the pulse is generated on the signal line 40p.

Reference numeral 46 is a circuit for detecting the presence or absence of recording paper. When there is recording paper, a signal of signal level "1" is output to the signal line 46a, and when there is no recording paper, a signal of signal level "0" is output to the signal line 46a.

Reference numeral 48 is a timer circuit that generates a pulse on the signal line 48a after a lapse of 3 seconds after the pulse is generated on the signal line 40q.

The control device 40 is composed of a microcomputer, a memory and the like, and controls each of the above-mentioned members by a program of main and interrupt.

The control procedure of the control device 40 in the above configuration is shown in FIG.
It is shown in FIG. 2 (A) to 2 (C) are a main routine for performing phase adjustment of the control device 40, FIG. 3 is a main routine for receiving an image signal, and FIG. 4 is an interrupt routine for performing phase adjustment. IPHSR is shown in Fig. 5 (A) ~
(D) is an interrupt routine IP for receiving image signals
It is a flow chart showing each IXR. Before explaining the flow chart, the outline of the operation of the control device 40 will be described.

In the main routine shown in FIGS. 2A to 2C, it is first determined whether the cause of the activation is the facsimile call signal or the telephone network call signal. First, the case of being activated by a facsimile call signal will be described. First, after transmitting the facsimile switching command signal (CED signal), the AGC is set to the peak AGC. Then, it goes to the reception of the signal of 2100 Hz which is the frequency of the phase signal. After detecting the 2100Hz signal, head for phase matching. 6Hz and 9Hz may be sent as the phase signal, but the modem status is set assuming that the 9Hz phase signal is coming. When the 9Hz phase signal is detected, hold the AGC.
To set. Then, the reception preparation completion signal is transmitted.
If the phase signal sent is 6Hz, check whether you want to record in A5 size high quality mode or A4 size standard mode, and set the modem status accordingly. To do. When the 6 Hz phase adjustment is completed, the AGC is set to the hold AGC and the reception preparation completion signal is transmitted. A5 in standard mode
By recording in size and changing the clock that samples the modem data in high quality mode, it is possible to easily record in A5 size in high quality mode or A4 size in standard mode.

In the present invention, the phase signal of A5 high-quality mode or A4 standard mode and scan line frequency not all white 6Hz, the phase signal of A5 standard mode and scan line frequency not all white 9Hz, scan line frequency 18Hz of all white line Although the least common multiple is used as a reference for the line period, the control device 40 uses the counter CT18Hz for scanning line frequencies of 6 Hz and 9 Hz (labels shown in capital letters below are software counters, pointers, routine names or flags. May be configured as hardware). As will be described in more detail later, when an interrupt of 18 Hz occurs in the interrupt, the value of CT18 Hz is checked, and when it is "0", it is determined as a line break. When the next line is all white (when it is judged as an all white line), CT18Hz is set to "0" to set the line to 1/18 second (18Hz).
To set. If the next line is not completely white (when it is determined that the line is not completely white) at the line break, set the line to 1/9 second (9Hz). Therefore, set “1” to CT18Hz. When the phase matching is completed and the frequency is 9Hz, set CT18Hz to "1" at the line break. At the line break, if the line is A5 high quality mode or A4 standard mode and the next line is not completely white (when it is determined that it is not an all white line), set that line for 1/6 seconds (6Hz ), Set "2" to CT18Hz. When the phase matching is completed and the frequency is 6 Hz, set CT18Hz to "2" at the line break.

If an 18Hz interrupt occurs, CT18Hz
Check the value of, and if it is not "0", reduce the value of CT18Hz by one. Here, even when the reception ready signal is being sent out, the interrupt is activated and the count of 18 Hz is performed.

On the other hand, when activated by the telephone network call signal,
First, the CED signal is transmitted. AGC set to peak AGC. Then, when considering a facsimile device having a function of communicating in the G2 mode, for example, a group 2 identification signal (GI2 signal) is transmitted. Then, it goes to the reception of the group 2 command signal (GC2 signal) or the 2100 Hz signal which is the phase signal in the mini-fax mode sent from the partner facsimile machine. When the 2100 Hz signal cannot be detected, the group 2 identification signal is transmitted at 3-second intervals until the 30-second time expires. Set the modem status assuming reception in G2 mode. When the frequency of the phase signal is 9 Hz, the reception is started in the mini focus mode. When the frequency of the phase signal is 6 Hz, after the phase matching is completed, the AGC is set to the hold AGC and the 7 second timer is started. If the signal is interrupted within 7 seconds, the reception preparation completion signal (CFR2) in the G2 mode is sent and the image reception in the G2 mode is started. If the signal is not broken within 7 seconds, proceed to reception in the mini focus mode. The time of 7 seconds is set because the phase signal in the G2 mode is 5 seconds to 7 seconds.

When the activation occurs due to the telephone network call signal, and the first phase signal (receiving the first image information) sent from the partner facsimile machine is 6 Hz, as described above. , It takes some time from the start of the reception of the phase signal to the start of the transmission of the reception preparation completion signal (in the mini focus mode). However, since it is recognized as the reception in the mini focus mode after the second time (when the second image information is received), the reception preparation completion signal is sent earlier than the first time after the reception of the phase signal is started. It became possible to do it.

In the main routine shown in FIG. 3, the start address when storing in the buffer is set to MOADR0 (start address of buffer 0) MOADR1 (start address of buffer 1). Then, the demodulator 14 sets "0" to the flag MOBAF indicating whether it is receiving to buffer 0 or buffer 1 and sets the start address MOADR0 of buffer 0 to MODPTR. Also, the counter MF used to detect the page end signal
"5" for EOM, counter M used to detect carrier loss
Set "18" to FEDCT. Then, after sending the reception preparation completion signal, the flag IF18Hz used to start receiving the image signal from the time when the line change point is detected is set to "0".
To set. Then, the destination address of the interrupt is set to IMFP.
Set to XR and start receiving image information. After that, whether the page end signal is detected or the carrier wave is detected,
Check if the recording paper is gone. During this period, the image information sent from the partner facsimile machine is received by an interrupt, and the recording unit 38 records the image information.
Then, when the page end signal is detected, the reception completion signal (MCF signal) is transmitted, and the reception of the 2100 Hz signal is started again. When a 2100 Hz signal is detected within 6 seconds, the next document is received. Further, when the interruption of the carrier wave is detected or when the recording paper is exhausted, the processing ends in error.

In the interrupt routine IPHSR shown in Fig. 4, when the 18Hz interrupt occurs, if the CT18Hz value is not "0", the DT18Hz value is decreased by 1 and the CT18Hz value is "0". If the flag PHSOK6, CT18Hz
Set the following values to. PHSOK6 is “0” (phase signal is
9Hz), set CT18Hz to "1" and PHSOK6
If is "1" (phase signal is 6Hz), set CT2 to "2" in CT18Hz.

Interrupt routine shown in FIGS. 5A to 5D
In IPIXR, switching between flag MOBAF and pointer MODPTR indicating which buffer is currently receiving data, checking whether the scan line currently being received is an all-white line, and control for the recording system (Control of which buffer data is recorded, control of whether or not it is an all-white line, control of notifying that buffer is pinched), CT18Hz control, detection of page end signal, disconnection of carrier wave Mainly performs detection and AGC control.
Here, the AGC control is reliably performed by changing the signal sent from the other side facsimile device depending on whether it is an image signal or a skip signal. In addition, all white lines, page end signals and carrier wave interruptions are detected by byte processing.

Next, each routine will be described in detail with reference to the drawings.

At step S60 in FIG. 2A, the flag PHSOK6 for storing the frequency of the phase signal sent from the partner facsimile machine is cleared (set to "0"). At 6Hz, PHSOK6 is set to "1", and at 9Hz, PHSOK6 is set to "0".

In step S62, when the phase signal is 6Hz, A5
Clear flag WRSZA4 to record in high quality mode or A4 standard mode (set to "0")
To do. When recording in A5 high quality mode, "0" is set in WRSZA4, and when recording in A4 standard mode, "1" is set in WRSZA4.

In step S64, the signal level of the signal line 40a is "0".
Is output, that is, the signal line 2a is connected to the signal line 2b.

In step S66, it is determined whether a pulse is generated on the signal line 4a, that is, whether the facsimile call signal is detected. When a pulse is generated in the signal line 4a, that is, when a facsimile call signal is detected, the process proceeds to step S70.
When no pulse is generated on the signal line 4a, that is, when the facsimile call signal is not detected, the process proceeds to step S68.

In step S68, it is determined whether a pulse has occurred on the signal line 6a, that is, whether a ringing signal for the telephone network has been detected. When a pulse is generated on the signal line 6a, that is, when a ringing signal for the telephone network is detected, the process proceeds to step S130. Signal line
If no pulse is generated at 6a, that is, if a ringing signal for the telephone network is not detected, the process proceeds to step S66.

In step 70, the signal level "1" is output to the signal line 40a, that is, the signal line 2a is connected to the signal line 2c.

In step S72, a pulse is generated on the signal line 40g,
That is, the CED signal is transmitted.

In step S74, a pulse is generated on the signal line 40p,
That is, a 30 second timer is started.

In step S76, it is determined whether a pulse has occurred on the signal line 10a, that is, whether a signal of 2100 Hz for 0.75 seconds or more has been detected. A pulse is generated on the signal line 10a, that is,
When a signal of 2100Hz for 0.75 seconds or more is detected, step S8
Go to 2. No pulse is generated on the signal line 10a, that is,
When the 2100 Hz signal of 0.75 seconds or more is not detected, the process proceeds to step S78.

In step S78, it is determined whether a pulse has occurred on the signal line 44a, that is, whether the 30-second timer has timed out. When a pulse is generated on the signal line 44a, that is, when the 30-second timer times out, the process proceeds to step S80. No pulse is generated on the signal line 44a,
That is, when the 30-second timer has not timed out, the process proceeds to step S76.

 Step S80 represents the off state.

In step S82, "0", "1" and "0" are output to the signal lines 40r, 40s and 40t, that is, the peak AGC.
To set.

In step S84, “120” is added to the signal lines 40b and 40c,
Outputs "576", that is, divides the clock so that recording is performed in A5 standard mode. 1.24416MH for signal line 22a
A 10.368KHz signal obtained by dividing the z signal by 120 is output.
An 18 Hz signal obtained by dividing the 10.368 KHz signal by 576 is output to the signal line 22b.

In step S86, "0" is set in the flag MOCKST indicating whether or not the modem clock is reset.
To set. It is set to "0" if the modem clock has not been reset, and to "1" if the modem clock has been reset.

In step S88, the interrupt destination is IPHSR.
To set.

In step S90, a pulse is generated on the signal line 40o,
That is, clear the signal lines 16a, 16b (set to "0")
To do. In step S92 of FIG. 2 (B), "FFH" is set in the counter CT18Hz used to divide 18Hz. Set "FFH" until phase matching is completed.

In step S94, it is determined whether the signal line 16a has the signal level "1", that is, whether the phase signal of 6 Hz is detected. The signal line 16a has a signal level "1", that is, 6
When the phase signal of Hz is detected (corresponding to "when the frequency of the phase synchronization signal is 6 Hz" of the present invention), step S106.
Proceed to. The signal line 16a has a signal level "0", that is, 6 Hz
When the phase signal of is not detected, the process proceeds to step S96.

In step S96, it is determined whether the signal line 16b has a signal level "1", that is, whether a 9 Hz phase signal has been detected. The signal line 16b has a signal level "1", that is, 9
When the Hz phase signal is detected, the process proceeds to step S102. When the signal line 16b does not detect the signal level "0", that is, the phase signal of 9 Hz, the process proceeds to step S98.

In step S98, it is determined whether a pulse has occurred on the signal line 44a, that is, whether the 30 second timer has timed out. When a pulse is generated on the signal line 44a, that is, when the 30-second timer times out, the process proceeds to step S100. When no pulse is generated on the signal line 44a, that is, when the 30-second timer has not timed out, the process proceeds to step S92.

 Step S100 represents an error condition.

In step S102, whether the flag MOCKST is "0",
That is, it is determined whether the modem clock has been reset. When the flag MOCKST is "0", that is, when the reset of the clock of the modem is not performed, the process proceeds to step S104. When the flag MOCKST is "1", that is, when the clock of the modem is reset, the process proceeds to step S100.

In step S104, the counter CT18Hz used to divide 18 Hz is set to "1".

In step S106, whether the flag MOCKST is "0",
That is, it is determined whether the modem clock has been reset. When the flag MOCKST is "0", that is, when the reset of the clock of the modem is not performed, the process proceeds to step S112. When the flag MOCKST is "1", that is, when the modem clock is reset, the process proceeds to step S108.

In step S108, since the 6 Hz phase signal is detected, "1" is set in the flag PHSOK6.

In step S110, the counter CT18Hz used to divide 18 Hz is set to "2".

In step S112, "1" is set in the flag MOCKST.

In step S114, it is determined whether the signal level of the signal line 24a is "0", that is, whether the recording in the A5 high quality mode is selected. When the signal level of the signal line 24a is "0", that is, when recording in the A5 high quality mode is selected (corresponding to "if the set recording paper width is A5 width" of the present invention), step S120 Proceed to. Signal line 24a
Is the signal level "1", that is, when recording in the A4 standard mode is selected (the "set recording paper width of the present invention is A4.
If width, "corresponds to step S116.

At step S116, since recording is performed in the A4 standard mode, "1" is set in the flag WRSZA4.

In step S118, “120” is added to the signal lines 40b and 40c,
"576" is output, that is, the clock is divided so that recording is performed in the A4 standard mode (corresponding to "sampling at the second frequency" of the present invention). The signal line 22a has 1.2
A signal of 10.368 KHz (corresponding to the "second frequency" of the present invention) obtained by dividing the 4416 MHz signal by 120 is output. Signal line 22
An 18 Hz signal obtained by dividing the 10.368 KHz signal by 576 is output to b.

In step S120, “180” is added to the signal lines 40b and 40c,
"384" is output, that is, the clock is divided so that recording is performed in the A5 high quality mode (corresponding to "sampling at the first frequency" of the present invention). The signal line 22a has 1.2
The signal of 4416 MHz is divided by 180 to 6.912 KHz (the “first of the present invention
Signal (corresponding to the “frequency”) is output. Signal line 22b
Outputs a 18 Hz signal obtained by dividing the 6.912 KHz signal by 384.

In step S122, a pulse is generated on the signal line 40,
That is, clear the signal lines 16a, 16b (set to "0")
To do.

In step S124, "0", "0", "1" are output to the signal lines 40r, 40s, 40t, that is, the hold AG.
Set to C.

In step S126, a pulse is generated on the signal line 40d, that is, a reception preparation completion signal in the mini focus mode is transmitted.

Step S128 represents proceeding to FIG. 2 (B).

In step S130 of FIG. 2C, the signal line 40a
Then, the signal level "1" is output, that is, the signal line 2a is connected to the signal line 2c.

In step S132, a pulse is generated on the signal line 40g, that is, a CED signal is transmitted.

In step S134, a pulse is generated on the signal line 40p, that is, a 30 second timer is started.

In step S136, a pulse is generated on the signal line 40f, that is, the GI2 signal is transmitted.

In step S138, a pulse is generated on the signal line 40q, that is, a 3-second timer is started.

In step S140, it is determined whether a pulse is generated on the signal line 10a, that is, whether a signal of 2100 Hz for 0.75 seconds or more is detected. A pulse is generated on the signal line 10a, that is,
When a signal of 2100Hz for 0.75 seconds or longer is detected, step S1
Proceed to 48. No pulse is generated on the signal line 10a, that is, when a 2100 Hz signal of 0.75 seconds or longer is not detected,
Proceed to step S142.

In step S142, it is determined whether a pulse has occurred on the signal line 48a, that is, whether the 3-second timer has timed out. When a pulse is generated on the signal line 48a, that is, when the 3-second timer times out, the process proceeds to step S144. When no pulse is generated on the signal line 48a, that is, when the 3-second timer has not timed out, the process proceeds to step S140.

In step S144, it is determined whether a pulse has occurred on the signal line 44a, that is, whether the 30-second timer has timed out. When a pulse is generated on the signal line 44a, that is, when the 30-second timer times out, the process proceeds to step S146. When no pulse is generated on the signal line 44a, that is, when the 30-second timer has not timed out, the process proceeds to step S136.

 Step S146 represents the off state.

In step S148, "0", "1", "0" are output to the signal lines 40r, 40s, 40t, that is, the peak AGC.
To set.

In step S150, “120” is added to the signal lines 40b and 40c,
Outputs "1728", that is, divides the clock so that recording is performed in G2 mode. 1.24416MHz on signal line 22a
The signal of 10.368KHz which is obtained by dividing the signal of 120 is output. A 6 Hz signal obtained by dividing the 10.368 KHz signal by 1728 is output to the signal line 22b.

In step S152, it is determined whether the signal line 16a has the signal level "1", that is, whether the phase signal of 6 Hz is detected. The signal line 16a has a signal level "1", that is, 6
When the Hz phase signal is detected, the process proceeds to step S160. When the signal line 16a does not detect the signal level "0", that is, the phase signal of 6 Hz, the process proceeds to step S154.

In step S154, it is determined whether the signal line 16b has a signal level "1", that is, whether a 9 Hz phase signal has been detected. The signal line 16b has a signal level "1", that is, 9
When the phase signal of Hz is detected, the process proceeds to step S84. When the signal line 16b does not detect the signal level "0", that is, the 9 Hz phase signal, the process proceeds to step S156.

In step S156, it is determined whether a pulse has occurred on the signal line 44a, that is, whether the 30-second timer has timed out. When a pulse is generated on the signal line 44a, that is, when the 30-second timer times out, the process proceeds to step S158. When no pulse is generated on the signal line 44a, that is, when the 30-second timer has not timed out, the process proceeds to step S152.

 Step S158 represents an error condition.

In step S160, "0", "0", "1" are output to the signal lines 40r, 40s, 40t, that is, hold AG.
Set to C.

In step S162, a pulse is generated on the signal line 40n, that is, a 7-second timer is started.

In step S164, it is determined whether a pulse has occurred on the signal line 42a, that is, whether the 7-second timer has timed out. When a pulse is generated on the signal line 42a, that is, when the 7-second timer times out, the process proceeds to step S84. No pulse is generated on the signal line 42a,
That is, when the 7-second timer has not timed out, the process proceeds to step S166.

In step S166, it is determined whether the signal level of the signal line 12a is "0", that is, whether the signal is disconnected. When the signal level of the signal line 12a is "0", that is, when the signal is disconnected, the process proceeds to step S168. When the signal level of the signal line 12a is "1", that is, when the signal is not broken, the process proceeds to step S164.

In step S168, a pulse is generated on the signal line 40e, that is, a reception preparation completion signal (CF
R2 signal).

Step S170 represents image reception in G2 mode.

In step S172 of FIG. 3, the head address when storing data in the buffer is set to MOADR0 and MOADR1. Set "8130H" to MOADR0 and "8230H" to MOADR1.

In step S173, buffer 0 and buffer 1 are cleared (set to "0").

In Step S174, whether PHSOK6 is "1",
That is, it is determined whether the phase signal is 6 Hz. PHS
When OK6 is "1", that is, when the phase signal is 6 Hz, the process proceeds to step S176. When PHSOK6 is "0", that is, when the phase signal is 9 Hz, the process proceeds to step S180.

In step S176, whether WRSZA4 is "1",
That is, it is determined whether the recording in the A4 standard mode is selected. When WRSZA4 is "1", that is, when recording in the A4 standard mode is selected, the process proceeds to step S178.
When WRSZA4 is "0", that is, when the recording in the A5 high quality mode is selected, the process proceeds to step S180.

In step S178, set MOADR0 to "810FH"
Set "820FH" to DR1.

In step S180, set MOBAF to "0" and MODPTR
Set MOADR0 to.

In step S182, "5" is set in the counter MFEOM used for detecting the page end signal. When the page end signal is detected for 6 consecutive lines, the page end signal is detected.

In step S184, "18" is set in the counter MFEDCT used for detecting the break of the carrier. When the carrier break is detected for 19 consecutive lines, the carrier break is detected.

In step S186, after the reception preparation completion signal is transmitted, "0" is set to the flag IF18Hz used to start the reception of the image signal from the time when the change point of the line is detected.

In step S188, the jump destination address of the interrupt is set.
Set to IMFPXR.

In step S190, it is determined whether the signal line 46a has the signal level "1", that is, whether there is a recording sheet. When the signal level of the signal line 46a is "1", that is, when there is a recording sheet, the process proceeds to step S192. When the signal level of the signal line 46a is "0", that is, when there is no recording sheet, the process proceeds to step S198.

In step S192, it is determined whether MFEOM is zero or more, that is, whether the page end signal is not detected.
If MFEOM is zero or more, that is, if the end-of-page signal is not detected, the process proceeds to step S196. When MFEOM is negative, that is, when the page end signal is detected, the process proceeds to step S194.

Step S194 represents a post procedure. Here, in the post-procedure, PHSOK6, WRSZA4 when receiving multiple sheets
After setting "0" to, proceed to step S70.

In step S196, it is determined whether MFEDCT is zero or more, that is, whether the carrier break has been detected. MFED
When CT is zero or more, that is, when the break of the carrier wave is not detected, the process proceeds to step S190. When MFEDCT is negative, that is, when the loss of the carrier wave is detected, the process proceeds to step S198.

 Step S198 represents an error condition.

In step S200 of FIG. 4, it is determined whether or not there is a signal on the signal line 22b, that is, whether or not an 18 Hz interrupt has occurred. If there is a signal on the signal line 22b, that is, if an 18Hz interrupt occurs, step S2
Go to 02. If there is no signal on the signal line 22b, that is, if 18 Hz interrupt is not generated, the process returns.

In step S202, it is determined whether the value of CT18Hz is "0", that is, whether the line has changed. CT
When the value of 18 Hz is "0", that is, when the line is changed, the process proceeds to step S206. The value of CT18Hz is not "0",
That is, when the line is not changed, step S2
Go to 04.

 At step S204, the CT18Hz value is decremented by one.

In step S206, it is determined whether PHSOK6 is "0", that is, whether the phase signal is 9Hz. When PHSOK6 is "0", that is, when the phase signal is 9 Hz, the process proceeds to step S208. PHSOK6 is “1”, that is, the phase signal is
If it is 6 Hz, proceed to step S210.

In step S208, CT18Hz is set to "1".

In step S210, "2" is set to CT18Hz.

In step S212 of FIG. 5A, the signal line 22b
Signal is detected, that is, whether or not an 18 Hz interrupt is occurring. If there is a signal on the signal line 22b, that is, if an 18 Hz interrupt occurs, the process proceeds to step S214. No signal on signal line 22b, ie 18H
If the z interrupt has not occurred, the process proceeds to step S272.

In step S214, it is determined whether the value of CT18Hz is "0", that is, whether the line has changed. CT
When the value of 18 Hz is "0", that is, when the line is changed, the process proceeds to step S218. The value of CT18Hz is not "0",
That is, when the line is not changed, step S2
Proceed to 16.

 At step S216, the CT18Hz value is decremented by one.

In step S218, "0", "0", "1" are output to the signal lines 40r, 40s, 40t, that is, hold AG.
Set to C.

In step S220, it is determined whether MFEOMC is "FFH", that is, whether the page end signal for one line is detected. For the detection of the page end signal, 6 lines in which signals from the end of the image signal to the end of the image signal are all "FFH" (that is, all white)
It is when the line continues. Counter 6 for these 6 lines
Counted by EOM. The memory called MFEOMC
It is used to check whether all the signals from the end of the image signal to immediately before the determination of the skip signal are "FFH". When MFEOMC is "FFH", that is, when the page end signal for one line is detected, step S2
Proceed to 24. When MFEOMC is not "FFH", that is, when the page end signal is not detected, the process proceeds to step S222.
Even in the area for judging the skip signal, when the received byte data is not "FFH", the same operation as in step S222 is performed.

In step S222, "5" is set in the counter MFEOM used for detecting the page end signal.

At step S224, the value of the counter MFEOM which uses the detection of the end-of-page signal is decremented by one.

In step S226, it is determined whether the counter MFCNT is less than 6, that is, whether the carrier loss for one line has been detected. When the carrier wave is cut off, it is usually recognized as an all-white line. That is, since one line is 1/18 second, when the carrier break is detected for 19 consecutive lines, the carrier break is detected. This 19-line counting is performed by the counter MFEDCT. If the carrier wave is cut off when it is not an all-white line, the received byte data is "FF" in the signal from the end of the image signal to immediately before the determination of the skip signal.
If it is less than 6 for "H", it means that the carrier wave for one line is broken. When the line is all white, the received byte data is "FF" in the area where the key AGC is working.
If the value is "H" less than 6, the carrier wave for one line is cut off. These 6 lines are counted by MFCNT. Counter MFCNT is less than 6, ie 1
When the interruption of the line carrier is detected, step S230
Proceed to. When the counter MFCNT is 6 or more, that is, when the interruption of the carrier wave is not detected, the process proceeds to step S228.

In step S228, "18" is set in the counter MFEDCT used for detecting the interruption of the carrier wave.

At step S230, the value of the counter MFEDCT used for detecting the interruption of the carrier wave is decremented by one.

In step S231, "0" is set in the counter WHFG used for checking whether or not the line is an all-white line. In the area to check whether it is a step signal,
When 2 bytes or more "00H" is detected, it is judged as a skip signal.

In step S232, set "FFH" to MFEOMC. The logical product is sequentially obtained from the signals from the end of the picture signal to immediately before the determination of the skip signal.

In step S234, "7" is set in the counter PAGCCT used to control the AGC when receiving the image signal which is not the all-white line. Activate the key AGC for 7 bytes from the end of the image signal. Otherwise hold A
It is a GC.

In step S236, the counter SAGCC used to control the AGC when receiving all white lines.
Set "40" to T. Activate the key AGC for 40 bytes from the point where it changed to the white signal of the skip signal. Other than that, it is a hold AGC.

In step S238, "4" is set in the counter SKPCKA used for checking whether the signal is a skip signal. If there are two or more bytes "00H" in the four bytes that check whether the signal is a skip signal, it is determined that the signal is a skip signal (that is, an all-white line).

In step S240, "128" is set in the counter PIXRCA used when receiving the image signal. When recording in A5 size, the effective recording width is 128 mm. Also,
In this embodiment, 1/8 (mm / dot) is considered as the density of main scanning lines. Therefore, PIXRCA is set to a value of 128 bytes.

In step S242, CT18Hz is set to "1".

In step S244 of FIG. 5B, it is determined whether PHSOK6 is "1", that is, whether the received phase signal is 6 Hz. When PHSOK6 is "1", that is, when the received phase signal is 6 Hz, the process proceeds to step S246. P
When HSOK6 is "0", that is, when the received phase signal is 9 Hz, the process proceeds to step S254.

In step S246, "2" is set in CT18Hz.

In step S248, whether WRSZA4 is "1",
That is, it is determined whether or not recording in A4 size is selected. When WRSZA4 is "1", that is, when recording in A4 size is selected, the process proceeds to step S250. When WRSZA4 is "0", that is, when recording in A5 size is selected, the process proceeds to step S254.

In step S250, "6" is set in the counter SKPCKA used for checking whether the signal is a skip signal. If 2 bytes or more "00H" is found in 6 bytes for checking whether the signal is a skip signal, it is determined to be a skip signal (that is, all white line).

In step S252, "192" is set in the counter PIXRCA used when receiving the image signal. When recording in A4 size, the effective recording width is 192 mm.

In step S254, it is determined whether the flag IF18Hz is "0", that is, whether the line change point is detected after the reception preparation completion signal is transmitted. When the flag IF18Hz is "1", that is, when the line change point is detected after the reception preparation completion signal is transmitted, the process proceeds to step S258. Flag IF
18Hz is "0", that is, after sending the reception ready signal,
When the change point of the line is not detected, the process proceeds to step S256.

In step S256, "1" is set in the flag IF18Hz.

In step S258, it is determined whether MOBAF is "0", that is, whether the data received up to now is buffer 0. If MOBAF is "0", that is, if the data received up to now is buffer 0, step
Proceed to S264. If MOBAF is "1", that is, if the data received up to now is buffer 1, step S2
Proceed to 60.

In step S260, MOBAF is set to "0" and MODPTR
Set MOADR0 to.

In step S262, "1" is output to the signal line 40k, that is, the data is stored in the buffer 1.

In step S264, MOBAF is set to "1", MODPTR
Set MOADR1 to.

In step S266, "0" is output to the signal line 40k, that is, the data is stored in the buffer 0.

In step S268, a pulse is generated on the signal line 40j, that is, data is stored in the buffer.

In step S270, "0" is output to the signal lines 40l and 40m, that is, information as to whether or not it is an all-white line is reset (that is, not all-white line).

In step S272 of FIG. 5 (C), the signal line 18a
It is determined whether a pulse is generated, that is, whether 8-bit data has been received. When a pulse is generated on the signal line 18a, that is, when 8-bit data is received, the process proceeds to step S274. No pulse is generated on the signal line 18a, that is,
When the 8-bit data is not received, the process returns.

In step S274, it is determined whether the flag IF18Hz is "0", that is, whether the line change point is detected after the reception preparation completion signal is transmitted. When the flag IF18Hz is "1", that is, when the line change point is detected after the reception preparation completion signal is transmitted, the process proceeds to step S276. flag
IF18Hz is "0", that is, when the line change point is not detected after the reception preparation completion signal is transmitted, the process returns.

At step S276, it is determined whether the counter SKPCKA is "0", that is, whether the counter signal is a skip signal or not. If the counter SKPCKA is "0", that is, if it is not a region for checking whether it is a skip signal, the process proceeds to step S300. Counter SKPC
If KA is not "0", that is, if it is a region for checking whether it is a skip signal, the process proceeds to step S278.

In step S278, the value of the counter SKPCKA is decremented by 1.

In step S280, the signal on the signal line 18b, that is, the received 8-bit data is input.

In step S282, it is determined whether the input 8-bit data is "00H". When the input 8-bit data is "00H", the flow proceeds to step S288. If the input 8 bit data is not "00H", step S
Proceed to 284.

In step S284, it is determined whether the input 8-bit data is "FFH". When the input 8-bit data is "FFH", the process returns. Entered 8
If the bit data is not "FFH", the flow proceeds to step S288.

In step S286, "5" is set in the counter MFEOM used for detecting the page end signal.

In step S288, "5" is set in the counter MFEOM used for detecting the page end signal.

In step S290, it is determined whether the counter WHFG is "2", that is, whether the skip signal is detected. When the counter WHFG is "2", that is, when the skip signal is detected, the process proceeds to step S294. When the counter WHFG is not "2", that is, when the skip signal is not detected, the process proceeds to step S292.

In step S292, the value of the counter WHFG is incremented by 1.

In step S294, whether MOBAF is "0",
That is, it is determined whether the data to be received from now on will be stored in buffer 0. MOBAF is "0",
That is, if the data to be received is stored in buffer 0, the process proceeds to step S298. MOBA
If F is "1", that is, if the data to be received is stored in buffer 1, step S296
Proceed to.

In step S296, "1" is output to the signal line 40m, that is, the data stored in the buffer 1 is all white.

In step S298, "1" is output to the signal line 40l, that is, the data stored in the buffer 0 is all white.

In step S300 of FIG. 5 (D), the counter WH
It is determined whether FG is "2", that is, whether the skip signal is detected. The counter WHFG is "2", that is,
When the skip signal is detected, the process proceeds to step S302. When the counter WHFG is not "2", that is, when the skip signal is not detected, the process proceeds to step S316.

In step S302, the signal on the signal line 18b, that is, the received 8-bit data is input.

At step S304, the value of the counter SAGCCT is decremented by one.

In step S306, it is determined whether the counter SAGCCT is equal to or greater than zero, that is, whether the area is where the key AGC operates. Counter SAGCCT is zero or more, that is, key
If it is in the area where the AGC operates, go to step S310.
If the counter SAGCCT is negative, that is, in the area where the hold AGC is activated, the process proceeds to step S308.

In step S308, "0", "0", "1" is output to the signal lines 40r, 40s, 40t, that is, the hold AG.
Set to C.

In step S310, it is determined whether the input 8-bit data is "FFH". When the input 8-bit data is "FFH", the process proceeds to step S312. If the input 8-bit data is not "FFH", step S31
Go to 4.

In step S312, the value of the counter MFCNT is incremented by 1.

In step S314, "1", "0" and "0" are output to the signal lines 40r, 40s and 40t, that is, the key AGC is set.

In step S316, it is determined whether the counter PIXRCA is "0", that is, whether or not the area is the area for recording the received data. If the counter PIXRCA is "0", that is, if the received data is not recorded, the process proceeds to step S324. When the counter PIXRCA is not "0", that is, when it is the area for recording the received data, the process proceeds to step S318.

At step S318, the value of the counter PIXRCA is decremented by one.

In step S320, the 8-bit data output to the signal line 18b is input and the data is stored in the address of MODPTR.

In step S322, the value of MODPTR is incremented by 1.

At step S324, the value of the counter PAGCCT is decremented by one.

In step S326, it is determined whether the counter PAGCCT is equal to or greater than zero, that is, whether the key AGC is operated. Counter PAGCCT is zero or more, that is, key
If it is in the area where AGC works, proceed to step S330.
If the counter PAGCCT is negative, that is, in the region where the hold AGC is activated, the process proceeds to step S328.

In step S328, "0", "0", "1" are output to the signal lines 40r, 40s, 40t, that is, hold AG.
Set to C.

In step S330, "1", "0" and "0" are output to the signal lines 40r, 40s and 40t, that is, the key AGC is set.

In step S332, the signal on the signal line 18b, that is, the received 8-bit data is input.

In step S334, it is determined whether the input 8-bit data is "FFH". If the input 8-bit data is "FFH", the flow proceeds to step S336. If the input 8-bit data is not "FFH", the flow proceeds to step S338.

In step S336, the value of the counter MFCNT is incremented by one.

In step S338, the value of MFEOMC and the input 8
The result of the logical product of the bit data is stored in MFEOMC.

In the present embodiment, the case of having the G2 function was considered as the case of using the telephone network for communication, but the same applies to the case of having other modes (G1 and G3). .

〔effect〕

As described above, according to the present invention, in the facsimile machine capable of using the mini-fax mode, the setting means for setting the recording paper width to be used to the A4 width or the A5 width is provided by the operator's operation, and the mini-fax is provided. When communicating in the mode, when the frequency of the phase synchronization signal of the received image signal is 6 Hz and the recording paper width set by the setting means is A5 width, the received image of A5 width is recorded in the fine mode. Therefore, the data output from the modem is sampled at the first frequency, and if the recording paper width set by the setting means is A4 width, it is output from the modem to record the A4 width received image in the standard mode. Data to be first
Since the sampling is performed at the second frequency higher than the frequency, the received image of A4 width can be recorded on the recording paper of A4 width even in the mini-fax mode.

[Brief description of drawings]

FIG. 1 is a block diagram of a facsimile apparatus adopting the present invention, and FIGS. 2 (A) to (C), FIG. 3, FIG. 4 and FIGS. 5 (A) to (D) are respectively in FIG. It is a flowchart figure explaining the processing procedure of the control apparatus of FIG. 2 …… NCU, 4 …… 1300Hz detection circuit 6 …… 16Hz detection circuit, 8 …… Hybrid circuit 10,2100Hz detection circuit, 12 …… Signal presence / absence detection circuit 13 …… AGC circuit, 14 …… Demodulator 16 …… PHS detection circuit, 18 …… S / P conversion circuit 20 …… Reference clock generation circuit, 22 …… dividing circuit 24 …… A4 / A5 selection detection circuit 26 …… CFR signal sending circuit, 28 …… CFR2 signal sending circuit 30 …… GI2 signal sending circuit, 32 …… CED signal sending circuit 34 …… Adding circuit, 36 …… Double buffer memory 38 …… Recording unit, 40 …… Control device 42 …… Timer circuit (7 seconds) 44 …… Timer circuit (30 seconds) 46 …… Recording paper presence / absence detection circuit, 48 …… Timer circuit (3
Seconds)

Claims (1)

(57) [Claims] 1. A facsimile apparatus capable of using the mini-fax mode, wherein a setting means for setting a recording paper width to be used to A4 width or A5 width by an operator's operation is provided, and when communicating in the mini-fax mode, When the frequency of the phase synchronization signal of the received image signal is 6 Hz and the recording paper width set by the setting means is A5 width, it is output from the modem in order to record the received image of A5 width in the fine mode. If the recording paper width set by the setting means is A4 width, the data output from the modem is recorded at the first frequency in order to record the received image of A4 width in the standard mode. A facsimile machine characterized by sampling at a higher second frequency.