JP2749821B2 - Facsimile machine - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a facsimile apparatus, for example, a facsimile apparatus having an error correction mode.

[Conventional technology]

In a conventional facsimile apparatus, when communication is performed in the normal G3 mode, if training reception of a high-speed signal (image signal) fails, subsequent communication is disabled. In addition, training reception of a high-speed signal (image signal) was successful, and data disorder occurred during data reception.
If a signal cannot be received, it is impossible to escape from receiving a high-speed signal. Then, in the decoding and decoding circuit, Q (MPS or EOM or EO)
The retransmission of P) was completed three times, and subsequent communication became impossible.

[Problems to be solved by the invention]

As described above, if the retraining error or the RTC of the high-speed signal is broken due to noise or the like, the subsequent communication becomes impossible.

[Means and actions for solving the problems]

According to the present invention, in a facsimile apparatus for communicating a predetermined amount of data at a high transmission rate, communicating a control signal at a low transmission rate, and switching between the high-speed data communication and the low-speed control signal communication, Data receiving means for receiving data at a high transmission rate, control signal receiving means for receiving a control signal at the low transmission rate, and when the high-speed transmission signal is detected for a first continuous time, Data reception by the data receiving means, the control means for receiving the control signal, the time corresponding to the predetermined amount of data transmission, if the high-speed transmission signal is not detected continuously for the first time, Even if retraining of a high-speed signal (image signal) fails, a low-speed control signal following the high-speed signal can be received, and the data transmission speed changes due to line quality or the like. It can reliably receive control signals.

Further, when the control means shifts to data reception by the data reception means, if the carrier of the signal of the high transmission rate is not detected continuously for the second time, the communication of the control signal is changed to the communication of the control signal. It is determined that a signal indicating the switch to the switch has been received, and the process shifts to the reception of the control signal. Even if the switch signal cannot be accurately received due to the influence of noise or the like, data communication can be continued. .

Further, when the control means shifts to data reception by the data receiving means, if valid data is not received within a third time, error processing is executed and communication is terminated.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

 First, an outline of the present embodiment will be described.

FIG. 3 shows an example of a communication sequence in which no error occurs in receiving the HDLC-formatted high-speed signal according to the present embodiment. FIG. 4 is a diagram showing the structure of image signal data.

In FIG. 3, noise and the like are mixed while the receiver is receiving 100 high-speed image signals, and a return signal to the control signal (FIG. 4)
When RCP) cannot be received, it has not been possible to escape from receiving high-speed signals. According to the present embodiment, it is possible to detect a carrier break for more than one second at least in the retransmission section of the low-speed signal, so that it is possible to proceed to the reception of the low-speed signal and the second reception of the PPS-NULL (101) is possible. Became.
Then, subsequent communication becomes possible.

In FIG. 3, when the transmitter cannot receive the MCF of 104, the transmitter retransmits PPS-NULL. Therefore, after transmitting the MCF 104, the receiver needs to simultaneously receive the high-speed signal and the low-speed signal. According to this embodiment, switching between a low-speed signal and a high-speed signal is possible.

First, the process proceeds to the reception of the high-speed image signal. When the high-speed flag is continuously detected for the predetermined time within the predetermined time, the process shifts to the reception of the high-speed signal. Further, when the high-speed flag cannot be detected continuously for a predetermined time within a predetermined time toward the reception of a high-speed image signal, a margin (flag transmission time, control signal reception time, control signal reception time) is required for the time required to transmit one block at the current transmission speed. The command is received for a time obtained by adding a time (eg, 6 seconds).

Then, the following control is performed when the operation shifts to the reception of the high-speed signal.

When the RCP is detected or the carrier break of a continuous high-speed signal for one second or longer is detected, the current transmission speed is set to a margin (a flag transmission time control signal reception time (for example, 6 hours) required to transmit one block. The command is received for the time added with seconds).

Also, no valid frame can be detected within one frame plus the predetermined time (margin) added to the time required to transmit one block at the current transmission speed. Alternatively, if a valid frame cannot be detected for a predetermined time (for example, 60 seconds) after detecting a valid frame, error processing is performed and the line is opened.

If no interrupt that data has been received continuously for 255 S or more is received, it is determined that an error has occurred, the line is released, and the processing ends with an error.

 Hereinafter, this embodiment will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the facsimile apparatus of this embodiment.

In FIG. 1, reference numeral 2 denotes a network for controlling connection of a telephone exchange network by connecting to a terminal of the line to use a telephone network for data communication and the like, switching to a data communication path, and holding a loop. Controller NCU (Network Cantrol Unit)
It is. The signal line 2a is a telephone line. NCU2 is signal line 40a
If the signal level is "0", the telephone line is connected to the telephone, that is, the telephone line 2a is connected to the signal line 2b. Also, the signal on the signal line 40a is input, and if this signal level is "1", the telephone line is connected to the facsimile apparatus side, that is, the telephone line 2a is connected to the signal line 2c. In a normal state, the telephone line is connected to the telephone.

 4 is a telephone.

Reference numeral 6 denotes a hybrid circuit for separating a signal of a transmission system and a signal of a reception system. That is, the transmission signal on the signal line 20a is transmitted to the telephone line via the NCU 2 via the signal line 2c. Further, the signal sent from the other side passes through the NCU 2, passes through the signal line 2c, and is output to the signal line 6a.

Reference numeral 8 denotes a reading circuit, which sequentially reads image signals for one line in the main scanning direction from a transmission original to create a signal sequence representing binary values of white and black. It is composed of an image sensor such as a CCD (charge coupled device) and an optical system. The binary signal sequence of white and black is output to the signal line 8a.

10 inputs the read data output to the signal line 8a,
This circuit outputs encoded (MH (Modified Huffman) encoded or MR (Modified Read) encoded) data to the signal line 10a.

Reference numeral 12 denotes a memory circuit that stores data output to the signal line 10a. Since this facsimile apparatus transmits a plurality of frames as one block at a time and then retransmits an erroneous frame, it is necessary to have a memory for at least one block. When the frame number to be transmitted is output to the signal line 40c, the memory circuit 12 outputs the information of the frame to the signal line 12a.

Reference numeral 14 denotes an address field, a control field, and an FCF before the encoded data output to the signal line 12a.
This is a circuit for adding a field and an FIF field (in which the frame number being transmitted is stored) and adding the information to the HDLC format and outputting the information to the signal line 14a. HDL
The C framing circuit 14 sends a flag for flow control on the transmitter side to the signal line 14a when the signal of the signal level "1" is output to the signal line 40d.

Reference numeral 16 denotes a modulator that performs modulation based on the known CCITT recommendation V27ter (differential phase modulation) or V29 (quadrature modulation). The modulator 16 receives the signal on the signal line 14a and performs modulation,
The modulation data is output to the signal line 16a.

Reference numeral 18 denotes a modulator that performs modulation based on the known CCITT recommendation V21. The modulator 18 receives the procedural signal on the signal line 40b, modulates the signal, and outputs modulated data to the signal line 18a.

Reference numeral 20 inputs the signals of the signal lines 16a and 18a, and outputs the sum to the signal line 20a.

Reference numeral 22 denotes a demodulator that performs demodulation based on the known CCITT recommendation V21. The demodulator 22 receives the signal on the signal line 6a, performs V21 demodulation, and outputs demodulated data to the signal line 22a.

A demodulator 24 performs demodulation based on the known CCITT recommendation V27ter (differential phase modulation) or V29 (quadrature modulation). The demodulator 24 receives the signal on the signal line 6a, performs demodulation, and outputs demodulated data to the signal line 24a.

Reference numeral 26 denotes a circuit which receives a signal of the signal line 6a and determines whether or not a carrier of high speed data of CCITT Recommendation V27ter or V29 is detected. 26 is when CCITT recommendation V27ter or V29 high speed data carrier is detected,
A signal having a signal level "1" is output to the signal line 26a, and a signal having a signal level "0" is output to the signal line 26a when the carrier of the high speed data of CCITT Recommendation V27ter or V29 is not detected.

Reference numeral 28 denotes a circuit which receives the demodulated data output to the signal line 24a and determines whether or not a flag pattern is detected. 28 outputs a signal of signal level "1" to the signal line 28a when the flag pattern is detected, and outputs a signal of signal level "0" to the signal line 28a when the flag pattern is not detected. It has a 2-byte memory space. At first, a signal of signal level "0" is output to the signal line 28a. When the recently received 8-bit data becomes a flag pattern (7EH), the signal line 28a Is "1". Once the signal level of the signal line 28a becomes "1", the subsequent 8 bits are not checked, and the latter 8 bits are not checked.
When the bit becomes the (7EH) pattern, it is checked whether the recently received 8-bit data is a flag pattern. If it is a flag pattern, the signal level of the signal line 28a is kept at "1".
The signal level of a becomes “0”. If the recently received 8-bit data is a flag pattern, the above check is repeated. If the recently received 8-bit data is not the flag pattern, only the recently received 8-bit is focused on, and this 8-bit becomes the flag pattern. At times, the signal level of the signal line 28a becomes "1".

An HDL 30 receives the demodulated data output to the signal line 24a, performs zero-deletion of the HDLC-converted data, and outputs the data before HDLC formatting to the signal line 30a.
This is a C deframing circuit.

Reference numeral 32 denotes a temporary memory circuit that temporarily stores encoded image information output to the signal line 30a in frame units. Data received correctly in frame units is a signal line.
Output to 32a.

Reference numeral 34 denotes an image memory circuit for storing the frame data output to the signal line 32a in a corresponding image memory space. A memory space for storing data of at least one block is required. The data up to the frame where no error has occurred is sequentially output to the signal line 30a. When a clear pulse is generated on the signal line 40e, the signal line 34b
Are all set to zero. The bit map of the received frame number is output to the signal line 34b.

A circuit 36 receives the demodulated data output to the signal line 34a and outputs the decoded (MH (Modified Huffman) or MR (Modified Read) decoded) data to the signal line 36a.

Reference numeral 38 denotes a recording circuit which receives a signal output to the signal line 36a and sequentially performs recording for each line.

A control circuit 40 mainly performs the control described in the first section of the embodiment. The control circuit 40 is constituted by peripheral devices of the micro computer such as a micro computer and a ROM storing a control program and a RAM for temporarily storing data.

FIG. 2 is a flowchart showing a control operation of the control circuit 40 of FIG.

2A is a main routine, and FIG. 2B is an interrupt routine at the time of receiving an image signal.

First, the main routine of FIG. 2A will be described.

In step S52, the signal level "0" is applied to the signal line 40a.
Is output, the CML is turned off, and the telephone line 2a is connected to the telephone.

Then, in step S54, it is determined whether facsimile reception has been selected. When facsimile reception is selected, the process proceeds from step S54 to step S58, and when facsimile reception is not selected, the process proceeds from step S54 to step S56 to perform other processing.

In step S58, the signal level "1" is set on the signal line 40a.
Is output, the CML is turned on, and the telephone line 2a is connected to the facsimile side.

Next, in steps S60, S62, S64 and S70, the pre-procedure of the CCITT recommended facsimile communication procedure is executed.

In step S62, it is determined whether or not ECM communication (error correction mode) is selected. If ECM communication is selected, the process proceeds to step S70, and if ECM communication is not selected, the process proceeds to step S64.

In steps S64 and S70, the remaining pre-procedures are executed.
In step S62, it is determined that the communication is not ECM communication, and in step S64, when the remaining pre-procedures are completed, the normal G3 communication is performed in step S66.
The image signal is received in the mode. When the reception of the image signal is completed, a post-procedure of the facsimile communication procedure is executed in step S68, and the process returns to step S52.

On the other hand, in step S62, ECM communication is determined, and in step S70
When the remaining pre-procedure is completed and the process proceeds to step S72, in step S72, a time for receiving high-speed data before detecting a valid frame different depending on each transmission speed, or a time when a procedure signal of 300 b / s is received. Set the timer value in R.SEDECMO to be used as the timer value. Here, when the transmission speed is 2400b / s, R.SEDEC
Set 250 seconds for MO. Thereafter, similarly, the transmission speed becomes 4
R.SEDECM at 800b / s, 7200b / s, 9600b / s
Set 150 seconds, 120 seconds, and 100 seconds in O. The reason for this time will be explained. If the number of bytes in one frame is assumed to be 256 bytes of data, and 1 byte of flag field, 1 byte of address field, 1 byte of control field, 1 byte of FCD field, 1 byte of FCD field, 1 byte of frame number field and 2 bytes of FCS are added. 263
It becomes bytes. When only the NULL block is transmitted without a flag, it is obtained from 263 × 8 × 256 / (transmission speed), and 2
244 seconds, 112 in the order of 400b / s, 4800b / s, 7200b / s, 9600b / s
Seconds, 75 seconds, 56 seconds. In addition, the flag sending time 30
The above value is determined by adding the time for receiving 0b / s and the like.

In step S74, after the reception of the high-speed signal, when a valid frame is detected, a timer R.SEDEMN which sets an error when no valid frame is detected thereafter is set to 60 seconds, and the flow advances to step S76.

In step S76, a high-speed signal receiving state is set.

Then, in step S78, when it is time to receive a high-speed signal, it is determined whether the high-speed flag has been continuously detected for a predetermined time within a predetermined time A, but the predetermined time A is set to timer0 according to each transmission speed. . The predetermined time B is set to Timer1 according to each transmission speed in step S80.

 The reason for setting the predetermined times A and B will be described.

First, as for the predetermined time B, the time of five consecutive flags is as follows at each transmission speed.

Training time 2400b / s 1158ms 4800b / s 923ms 7200b / s 253ms 9600b / s 253ms Time for 5 flags ・ Maximum delay time due to international line 1.25 ・ Assuming 0.55 as the time from the completion of the reception of the signal of 300b / s to the start of high-speed signal transmission.

・ Probability that 5 flag patterns occur by chance ・ After receiving the training signal,
The time is set to check whether five flags have been detected consecutively.

2400b / s 1.16 + 1.2 + 0.5 + 1.0 = 3.86 (S) 4800b / s 0.92 + 1.2 + 0.5 + 1.0 = 3.62 (S) 7200b / s 0.25 + 1.2 + 0.5 + 1.0 = 2.95 (S) 9600b / s 0.25 + 1.2 + 0.5 + 1.0 = 2.95 (S) The probability that five flags are generated consecutively in one second is the maximum. (The number of bits is the largest at 9600 b / s), so it is extremely small that five consecutive flags are accidentally detected. For this reason, it is determined whether or not a high-speed image signal has been received by determining whether or not five flags have been continuously detected in one second after the training signal has been received. Therefore, the predetermined time B is a time corresponding to five flags at each transmission speed.

In addition, the predetermined time A is the training time of the high-speed signal, the maximum delay time on the international line, and one second added to the time from the completion of the reception of the 300 b / s (for example, CFR.MCF) by the other party to the start of transmission of the high-speed signal. Think time.

In steps S82, S84, S86, S88 and S90, it is determined whether or not a high-speed signal flag has been detected for a predetermined time B continuously within a predetermined time A when the high-speed signal is received. If the flag of the high-speed signal is detected continuously, the process shifts to the reception of the high-speed signal (step S92). If the flag of the high-speed signal cannot be detected, the time required to transmit one block at the current transmission speed is obtained. Time (R.
(Time stored in SEDECMO) is set in Timer2, and the flow shifts to command reception.

On the other hand, when it is determined in step S84 that the timer 1 has timed out (the predetermined time B has elapsed), and the process proceeds to step S92, the high value at the time of reception in the temporary buffer is set in step S92. Here, the address is composed of 20 bits. The address has two 16-bit addresses, and a value obtained by shifting the high-side address to the left by 4 bits to the low-side address is added to be a 20-bit value. The temporary buffer includes a temporary buffer 0 and a temporary buffer 1, each having a memory space of 512 bytes.

Next, in step S94, 0000H is set to the low-side pointer R.FRMPTR for reception in the temporary buffer.

In step S96, a flag TEMPBFFU indicating whether temporary buffers 0 and 1 are empty or data is packed.
Set L to 00H. When B0 of TEMPBRRUL is 0, temporary buffer 0 is empty, and when B0 is 1, temporary buffer 0 is full. When B1 of TEMPBFFUL is 0, temporary buffer 1 is empty, and when B1 is 1, temporary buffer 1 is full.

In step S98, 0 is set to a flag TEMPBFI indicating which temporary buffer is to store data next. When TEMPBFI is 0, data is stored in temporary buffer 0 next, and when TEMPBFI is 1, data is stored in temporary buffer 1 next.

In step S100, the interrupt of the receiving modem is enabled.

In step S102, 0 is set to a flag TEMPBFO indicating which temporary buffer data is to be transferred to the image memory section. When TEMPBFO is 0, when the temporary buffer 0 becomes full next, the data of the temporary buffer 0 is transferred to the image memory space. TEMP
When BFO is 1, when the temporary buffer 1 becomes full next time, the data of the temporary buffer 1 is transferred to the image memory space.

In step S104, 1 second is set to a timer Timer0 for checking the carrier interruption of the high-speed signal.

In step S106, if it is determined that a valid frame cannot be detected for a predetermined time or more, the line is released and an error is terminated, but this time is checked by the timer Timer1 and R.SEDE.
Set the value of CMO.

When the various types of steps S92 to S106 are completed, the process proceeds to step S108, and in step S108, TEMPBF
It is determined whether O is 0 or not. When TEMPBFFO is 0, B0 of TEMPBFFUL is 1 in step S110 (that is,
(Temporary buffer 0 is full). If B0 of TEMPBFFUL is 1 at step S110 (that is, temporary buffer 0 is full), the contents of temporary buffer 0 are transferred to the corresponding image memory space at step S112 (step S112), and step S1 is performed.
After setting TEMPBFFO to 1 in step 14, set TEMPBFFO in step S116.
Set 0 to B0 of BFFUL. If B0 of TEMPBFFUL is not 1 in step S110, the process proceeds to step S126.

If TEMPBFO is 1 in step S108, step S
At 118, it is determined whether B1 of TEMPBFFUL is 1 (that is, whether or not temporary buffer 1 is full). If B1 of TEMPBFFUL is 1 at step S118 (that is, temporary buffer 1 is full), the contents of temporary buffer 1 are transferred to the corresponding image memory space at step S120, and TEMPBFO is set to 0 at step S122. After setting
At step S124, 0 is set to B1 of TEMPBFFUL.

Next, in step S126, it is determined whether the carrier of the high-speed signal is detected (ie, whether the signal level of the signal line 26a is "1"). When the carrier is detected in the high-speed signal also in step S126 (that is, when the signal level of the signal line 26a is "1"), the timer 0 is determined in step S128.
Set 1 second to

In step S130, it is determined whether at least one PCP signal has been detected. Detect at least one RCP signal. That is, when RCPDTFG is 1, step S13
Proceed to 8. Also, the RCP signal has not been detected. That is, RCPD
When TFG is 0, the process proceeds to step S132.

In step S132, TIMER0 is 0, that is, 1
It is determined whether or not a high-speed signal carrier break has been detected continuously for at least two seconds. When TIMER0 is 0, that is, when the carrier break of the high-speed signal is detected continuously for 1 second or more, the process proceeds to step S138.
If TIMER0 is not 0, that is, if the carrier break of the high-speed signal is not detected continuously for 1 second or more, the process proceeds to step S134.

In step S134, it is determined whether TIMER1 is 0, that is, whether a valid frame has been detected for a predetermined time or more. If TIMER1 is 0, that is, if no valid frame has been detected for a predetermined time or more, error processing is performed in step S136. If TIMER1 is not 0, that is, if a valid frame is detected within a predetermined time, the process proceeds to step S108.

In step S138, it is determined whether or not the received HDLC frame data has an error. If there is an error, a retransmission request signal (specifically, a PPR signal) is transmitted in step S140. If there is no error, step S142
Proceed to.

In step S142, it is determined whether or not the recording has been completed. It is determined whether the recording is completed. If the recording has not been completed, flow control (control for temporarily stopping transmission of the image signal to the transmitting side) is performed in step S148, and the recording operation is performed. When the recording is completed, it is determined in step S144 whether the next information is present. When there is the next information in step S144, the process proceeds to step S146, and when there is no next information, the process proceeds to step S52.

In step S146, it is determined whether or not there is a mode change. If there is a mode change, the process proceeds to step S60. If there is no mode change, the process proceeds to step S72.

FIG. 2B is a flowchart showing the interrupt processing of the modem at the time of receiving the image signal.

Hereinafter, the information of DLS and STS is the status information of Data Link Processor. And FEND is a flag pattern (01
11 Set to 1 when 1110B) is detected.

The CRC checks the FCS when FEND = 1, and determines whether or not correct frame data has been received. A value of 0 indicates that correct frame data has been received, and a value of 1 indicates that correct frame data has not been received.

The ABT is set to 1 when seven or more ABTs are detected continuously.

OVR is full of buffers. This is set to 1 when the main does not input the data received one time before even though the next byte data is ready.

First, in step S152, information on DLP and STS is input. Then, in step S154, it is determined whether or not OBF (output buffer full) is 1. If OBF is 0, dummy data is input in step S156, and the process returns in step S158. When OBF is 1, step S16
If 0, it is determined whether any of FEND, CPC, ABT, or OVR is 1. If it is 1, the process proceeds to step S162. If it is not 1, the process proceeds to step S174.

When the process proceeds from step S160 to step S162, it is determined whether or not either ABT or CRC is 1, and if it is 1, the process proceeds to step S166. If it is not 1, the process proceeds to step S166.
Proceed to S164.

In step S164, it is determined whether FEND is 1 or not.
If it is 1, the process proceeds to step S202 (this is the case where one frame of data has been correctly received). Also, 0
If so, the process proceeds to step S166.

In step S166, the fact that a frame error has occurred is added to F.LNKSTS. Then, R.FRMPTR is set to 0 in step S168, 1-byte data is input in step S170, and the process returns in step S17.

On the other hand, when the process proceeds from step S160 to step S174, 1-byte data is sequentially input after step S174.

In step S174, 1-byte data is input. Then, in step S176, the value of R.SADRRCM is set to BX, and in step S178, the value of R.FRMPTR is set to DI.

Next, in step S180, it is determined whether or not DI, that is, the received data of one frame has become 260 or more. D
I, that is, it is abnormal that the received data of one frame becomes 260 or more. Therefore, an error indicating that the frame is too long is written in F.LNKSTS in step S182, and R.FRMPTR is written in step S184.
Is set to 0, and the process returns in step S186.
If the DI in step S180, that is, the received data of one frame is less than 260, the process proceeds to step S188.

In step S188, it is determined whether DI is 0 or not. If it is 0, the CRC, ABT, OVR of F.LNKSTS is determined in step S190.
Is set to 0, DATA.5 is set to 1 in step S192, and the flow advances to step S194.

In step S194, the input data of 1 byte is stored in the temporary memory space, and the value of DI is incremented by one in step S196, and the value is incremented in step S198.
Set to R.FRMPTR and return at step S200.

In step S202, the value of R.SADRECM is set in SI.

In step S204, the contents of the address SI + 2, that is,
Check the contents of the FCF. It is determined whether or not the content of the FCF is RCP (86H). If it is RCP, 1 is set to the flag RCPDTFG indicating that RCP was detected in step S206, and 1 byte data is input in step S208, and then in step S210. To return.

If it is determined in step S204 that the content of the FCF is not RCP (86H) and the process proceeds to step S212, it is determined in step S212 whether the content of the SI address is 0FFH (that is, whether the address information is correctly received). In step S214, it is determined whether the content of the address SI + 1 is 03H (that is, whether the control information is correctly received).
In step S216, it is determined whether the content of address SI + 2 is 06H (that is, whether the FCD is correctly received). If the address, control, and FCD have been correctly received, the process proceeds to step S218, and if not, the process proceeds to step S166.

When the process proceeds from step S216 to step S218, the process proceeds to step S218.
In S218 and S220, the value of R.SEDECMN is set to TIMERI.

Then, in step S222, a flag TEMPBFI indicating which temporary buffer the data is to be input to.
Check. When TEMPBFI is 0 (that is, data has been input to the temporary buffer 0 until now), the process proceeds to step S232, and R.SADRECM is set in steps S232 and S234.
Set TBFISFSTA, 1 in B0 of TEMPBFFUL in step S236
Is set, and 1 is set in TEMPBFI in step S238. Then, R.FRMPTR is set to 0 in step S240, 1-byte data is input in step S242, and the process returns in step S244.

If TEMPBFI is 1 in step S222, that is, if data has been input to the temporary buffer 1, the process proceeds to step S224, and R.SADRE is set in steps S224 and S226.
Set TBF0SFSTA to CM and set TEPBFFUL B in step S228.
1 is set to 1 and TEMPBFI is set to 0 in step S230.

[Embodiment 2] In the above embodiment, after shifting to the reception of the high-speed signal, when the high-speed data is being received, the RCP or the carrier disconnection of the high-speed signal of 1 second or longer is detected, and the current transmission speed is used. TIMER2 is set to the time obtained by adding a margin to the time required to transmit one block, and the command is received.

However, for example, the last received frame number is checked, this value is subtracted from 255, the maximum number of frames to be received is determined, and the time required to transmit the number of frames at the current transmission speed has a margin. The command may be received at the time when the command is added.

[Embodiment 3] When the reception of the high-speed signal is completed once and there is an error frame in the received one frame, the reception of the high-speed signal is performed after transmitting the retransmission request signal (specifically, the PPR signal). Move to. At this time, the value of R.SEDECMO is transmitted at each transmission speed by the number of frames that can be retransmitted (determined by subtracting the number of frames that can be received correctly from the number of frames specified by PPS-Q). A time obtained by adding a margin to the time required for the setting may be set. When there are no error frames and a signal such as MCF is transmitted, R.SED
ECMO will, of course, reset.

Embodiment 4 In the above embodiment, when determining the time of R. SEDECMO, 256 bytes were considered as the number of bytes of data of one frame. However, the number of bytes of other data,
For example, when 64 bytes are selected, the value of R.SEDECMO may be changed.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a facsimile apparatus that can continue communication even if a retraining error occurs or a specific signal cannot be received during data reception.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of the facsimile apparatus of this embodiment, FIGS. 2A and 2B are flowcharts showing the control operation of the control circuit 40, and FIG. 3 is a communication sequence. FIG. 4 is a diagram showing the format of image signal data. 2 is an NCU, 4 is a telephone, 6 is a hybrid circuit, 8 is a reading circuit, 10 is an encoding circuit, 12 is a memory circuit, 14 is an HDLC framing circuit, 16 is a V27ter or V29 modulator, 1
8 is V21 modulator, 20 is addition circuit, 22 is V21 demodulator, 24 is V27
ter or V29 demodulator, 26 is a high-speed carrier detection circuit,
28 is a flag pattern detection circuit, 30 is an HDLC deframing circuit, 32 is a temporary memory circuit, 34 is an image memory circuit, 36 is a decoding circuit, 38 is a recording circuit, and 40 is a control circuit.

Claims (3)

(57) [Claims] 1. A facsimile apparatus for communicating a predetermined amount of data at a high transmission rate, communicating control signals at a low transmission rate, and switching between the high-speed data communication and the low-speed control signal communication. Data receiving means for receiving data at a transmission rate of: control signal receiving means for receiving a control signal at the low transmission rate; when the high-speed transmission signal is detected continuously for a first time, the data A control unit for receiving data by the receiving unit and receiving the control signal for a time corresponding to the predetermined amount of data transmission when the high-speed transmission signal is not detected continuously for the first time. Facsimile machine characterized. 2. When the control means shifts to data reception by the data receiving means, if the carrier of the signal of the high transmission rate is not detected continuously for a second time, the control means performs the control from the data communication. 2. The facsimile apparatus according to claim 1, wherein it is determined that a signal indicating a switch to signal communication has been received, and the process shifts to receiving the control signal. 3. When the control means shifts to data reception by the data receiving means, if valid data is not received within a third time, the control means executes error processing and terminates communication. The facsimile apparatus according to claim 1, wherein