JPH0618427B2 - Image communication device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image communication apparatus that divides image information into a plurality of line information and transmits the line information.

More specifically, the present invention relates to an image communication device such as a facsimile device configured to efficiently perform retransmission correction of image information.

[Prior art]

When data is transmitted through a communication line such as telephone reselection, data is erroneous at a certain rate due to the effects of instantaneous disconnection, noise, distortion, etc. of the communication line. In order to detect this data error, the received data is subjected to a predetermined calculation or the like to determine whether or not a certain rule is maintained. And if an error is detected,
According to a predetermined transmission control procedure, a method of retransmitting an information data group including error data is adopted.

Such automatic repeat request method (ARQ: automatic repeat reque
st) is a method used when performing half-duplex transmission using a telephone line, etc., and is a high-level data link control procedure.
(HDLC: high level data link control procedure). This HDLC is a bit transparent that enables highly efficient data transmission between data terminal equipment (DTE) via a data transmission line and can transmit an arbitrary bit string without depending on any coding system. It is a synchronous transmission control procedure. In the HDLC procedure, information of an arbitrary bit string and link control information are transmitted by a frame which is a transfer unit. The start and end of the frame are indicated by the flag sequence (01111110).

FIG. 1 shows the frame format of the HDLC procedure. The illustrated flag sequence is a signal for frame synchronization, and the frame is synchronized by transmitting and receiving one or more flag sequences. Also, when the same bit string as the flag sequence appears in the information transferred in the frame, the receiving side regards it as the end of the frame. To prevent this, when a pattern of five consecutive bits "1" appears in the information of the frame, the transmitting side forcibly inserts one bit "0" immediately after that, and the receiving side Then, the transparency of data to be transferred is guaranteed by using a method (zero bit insertion method) of removing one bit "0" received following a pattern of five consecutive bits "1".

The address field indicates the address assigned to the station that transmits and receives the frame by a binary code (for example, 11111111). The frame having the address of the station on the receiving side is the command frame, and the frame having the address of the station on the transmitting side is the response frame.

The control field indicates an operation command to the partner station when the frame is a command, and a response to the command frame command when the frame is a response.

Frame checking sequence (FCS)
ence) is a 16-bit sequence for frame transmission error detection, and indicates the calculation result by the generator polynomial X ¹⁶ + X ¹² + X ⁵ +1. The calculation target is from the beginning of the address field of the frame to the end of the information field.

The length of the information field is arbitrary (eg 512 bytes or 512 x 8 bits).

FIG. 2 shows a specific example when error retransmission is performed using the HDLC frame data shown in FIG. That is, when the receiving side receives a certain frame, an ACK signal is sent if no error has occurred, and a NACK signal is sent if an error has occurred.

On the other hand, on the transmission side, in response to the ACK signal detected during the transmission of the frame N, the frame N + 1 is transmitted after the frame N is transmitted.

On the other hand, if the NACK signal is detected during the transmission of a certain frame N, or if the ACK signal cannot be detected, the frame N is transmitted and then the frame N-1 is retransmitted.
Then, for the same frame, when the NACK signal is detected a predetermined number of times or more, or when the ACK signal is not detected at all, control for performing fallback is performed.

As described above, when the framed data is transmitted from the transmitting side and is received by the receiving side, the receiving side does not generate an error for the frame N as shown in FIG. 2, and an error occurs when receiving the frame N + 1. When it occurs, the following control is performed. That is, the receiving side sends the ACK signal after receiving the frame N,
The NACK signal is transmitted after receiving +1.

On the other hand, on the transmission side, the AC
Since the K signal is received, the frame N + 2 is transmitted after the frame N + 1 is transmitted. Further, on the transmitting side, the NACK signal is received during the transmission of the frame N + 2, so that the frame N + 2 is transmitted again after the transmission of the frame N + 2.
Send +1.

The receiving side sends the NACK signal for the frame N + 1 and then sends the ACK signal after receiving the frame N + 2 regardless of whether an error occurs in the frame N + 2. Thus, the receiving side is in the waiting state for receiving the frame N + 1. Then, when no error occurs in the retransmission frame N + 1 transmitted subsequent to the frame N + 2, the receiving side transmits the ACK signal after receiving the retransmission frame N + 1.

On the other hand, since the transmitting side receives the ACK signal while transmitting the retransmission frame N + 1, the transmission frame N + 2 is transmitted again after transmitting the retransmission frame N + 1. And
In response to the ACK signal received during the transmission of the frame N + 2, the frame N + 3 is transmitted after the frame N + 2 is transmitted.

Since the image communication apparatus using the conventionally known retransmission correction method ARQ adopts the HDLC frame structure as described above, there are mainly the following problems.

i) Effect on line error Since the signal to be transmitted is divided into blocks using the HDLC frame, a) on the receiving side, b) whether any error occurred in the block,
Alternatively, (b) it can be determined whether an error of 1 bit or more has occurred. Therefore, on the receiving side,
It is possible to reproduce a good image with no error even for 1 bit.

However, when a reception error occurs with respect to a certain block, it cannot be determined how much the error was. That is, on the receiving side, whether the block simply has no error or the block has an error (that is, the 1st bit to the xth bit (x depends on the block size and image information)). Can not be specified)) was the only alternative decision.

Therefore, it is effective to block the signal by HDLC frame under the condition that the line condition is good such as Japan (that is, when the line condition is good, the receiver side reproduces an image with no error of 1 bit). But you can)
When the line condition is poor, there is a high probability that some bits included in the HDLC frame will cause a reception error. For this reason, there is a drawback that the number of retransmissions increases.

ii) Regarding the influence of the bit position where the error occurs Since the signal to be transmitted is divided into blocks using the HDLC frame, it is necessary to retransmit from the beginning of the block even if the error occurs at any bit position of the block. is there. For example, as shown in FIG. 3, even when an error occurs in the data in the portion indicated by (A), it is necessary to perform retransmission from the beginning of the block, that is, the data at (A). Therefore, there is a drawback that the transmission efficiency cannot be improved.

iii) Regarding the influence based on the propagation delay characteristic of the communication line The transmitting side determines whether or not the frame N-1 transmitted earlier during the transmission period of a certain frame N is correctly received by the receiving side. However, even in this case, a situation may occur in which the ACK signal cannot be received due to the delay time inherent in the line. A specific example will be described with reference to FIG. Now, assuming that the time required for transmitting one block of data is Tf and the delay time generated when transmitting a signal from the transmitting side to the receiving side is Td, it is necessary that Tf> 2Td.
As described above, there is a drawback in that the allowable delay time on the line is defined according to the block size. Therefore, in order to allow a long delay time on the line, a method of increasing the block size can be considered.
However, if the block size is increased,
i) About the influence of the bit position where the error has occurred ”, the disadvantage described in the above section appears remarkably.

〔Purpose〕

An object of the present invention is to read a document image, a memory unit for storing the image data read by the reading unit, a transmitting unit for transmitting the image data stored in the memory unit, and the transmitted unit. Receiving means for receiving an error resending request signal for the image data, detecting means for detecting the end of the page of the image data stored in the memory means, and reading the image data instructed by the error resending signal from the memory means. The control means for causing the transmitting means to transmit the untransmitted image data that has not been transmitted by the transmitting means to a predetermined amount or less and the end of page is not detected by the detecting means. If the transmission of image data is prohibited and the end of page is detected by the detecting means even if the amount of untransmitted image data is less than the predetermined amount, Is to provide an image communication apparatus and performs transmission of the untransmitted image data.

〔Example〕

A facsimile machine will be described as an example, and will be described.

First, the outline of this embodiment will be described.

(i) At the time of transmitting the image information (transmitting side), the encoded line number is attached to each line and transmitted together with the image information. Then, the subsequent data can be retransmitted from the code corresponding to a certain line number.

On the receiver side, the line number is checked during the reception of the image information, and thereby the presence or absence of a reception error is determined. Then, when the data is correctly received, the line number is removed and the decoding is performed. On the other hand, when the reception side recognizes the occurrence of a reception error, the reception side device sends a control signal to interrupt the transmission of image information by the transmission side device.
After that, the receiving side device informs the transmitting side device of the retransmission request start line number. As a result, the transmitting device is
Transmission from the retransmission request start line number is restarted.

(ii) When transmitting image information, the line number inserted for each line has the following characteristics.

B) The line number is incremented for each certain line (1 to n (n is a positive integer)).

When the receiving side device receives the image data of one line, the line number is checked, and when the line number is the same as the previous one or is incremented by one, the received image is good. to decide. That is, the line number is set to 1 in the transmitting device.
When the line number is incremented for each line, the receiving side apparatus determines that the received image is not good when a reception error occurs even for one line, and requests retransmission. As a result, the received image information can be obtained without any error in one line.

On the other hand, in the case where the transmitter side is configured to increment the line number by one every two lines, the received image is judged to be good even if a reception error occurs for one line. It Therefore, it is possible to arbitrarily change the error determination of the received image in the receiving side device depending on how the line number is incremented.

(B) The line number is a signal indicating the end of the code of one line, for example, "EOL" (End of Line; used when modified Huffman coding or modified read coding is performed based on CCITT Recommendation T4). Insert later. As a result, the receiving side device can identify the image information and the line number.

C) The length of the line number is constant. Therefore,
The code numbers of the line numbers representing a small number and the line numbers representing a large number are the same. As a result, the receiving side device can recognize that the predetermined byte of the signal indicating the end of the code of one line is the line number. In this way, the image information and the line number can be easily identified on the receiving side.

D) A line number is a signal with a special meaning, for example,
This signal has a code configuration different from that of the signal indicating the end of one line. Therefore, when an error occurs on the receiving side, it is possible to search for a signal having a special meaning (indicating the end of one line) again and establish line synchronization in response to the detection of the signal.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.

FIG. 5 is a bit configuration diagram showing a specific example of the line number. This line number is EOL (line terminator)
Is inserted after.

In this embodiment, the modified Huffman code is changed as the coding method.

The line number is 2 bytes (16 bits) following the line end code EOL. The high byte LSB (Least Significant Bit) of the line number and the low byte LSB of the line number are fixed to 1 so that the line number can be distinguished from the EOL signal. The number of bits per line is 1728 when decoded by the receiving device
If it was not a bit (when receiving A4 size),
Performs EOL search and establishes line synchronization. Therefore, the line number needs to be a signal different from EOL.

For example, line number 0 is 01H (high byte of line number) 01H (low byte of line number), line number 1 is 01H (high byte of line number) 03H
(Low byte of line number), line number 2
01H (line number high byte) 05H (line number low byte), line number 3 01H (line number high byte) 07H (line number low byte), line number 10 01H (line number high byte) 15H (low byte for line number), 01H for line number 100 (high byte for line number) C9H
(Line number low byte). These line numbers are specified to be incremented every 3 lines.

FIG. 6 exemplifies a state in which coded data and a retransmission start address corresponding to each line number are stored in the memory. In the figure, TFIFS is the start address (8400H in this embodiment) of the memory that stores the encoded data. As a memory area for storing encoded data in the transmission side device, for example, 8400H to AFF
Think up to FH. Consider, for example, C000H to C3FFH as a memory area for storing the retransmission start address.

Now, as the condition of the transmitting side device, when the minimum transmission time when one line is all white is 10 msec, the minimum transmission time when there is black on one line is 20 msec, and the transmission speed is 4800 b / s, A procedure for transmitting an A4 size document (all white) will be described with reference to FIG. At this time, the minimum number of bytes in one line is 6. Also, when the byte data stored in the memory is transmitted, it shall be transmitted from the LSB. For example, when sending data at address 8401H, first set 0
7 bits of information, and then 1 information.

In FIG. 6, EOL is formed by the data stored in the addresses 8400H and 8401H (1 information is sent after 15 consecutive 0 information). Address number 8402H stores the line number high byte data, and address 8403H stores the line number low byte data. address
The data stored in 8402H and 8403H are 01H and 01H, and represent line number 0.

Addresses 8404H to 8406H store modified Huffman-encoded data when 1728 bits are all white. That is, the modified Huffman-encoded data when it is 1728 bits all white is 01 001
1 011 0011 01 01 (when data is sent to the line in order from the left side data). Here, 010011011 is a makeup code in the case of 1728 bit white run length,
00110101 is a terminating code in the case of 0-bit white run length. When the modified Huffman-encoded data in the case of 1728-bit all white is stored in the memory, it becomes B2H, 59H, 01H.

When data is sent to the line, the data from LSB of B2H to MS
B data, 59H LSB data to MSB data, 01H L
The data is sent in order from SB data to MSB data. That is, 01001101 (B2H data) 100 11010 (59H data) 1000
Data is sent to the line in the order of 0000 (data of 01H) (when data is sent to the line in order from the left data). Thereafter, similarly, the encoded data is stored in the memory of the transmission side device.

On the other hand, the retransmission start address is stored in the memory corresponding to each line number. The memory area that stores the resend start address is from address C000H to address C3FFH.
Is. The start address of the memory area where the retransmission start address is stored is called LIN0. In order to specify one retransmission start address, the memory area requires 2 bytes. The memory area from address C000H to address C3FFH is
Since it is 1024 bytes, it is possible to store 512 retransmission start addresses. Further, as described above, the line number is configured to be incremented every 3 lines, so the line number has changed (that is,
When incremented by 1), the start address of the line number of the memory storing the encoded data is stored in the memory storing the retransmission start address. A specific example is as shown in FIG.

00H and 84H are stored in the addresses C000H and C001H.
The data stored in the address C000H is the raw data and the address at the retransmission start address of line number 0.
The data stored in C001H is high data at the retransmission start address of line number 0, and the head address where line number 0 is stored (for the memory storing encoded data) is 8400H. Is.

Further, 15H and 84H are stored in the addresses C0002H and C003H. The data stored at address C002H is the raw data at the retransmission start address of line number 1, the data line number 1 stored at address C003H.
Is the high data at the retransmission start address of, and the head address where the line number 1 is stored (for the memory where the encoded data is stored) is 8415H. Similarly, the head addresses where the line numbers 2, line numbers 3 and line bars 4 are stored (for the memory storing the encoded data) are:
They are 842AH, 843FH and 8454H.

Further, as described above, since the memory area for storing the retransmission start address is 1024 bytes, 512 retransmission start line numbers can be stored. The 513th line number is stored in LIN0 (address C000H). Thus, the last 512 line numbers will be stored.

In the transmission side device, the data encoded according to this embodiment is stored in a FIFO (First-In First-Out) memory. FIG. 7 shows the relationship between the FIFO memory and various pointers. The capacity of the FIFO memory is 8400H to AFFFH as described above. Here, the start address of the FIFO memory of the transmission side device is TFIFS (TRN FIFO START; 8400 in this embodiment).
H), the high byte at the start address of the FIFO memory of the transmission side device is TFIFSH (TRN FIFO START HIGH; 84H in this embodiment), and the final address in the FIFO memory of the transmission side device is TFIFE (TRN FIFO END; this embodiment) At AFFF
H), the high byte at the final address of the FIFO memory of the transmission side device is called TFIFEH (TRN FIFO END HIGH; AFH in this embodiment).

In the transmitting side device, the data read by the reading means (not shown) is FI of the transmitting side device after being encoded.
Stored in FO memory, but uses pointers to control the FIFO memory. The pointer used for this purpose is called TMHPTR (TRN MH POINTER). The data stored in the FIFO memory on the transmitter side is sequentially transmitted to the line after being modulated by the modulator, but a pointer for controlling the FIFO memory is also required here. The pointer used for this is TMDPTR (TRN MODEM POINTER)
Call.

On the other hand, in the receiving side device, the data sent from the transmitting side device is stored in the memory. This memory is a first-in first-out (FIFO) memory like the transmission side device.
The FIFO memory capacity of the receiving device is the same as that of the sending device.
From 8400H to AFFFH.

Here, the start address in the FIFO memory of the receiving side device is RFIFS (REC FIFO START; 8400H in this embodiment),
The high byte of the start address in the FIFO memory of the receiving device is RFIFSH (REC FIFO START HIGH; 84H in this embodiment), and the final address in the FIFO memory of the receiving device is RFIFE (REC FIFO END; AFFFH in this embodiment). ), The high byte of the final address in the FIFO memory of the receiving side device is RFIFEH (REC FIFO END HIGH; AF in this embodiment is
H).

In the receiving side device, the data sent from the transmitting side device is demodulated by the demodulator and then stored in the FIFO memory. A pointer is used to store the demodulated data in the FIFO memory, and this pointer is used for RMDPTR (REC MODEM
POINTER). Further, the data stored in the FIFO memory is sequentially read, decoded, and recorded. The pointer is also used when sequentially reading and decoding the data stored in the FIFO memory, but this pointer is used for RMHPTR (R
EC MH POINTER).

The management of the FIFO memory included in the transmission side device will be described below. TMHPTR indicates up to which address in the FIFO memory space the encoded data is stored. On the other hand, TMDPTR indicates in the FIFO memory space up to which address data is modulated and transmitted to the line.
The encoder stores the encoded data from the TFIFS address, and when storing the encoded data up to the TFIFE address, stores the next encoded data in the TFIFS address.
At this time, a flag called REVRS (reverse) is set to 1 to notify the modem side that the encoded data is stored up to the last address of the FIFO and TMHPTR has returned to the head of the FIFO.

On the other hand, as the processing on the modem side, the encoded data from the TFIFS address is sequentially read out, modulated and then sent to the line. Then, after reading the data stored in the TFIFE address, modulating it and sending it to the line, it reads the data stored in the TFIFS address, modulating it and sending it to the line. At this time, the side that is encoding by setting 0 to the REVRS (reverse) flag has finished the data modulation at the last address of the FIFO and the transmission to the line, and TMDPTR has returned to the beginning of the FIFO. Let me know.

The main operations of the FIFO management in the transmitting side device are as follows.

When the line number is changed, the address storing the encoded data corresponding to the line number is stored in the memory for storing the retransmission start line number.

Ensure that the modem's pointer, TMDPTR, does not overtake the encoder's pointer TMHPTR.

Therefore, a distance of a predetermined amount of untransmitted image data is provided between the encoder pointer TMHRTR and the modem pointer TMDPTR. If the untransmitted image data is a predetermined amount, the image data is transmitted, and if not, the image data is aligned by a predetermined amount. It is conceivable to control so as to wait until until transmission.

However, at this time, the page reading may end when the amount of untransmitted image data is less than or equal to a predetermined amount at the end of the page. In that case, the untransmitted image data waits for a predetermined amount of image data to be gathered for a certain period of time, and after a certain period of time,
It is determined that there is no subsequent image data on the page, and the untransmitted image data on the page is transmitted. However, during this waiting time, if the next page is read and the image data at the beginning of the next page exceeds the specified amount, the untransmitted image data at the end of the previous page waiting to be transmitted First, the inconvenience of transmitting the first image data of the next page occurs.

The present invention aims to eliminate this inconvenience (object of the present invention).

The encoder pointer TMHPTR goes around the FIFO memory so that it does not come too close to the modem pointer TMDPTR. (When the receiving side retransmits when a reception error occurs, the data for this retransmission is left in the FIFO memory. To keep).

The above has already been described with reference to FIG. 6, and therefore the description is omitted here.

Next, in order to explain the operation of this embodiment, the above description will be made. To prevent the modem pointer TMDPTR from overtaking the encoder pointer TMHPTR, send a fill when the modem pointer TMDPTR approaches the encoder pointer TMHPTR. Here, when encoding the read data, EOL consists of 2 bytes, 00H, 80
The data is for H (see Fig. 6). The following actual examples are conceivable as examples of control of such items.

When the pointer TMDPTR of the modem detects the data of 00H and 80H while sending the data of the FIFO memory, the REVRS (reverse) flag is checked. When the REVRS (reverse) flag is 0, (high address in encoder pointer TMHPTR)
-(High address in modem pointer TMDPTR) <
2 is judged, and when the above condition is satisfied, the fill is transmitted (the operation of “prohibiting transmission of untransmitted image data” of the present invention), and when the above condition is not satisfied, that is, (Address in encoder pointer TMHPTR) −
(High address in modem pointer TMDPTR) ≧ 2
In this case, the pointer TMDPTR of the modem is sequentially incremented to send out the data stored in the FIFO memory.

On the other hand, when the REVRS (reverse) flag is 1, first, the high address in the pointer TMDPTR of the modem is TF.
It is determined whether it is equal to IFEH (byte at the final address of FIFO). When the high address in the pointer TMDPTR of the modem is not equal to TFIFEH, the pointer of the modem is sequentially incremented to send out the data stored in the FIFO memory.

When the modem pointer TMDPTR is equal to TFIFEH, (high address in encoder pointer TMHPTR)
-If TFIFSH <1 is judged, and if the above condition is satisfied, fill is transmitted (the operation of "prohibiting transmission of untransmitted image data" of the present invention), and the above condition is not satisfied. , Ie, (high address in encoder pointer TMHPTR)
-If TFIFSH ≥ 1, the modem pointer TMDPTR is sequentially incremented to send the data stored in the FIFO memory.

In the above case, even when the fill is transmitted, all the encoding is completed (actually, when the encoding is completed, the flag MHEND is set to 1, so the modem side sets this flag. By checking it, it is possible to recognize whether or not all coding is completed.) When the modem pointer TMDPTR
Is sequentially incremented to transmit the data stored in the FIFO memory (the operation of "transmitting the untransmitted image data when the end of page is detected" of the present invention.

Further, when the transmission of all encoded data is completed, an RTC (Return To Control) signal is transmitted.

According to the present invention as described above, when the untransmitted image data that has not been transmitted by the transmitting unit is equal to or less than the predetermined amount and the page end is not detected by the detecting unit, the transmission of the untransmitted image data is prohibited and the untransmitted image data is transmitted. When the end of the page is detected by the detecting means even if the image data is less than or equal to a predetermined amount, the untransmitted image data is transmitted. When the amount of data becomes less than a predetermined amount and the next page is transmitted, the page management on the receiving side becomes complicated. However, the present invention can easily do this, and at the beginning of the next page an error occurs. If there is, it can be prevented that the page cannot be recorded forever (effect of the present invention).

Next, the above will be described. FIG. 8 shows the number of bits and the number of bytes transmitted in 3 seconds at each transmission speed. That is, the encoder pointer TMHPTR needs to be separated from the modem pointer TMDPTR by 3600 or more in order to be able to perform re-transmission up to a delay of 3 seconds in a round trip.

FIG. 9 shows the relationship between the FIFO memory and various pointers. In this embodiment, when the high address in the encoder pointer TMHPTR is incremented, the modem pointer TM
As compared with DPTR, the encoder pointer TMHPTR is controlled to be separated from the modem pointer TMDPTR by 4096 or more. The specific example of the control is shown below.

When incrementing the high address in the encoder pointer TMHPTR, the REVRS (reverse) flag is checked. When the REVRS (reverse) flag is 0, it is determined whether or not {TIFEH- (high address in encoder pointer TMHPTR)} + {(high address in modem pointer TMDPTR) -TFIFSH} <16, and When the condition is satisfied, the encoding is suspended and the wait state is set. When the above condition is not satisfied, that is, {TFIFEH- (high address in encoder pointer TMHPTR)} + {(high address in modem pointer TMDPTR) -TFIFSH} ≧ 16, encoding is performed,
Store the encoded data in the FIFO memory.

On the other hand, when the REVRS (reverse) flag is 1, (high address in the modem pointer TMDPTR)-
(High address in encoder pointer TMHPTR)
If it is <16, and if the above conditions are met, encoding is suspended and a wait state is entered. When the above conditions are not met, ie (high address in modem pointer TMDPTR) −
(High address in encoder pointer TMHPTR)
When ≧ 16, encoding is performed and the encoded data is stored in the FIFO memory.

In this embodiment, the memory area for storing the retransmission start address is
I am thinking of 1024 bytes. Therefore, 512 retransmission start addresses can be stored. Ie 512 in the past
The line number can be retransmitted. here,
When one line is encoded, the shortest data is when one line is all white. As described above, the number of bytes when encoding all white lines is 7 bytes. 1
Since the line number is incremented every 3 lines, the minimum number of bytes in one line number is 21. Then, considering retransmission of 512 line numbers, a minimum of 10752
I need a bite. At this time, the transmission speed is 9600b / sec
Also, 10752 (bytes) / 1200 (bytes / second)
≅9 (seconds), and 3 seconds is considered as the time to allow the delay on the line as described above, so it is sufficient to store the retransmission start address in the memory having a capacity of 512.

The receiving side device is provided with a memory area for storing the latest received line number. Then, at the time of initialization, the data of 0101H is stored. Then, the decoder checks the next 2-byte data, that is, the line number, every time the EOL is detected. Then, if the line number is the same as the last time or is incremented by one, it is determined that the received image is “good”. The line number is stored and updated in memory each time it is detected.

On the other hand, when the line number is incremented by 2 or more compared with the previous time, the NACK signal is transmitted. In this embodiment, a PIS signal (a signal in which a 462 Hz signal is continuous for 3 seconds) is transmitted. Then, after confirming that the signal from the transmission side device is disconnected, the retransmission start line number is notified to the transmitter by using the signal of 300b / s.

FIG. 10 shows an example of a 300 b / s signal for notifying the retransmission start address from the reception side device to the transmission side device. In this figure, the preamble is the continuous transmission of "0111 1110" pattern, FFH
Is address data, 13H is control data (LSB data is sent to the line in the order of MSB data), 20H is NS
It is the FCF (Facsimile Control Field) of F. Further, the line numbers transmitted thereafter are data focusing on the lower 9 digits of the line number, and are from line number 0 to line number 511. Regarding the line number transmitted at this time, 1 is not set to the LSB of each byte data. For example, the line number 0 is 00H and 00H. FCS is a frame check sequence and FLAG is “0111 1110”. When decoding, the 2-byte data following EOL is ignored.

The transmission side device reads the information of the original by the reading means (not shown), encodes the data by the encoder, modulates the encoded data by the modem, and sends out to the line. At this time, the NACK signal (PIS signal in this embodiment) is being monitored. Then, when the NACK signal is not detected, the image information is transmitted, and when the NACK signal is detected, the transmission of the image information is interrupted. Then, it goes to receive the 300b / s signal. In this 300 d / s, as described above, the line number (lower 9 digits) for starting the retransmission is stored.

When the sending device detects the retransmission start line number, it checks the address in the encoder pointer TMHPTR of the sending device, the address of the modem pointer TMDPTR in the sending device, the REVRS (reverse) flag, and the resending start address, and based on the result Various controls.
As the control example, the following three cases can be considered.

In the first case, when the REVRS flag is 0, the encoder pointer TMHPTR in the transmitting device is larger than the modem pointer TMDPTR in the device, and the modem pointer TMDPTR in the transmitting device is larger than the retransmission start address. Is. 11 (1) to 11 (3) show three cases in which the retransmission start address is recognized and retransmission is performed. The first case described here is illustrated in FIG. 11 (1). In this case, the retransmission start address is set in the pointer TMDPTR of the modem in the transmitting side device, and the retransmission is performed from that line number.

The second case is illustrated in Figure 11 (2). That is, the REVRS (reverse) flag is 1 and the pointer TMDPTR of the modem in the transmission side device is larger than the pointer TMHPTR of the encoder in the device. In this case, the modem pointer TMDPTR in the sending device
The retransmission start address is set in and the retransmission is performed from that line number. Here, if the encoder pointer TMHPTR in the transmission side device is larger than the retransmission start address, it is determined that an error has occurred, and the DCN signal or the like (at 300 b / s) is transmitted without transmitting the image information. , Open the line.

The third case is illustrated in Figure 11 (3). That is, when the REVRS (reverse) flag is 0 and the encoder pointer TMHPTR in the transmitting device is larger than the modem pointer TMDPTR in the device, the retransmission start address pointer is larger than the modem pointer TMDPTR in the transmitting device. This is the case. In this case, the retransmission start address is set in the pointer TMDPTR of the modem in the transmitting side device, and the retransmission is performed from that line number.
Here, the encoder pointer TMHP in the transmitting device
If TR is larger than the retransmission start address, it is judged as an error and the image information is not transmitted, for example, DCN signal (30
0b / s) to release the line.

Next, other processing in the receiving side device will be briefly described. When the reception is good, the 2 bytes (that is, the data of the line number) following the EOL are ignored and decoding is performed. On the other hand, as a result of checking the line number, if a reception error occurs, a retransmission request is issued. As controls other than this, for example, the following control is performed.

1) If EOL cannot be detected for 5 seconds, it is judged as an error and the line is opened.

2) If the carrier is not detected continuously for 5 seconds, it is judged as an error and the line is opened.

3) If error retransmissions are performed a predetermined number of times or more while receiving one piece of image information, fall back the transmission rate or disconnect the line.

4) When the control return signal RTC is detected, the image information receiving process is terminated.

FIG. 12 is a block diagram showing the configuration of the transmission side of the facsimile machine to which the present invention is applied.

In FIG. 12, 2 is a network controller NC that holds a loop.
U (Network Control Unit), which connects to a terminal of the line to control connection of the telephone switching network or switches to a data communication path in order to use the telephone network for data communication and the like.

2a is a telephone line.

Reference numeral 4 is a hybrid circuit for separating a transmission system signal and a reception system signal. The transmission signal of the signal line 28a passes through the signal line 2b and is sent to the telephone line 2a via the network control device 2.
The signal sent from the facsimile machine on the other side is output to the signal line 4a after passing through the network control device 2.

Reference numeral 6 is a circuit for detecting a retransmission request signal (a PIS signal is used in this embodiment) sent from the receiver ("reception means" of the present invention). That is, the signal of the signal line 4a is introduced, and when the retransmission request signal (the PIS signal in this embodiment) is detected, the signal of the signal level "1" is output to the signal line 6a. On the other hand, when the signal of the signal line 4a is introduced and the retransmission request signal (PIP signal in this embodiment) is not detected, the signal of signal level "0" is output to the signal line 6a.

Reference numeral 8 denotes a 300b / s signal (in this embodiment, which uses an NSF signal (see FIG. 10)) in which a retransmission start line number is stored, which is transmitted subsequently to the retransmission request signal from the receiving side device, and the retransmission. Disconnection command sent after request signal
This circuit receives the (DCN) signal (300b / s signal). This binary signal receiving circuit 8 detects the NSF signal,
A pulse is generated on the signal line 8a and a retransmission start line number is output on the signal line 8b. The binary signal receiving circuit 8 also generates a pulse on the signal line 8c when detecting a DCN signal.

A reading device 10 reads an image signal for one line in the main scanning line direction from a transmission document and creates a signal sequence representing binary values of white or black ("reading means" of the present invention). The reader 10 is composed of an image pickup device such as a CCD (charge coupled device) and an optical system. When a pulse is generated on the signal line 12a, that is, when there is a request to read the image signal of one line, the image signal of one line is read and binarized data is output to the signal line 10a.

Reference numeral 12 is a double buffer circuit for allowing the image signal of the next line to be written in the other buffer memory while the image signal in one buffer memory is being encoded. Two buffers are BUF0 (buffer 0) and BUF1
It is called (buffer 1). When the buffer of BUF0 is full of image data, it outputs a signal of signal level "1" to the signal line 12b (buffer 0 full). When the image data is not clogged in the buffer of BUF0, the signal of the signal level "0" is output to the signal line 12b (buffer 0 full). When the buffer of BUF1 is full of image data, it outputs a signal of signal level "1" to the signal line 12c (buffer 1 full). When the buffer of BUF1 is not full of image data, it outputs a signal of signal level “0” to the signal line 12c (buffer 1 full).

After confirming that the buffer is full, the control circuit 30, which will be described later, specifies the buffer to be read next by the signal output to the signal line 30b (when the signal line 30b is at the signal level “0”, the buffer is read). 0 data is read; when the signal line 30b is at the signal level "1", the data in the buffer 1 is read), and then a pulse (read pulse) is generated on the signal line 30a.

The double buffer circuit 12 outputs the data in the designated buffer to the signal line 12d. Then, when the output of the data of the designated buffer to the signal line 12d is completed, the buffer full of the designated buffer is dropped. That is, the signal line 30
When the signal level output to b is “0” (buffer 0 is designated) and a (read) pulse is generated on the signal line 30a and all the data in the buffer is output, the buffer full 0 is dropped (ie, , And outputs a signal of signal level “0” to the signal line 12b). When the signal level output to the signal line 30b is “1” (buffer 1 is designated) and a (read) pulse is generated on the signal line 30a and all the data in the buffer is output, the buffer full 1 is output. (That is, a signal of signal level “0” is output to the signal line 12c).

Further, the double buffer circuit 12 generates a pulse on the signal line 12a when the buffer becomes empty, and inputs the data for one line in the main scanning direction from the reading device 10. In this case, the data is stored in the empty buffer, but at the same time, 1 is set in the buffer full in which the data is stored. The read data is buffer 0, buffer 1,
It is stored alternately with buffer 0 and buffer 1.

Reference numeral 14 is a counter that counts the line number inserted after the line end code (EOL). When a pulse is generated on the signal line 30c, the line number is set to 0 (0101H). Then, each time a pulse is generated on the signal line 30d, the line number value is incremented. That is,
When a pulse is generated in the signal 30d while the line number is 0 (0101H), the line number is 1 (0103H). The same applies hereinafter. The 2-byte data indicating the line number is output to the signal line 14a.

Reference numeral 16 is a circuit for inputting one line of binarized data output to the signal line 30e and outputting encoded data (modified Huffman encoding in this embodiment) to the signal line 16c. A pulse is generated on the signal line 16a when the number of bits when the binary data of one line is input and encoded becomes eight, that is, when the encoded data of 1 byte is complete. . On the other hand, when the encoding of one line is completed, an (end) pulse is generated on the signal line 16b. When the last data is less than 8 bits when the encoding of one line is completed, the remaining data is set to 0 and the processing is performed assuming that all the data are 8 bits.

Reference numeral 18 is a FIFO memory used for reading line data and storing encoded data ("memory means" of the present invention). On the other hand, the modem side reads the data stored in this FIFO memory and sends it to the modulated line. From the signal line 30f to the three signal lines 30h,
Write the encoded data to the FIFO memory. Signal line 30f
When a (write) pulse is generated at, the byte data output to the signal line 30h is stored at the address output to the signal line 30g. Further, the data stored in the FIFO memory is read out by the three signal lines of the signal line 30i, the signal line 30j, and the signal line 18a. When a (read) pulse is generated on the signal line 30i, the data of the address output on the signal line 30j is output on the signal line 18a. In this embodiment, the FIFO memory has addresses from 8400H to AFFFH.

20 is a memory for storing the retransmission start address.
When a reception error occurs on the reception side, the transmission side device retransmits from the line number where the error occurred. When the transmission side device retransmits from a certain line number, it is necessary to recognize from which address of the FIFO memory the data of that line number is stored, but this data is stored in this memory. Using the signal line 30k, signal line 30l, and signal line 30m, the data of a certain line number is
Write the information "where in the memory is stored from the memory" to the main memory 20. When a (write) pulse is generated in the signal line 30m, the byte data of the signal line 30l is written in the address output to the signal line 30k. Store, and signal line 30
By using k, the signal line 30n, and the signal line 20a, the information "where in the FIFO memory the data from a certain line number is stored" is read from the main memory 20.

Then, when a (read) pulse occurs on the signal line 30n,
The address data output to the signal line 30k is output to the signal line 20a. Retransmission start address storage memory is from C000H to C
It has an address of 3FFH. The memory structure for storing the retransmission start address is as shown in FIG.

As shown in FIG. 13, the addresses of the liner bars 0, 512, ... Are stored in the addresses C000H, C001H.
Addresses of line numbers 1, 513 ... are stored in 2H, C003H, and line numbers 2, are stored in addresses C004H, C005H.
The address of 514 ... is stored, and so on.
Addresses of line numbers 510, 1022 ... are stored in CH, C3FDH, and line numbers 511, 1 are stored in addresses C3FEH, C3FFH.
The address of 023 ... Is stored.

22 is a parallel-serial conversion circuit (hereinafter, abbreviated as P / S conversion circuit) that converts parallel data to serial data.
Is. The P / S conversion circuit 22 generates a byte data request pulse on the signal line 22a when the parallel data becomes empty. The control circuit 30, when a pulse is generated in the signal line 22a,
Byte data is output to the signal line 300. On the other hand, the P / S conversion circuit 22 inputs the byte data output to the signal line 300, performs parallel-serial conversion, and then outputs the serial data to the signal line 22b.

Reference numeral 24 is a modulator that performs modulation based on the well-known CCITT recommendation V27ter (differential phase modulation) ("transmitting means" of the present invention). The modulator 24 receives the signal on the signal line 22b, modulates the signal, and outputs the modulated data to the signal line 24a.

26 is on signal line 26a when a pulse occurs on signal line 30p
This is a circuit that sends out a DCN signal (300b / s signal). This DCN
When the transmission of the DCN signal ends, the signal transmission circuit 26 generates a pulse on the signal line 26b.

Reference numeral 28 is an adder circuit that inputs the signal of the signal line 26a of the signal of the signal line 24a and outputs the addition result to the signal line 28a.

Reference numeral 30 is a control circuit that performs the following control (“detection means” and “control means” of the present invention). However, the encoding is processed according to the main routine, and the signal transmission is processed by the interrupt routine.

The encoding process by the control circuit 30, that is, the control process in the main routine is as shown in FIG. First,
Modem pointer TMDPTR and encoder pointer TM
HPTR is set to the start address of the FIFO memory that stores the encoded data (step S100). Then, it is determined whether the reading of the image information of one main scanning line is completed, that is, whether the line buffer is full (step S102).

When the reading of the image information of the main scanning line in one line is completed (that is, when the line buffer becomes full),
Proceed to step S104. Then, the data of one line is read (step S104). Here, as described above, the buffer has a double buffer structure of buffer 0 and buffer 1, and data is alternately read from these two buffers.

After reading the data from each buffer, the data is encoded and the encoded data is written to the FIFO memory (step S1
06). The main control at the time of encoding is shown in the following itemized list.

1. Write the encoded data to the FIFO memory.

2. Set the line end code (EOL signal) (00H and 80H for writing data to the FIFO memory) and the line number to FI.
Write to FO memory.

3. When a reception error occurs in the receiving side device, the transmitting side device retransmits the data from the line number in error. The following control is performed so that this retransmission can be performed.

That is, when incrementing the byte in the encoder pointer TMHPTR, the encoder pointer TMHPTR
TR goes around the FIFO memory to the pointer TMDPTR of the modem,
Control so that you do not get too close. Specifically, when the encoder pointer TMHPTR approaches the modem pointer TMDPTR to some extent or more, the encoding is interrupted and the wait state is set. Then, while waiting, it is checked whether or not the PIS signal is detected, and when the PIS signal is detected, the NSF signal is received. Then, the pointer of the modem is set to the retransmission start address, and the data is retransmitted. When retransmitting, perform training again. This is performed from step S108 to step S1 described later.
It is the same as 12 controls.

4. When resending from a certain line number, it is necessary to recognize from which address of the FIFO memory the data of that line number is stored. This information is stored in the retransmission start address storage memory.

Then, when the coding of a certain line is completed, it is determined whether or not the retransmission request signal, that is, the PIS signal is detected (step S108). When the retransmission request signal, that is, the PIS signal is detected, the transmission of the image information is interrupted and the NSF signal is received (step S110). And the modem pointer TM
DPTR is set to the retransmission start address (this information is included in the NSF signal), and the data is retransmitted (step S112).

Next, it is determined whether the encoding of one original has been completed (step S114). If the encoding of one original has not been completed, the process returns to step S102. If the encoding of one document is completed, the process proceeds to step S116.

When the encoding of one original is completed, it is determined whether or not the unencoded data remains in the double buffer memory (step S116). If there is still unencoded data in the double buffer memory,
Return to step S102. If no unencoded data remains in the double buffer memory, the process proceeds to step S118, and the control return signal RTC (Return To Control) is set.
Write to FIFO memory.

On the other hand, the transmission processing (that is, the interrupt processing) includes (a) modulating the data stored in the modem pointer TMDPTR and transmitting the data to the line, (b) sequentially incrementing the modem pointer TMDPTR, and (c) Modem pointer TMDPTR is encoder pointer
The main content is to control so as not to overtake TMHPTR.

Next, the control procedure (encoding processing procedure) performed by the control circuit 30 will be described with reference to the flowcharts shown in FIGS. 15 (1) to 15 (9).

First, various initialization processes are performed in steps S128 to S144.

In step S128, a flag TRNEND indicating whether or not all the data stored in the encoded FIFO memory has been transmitted is set to 0.

In step S130, C000H is set in the pointer AGAPTR that controls the memory that stores the retransmission start address.

In step S132, the encoder pointer TMHPTR
Set 8400H to.

In step S134, the pointer TMDPTR of the modem is set to 84.
Set 00H.

The line number is incremented every fixed number of lines (3 lines in this embodiment).
It is controlled by a counter called LINCNT. Step S136
In, the counter LINCNT is set to 3.

In step S138, the REVRS flag described above is set to zero.

In step S140, 0 is set to the flag MHEMD indicating whether or not the encoding is completed.

In step S142, a flag BAF indicating which buffer is currently reading data is set to 0. When the flag BAF is 0, data is read from the buffer 0. When the flag BAF is 1,
Data is being read from buffer 1.

In step S144, the line number is initialized.

In steps S146 to S154, it is determined whether the buffer is full, that is, whether reading of one line is completed. If the buffer is full, step S1
Continue to 56. Here, the data in the buffer is buffer 0,
Alternately read with buffer 1.

In steps S156 to S160, one line of data is read from the double buffer and output to the encoder.

In step S162 to step S182 shown in FIG. 15 (2), the retransmission start address storage is performed to determine from which address of the FIFO memory the data of the specific line number is stored so that the data of the specific line number is retransmitted. Store in memory. Here, when the line number changes, the retransmission start address is stored in the retransmission start address storage memory.

In step S162, control is performed to increment the line number every 3 lines. In steps S164 to S168, the raw byte data at the retransmission start address is stored in the retransmission start address storage memory.

In step S170, the retransmission start address pointer AG
Increment APTR. In steps S172 to S176, the high-byte data at the retransmission start address is stored in the retransmission start address storage memory. In step S178, the retransmission start address pointer AGAPTR is incremented. In step S180, it is determined whether the retransmission pointer AGAPTR has reached the end of the retransmission start address storage memory. Then, when the retransmission pointer AGAPTR advances to the end of the retransmission start address storage memory, C000H is set in the retransmission pointer AGAPTR (step S182).

In steps S184 to S188 shown in FIG. 15 (3), 00H is stored in the FIFO memory.

In step S190, the encoder pointer TMHPTR
Is incremented. The increment of TMHPTR will be described later.

In steps S192 to S196, 800H is stored in the FIFO memory.

In step S198, the encoder pointer TMHPTR
Is incremented.

In steps S200 to S216, the line number is input and the line number is stored in the FIFO memory. That is, in step S200, the line number is input. In steps S202 to S206, the high byte data of the line number is stored in the FIFO memory. In step S208, the encoder pointer TMHPTR is incremented. Step S210
Or, in step S214, the low byte data of the line number is stored in the FIFO memory. Step S216
In, the encoder pointer TMHPTR is incremented.

In steps S218 to S230 shown in FIG. 15 (4), the encoded data is stored in the FIFO memory.

First, in step S218, it is determined whether or not 1-byte data has been encoded. When 1-byte data is encoded, the data is input (step S220), and 1
The encoded data of bytes is stored in the FIFO memory (steps S222 to S226).

In step S228, the encoder pointer TMHPTR
Is incremented. In step S230, it is determined whether the encoding of one line is completed. If the encoding of one line is not completed, the process proceeds to step S218. When the encoding of one line is completed, the process proceeds to step S232.

In steps S232 to S238 shown in FIG. 15 (5), it is checked whether or not the line number is incremented. If it is necessary to increment the line number, the line number is incremented. Here, the line number is incremented every 3 lines.

In steps S240 to S248, it is determined whether a retransmission request signal, that is, a PIS signal has been received. P
When the IS signal is received, the NSF signal is received and the retransmission start line number is input. Then, the retransmission start address is set in the pointer TMDPTR of the modem, and data is transmitted from that address.

In step S250, it is determined whether or not the encoding of one original has been completed. If the encoding of one document is completed, the process proceeds to step S252. If the encoding of one original has not been completed, the process proceeds to step S146.

In steps S252 and S254, it is determined whether either buffer is full. Buffer 0,
Alternatively, if one of the buffers 1 is full, the process proceeds to step S146. If neither the buffer 0 nor the buffer 1 is full, the process proceeds to step S256.

In steps S256 to S300 shown in FIGS. 15 (6) and (7), the control recovery signal RTC (Retu
rn To Control) signal is stored.

First, in steps S256 to S260, 00
Store H data to FIFO memory.

In step S262, the encoder pointer TMHPTR
Is incremented.

In steps S264 to S268, 80H data is stored in the FIFO memory.

In step S270, the encoder pointer TMHPTR
Is incremented.

In steps S274 to S296, 00H, 08H,
Store 80H data in FIO memory. Step S272,
By steps S298 and S300, 00H, 08H, and 80H data are stored in the FIFO memory.

In step S302, since the encoding is completed, the flag
MHEND is set to 1 and waits until the modem transmits all encoded data (step S303). And when the modem sends out all the encoded data,
The image transmission ends (step S304).

Step S306 to step S326 shown in FIG. 15 (8),
Detects a resend request signal (that is, PIS signal) during transmission,
This is a subroutine for setting the pointer TMHPTR of the modem to the retransmission start address (step S248, step
S348).

As described above, the set of retransmission start address is 1) REVRS
When the flag is 0 1-1) TMHPTR> TMDPTR and the resend address <TMDP
When TR is 1-2) TMHPTR> TMDPTR, and resend address> TMHPTR, and resend address> TMHPTR (in this case, REVRS is set to 1) 2) When REVRS flag is 1, TMDPTR> TMHPTR, If the resend address> TMHPTR, the resend address is set in the pointer TMDPTR of the modem (step S318) and the process returns (step S320).
Other than that, it is an error.

In steps S328 to S354 shown in FIG. 15 (9), the encoder pointer TMHPTR is incremented.

Here, in step S330, the pointer TMHPTR of the encoder is incremented. Then, when the high byte of TMHPTR is not incremented, the process immediately returns, but when the high byte of TMHPTR is incremented, the process proceeds to step S334.

In step S334 and step S338, the encoder pointer TMHPTR goes round and the modem pointer TMDP
Control not to get too close to TR. That is,
The encoder pointer TMHPTR is the modem pointer TMDP
When TR is more than 4096, return. At this time, it is checked whether or not the encoder pointer TMHPTR has reached the end of the FIFO memory. If it has reached the end of the FIFO memory, the encoder pointer TMHPTR is set to 84
Set 00H.

Encoder pointer TMHPTR is Moden pointer TMDPTR
If it is not more than 4096, the encoding is interrupted and the wait state is entered. During this waiting, it is determined whether or not the retransmission request signal (that is, the PIS signal) is detected (step S340). When the PIS signal is detected, the transmission is interrupted (step S342) and the NSF signal is received (step S344). Then, enter the retransmission start line number (step S346) and set the modem pointer TMHPTR.
Set the resend address to.

In the present embodiment, when the PIS signal is received, the NSF signal is received, but when the DCN signal is received at this time, the line is disconnected and the error processing is terminated.

The flowchart shown in FIG. 16 shows a detailed control process relating to a transmission process (that is, an interplat process) of encoded data. In this embodiment, when a pulse (that is, a byte data request pulse) is generated on the signal line 22a,
This interrupt process is executed.

The main control here is to sequentially read the data stored in the FIFO memory (step S370 to step S376), P /
Output to the S conversion circuit 22 (step S380 to step S380
386, step S390 to step S396).
At this time, the pointer TMDPTR of the modem is controlled so as not to overtake the pointer of the encoder. In other words, when 00H and 80H data is detected during transmission of encoded data, as described above, if the encoder pointer TMHPTR is not ahead of the modem pointer by a certain amount, a fill is transmitted and encoded. Wait for the progress (step S3
80 to step S392, step S404 to step S
410) C) "Prohibit transmission of untransmitted data" operation of the present invention). Here, this is not limited to the case where MHEND is 1 (that is, when the encoding of one document is completed) (when the "end of page is detected in the present invention, transmission of the untransmitted image data is transmitted. "Do" action). The modem pointer
When reaching the end of the FIFO memory, the pointer TM of the modem
DPTR is set to the start address 8400H of the FIFO memory (steps S398, S400).

When all the coding is completed (MHEND = 1) and the modem sends out all the coded data (TMHPTR = TMDPTR) (step S364), TRNEND is set to 1 (step S36).
6) Notify the main processing routine (encoding processing routine) that the transmission of encoded data has been completed.

FIG. 17 is a block diagram showing the configuration of the receiving side of the facsimile apparatus to which the present invention is applied.

In FIG. 17, 40 is the same network control device as 2 shown in FIG.
(NCU). Further, 40a indicates a telephone line.

42 is a hybrid circuit similar to 4 shown in FIG. The signal transmitted to the signal line 54a passes through the signal line 40b,
It is sent to the telephone line 40a via the network control device 40. Also, the signal sent from the facsimile machine on the other side is
After passing through the rope control device 40, it is output to the signal line 42a.

Reference numeral 44 is a circuit that receives a signal from the signal line 42a and detects whether or not there is a signal. When a signal of -43 dBm or more is received, the signal of the signal level "1" is output to the signal line 44a, and when a signal of less than -43 dBm is received, the signal line 44
The signal of signal level "0" is output to a.

Reference numeral 46 is a demodulator that performs demodulation based on the well-known CCITT recommendation V27ter (differential phase modulation). The demodulator 46 uses the signal line 42a.
Signal is input and demodulated, and the demodulated data is sent to the signal line 46a.
Output to.

A serial-parallel conversion circuit 48 converts serial data into parallel data (hereinafter, abbreviated as S / P conversion circuit). The S / P conversion circuit 48 generates a pulse on the signal line 48a when the 8-bit parallel data is complete, and outputs the received data to the signal line 48b. The control circuit 66 uses this signal line 48a.
It is recognized that 1 byte of data has been received by detecting that a pulse has been generated at.

50 is NS on signal line 50a when a pulse occurs on signal line 66b.
It is a circuit that sends out the F signal (see FIG. 10). The NSF signal contains the line number. The value output to the signal line 66a is set to this line number. N
The SF signal transmission circuit 50 generates a pulse on the signal line 50b when the transmission of the NSF signal is completed.

52 is a retransmission request signal (that is, PI in this embodiment).
It is a circuit that sends out (S signal). In other words, the signal line 66c
This is a circuit for sending out a PIS signal (a signal of 462 Hz for 3 seconds) to the signal line 52a when a pulse is generated at. When the transmission of the PIS signal is completed, a pulse is generated on the signal line 52b.

Reference numeral 54 is an adder circuit that inputs the signal of the signal line 50a and the signal of the signal line 52a and outputs the addition result to the signal line 54a.

Reference numeral 56 is a FIFO memory used to demodulate the data sent from the facsimile machine on the other side and store the demodulated data. This FIFO memory is the FIFO memory (1st
2 See 18).

On the other hand, the decoder reads the data stored in this FIFO memory, decodes it, and records it via the double buffer circuit 62. The demodulated data is written in the FIFO memory using the signal lines 66c to 66e. When a (write) pulse is generated on the signal line 66c, the byte data output on the signal line 66e is stored in the address output on the signal line 66d.

Further, the data stored in the FIFO memory is read by the three signal lines 66f, 66g, and 56a. When a (read) pulse is generated on the signal line 66f, the data of the address output on the signal line 66g is output on the signal line 56a. In this embodiment, the address of the FIFO memory is
8400H to AFFH.

Reference numeral 58 is a line number storage memory for storing the latest line number received correctly. When writing a line number in the line number storage memory 58, the line number is output to the signal line 66h and a (write) pulse is generated on the signal line 66i. On the other hand, when reading the latest correctly received line number, when a (read) pulse is generated on the signal line 66j, the correctly received latest line number is output to the signal line 66h.

A decoder 60 reads the demodulated data from the FIFO memory and outputs the decoded data to the signal line 60c. When the preparation for decoding the demodulated 1-byte data is completed, a byte data request pulse is generated on the signal line 60a.
When the pulse is generated, the time control circuit 66 reads out 1 byte of demodulated data from the FIFO memory and outputs the signal line.
Output to 66k. When the decoding of one line is completed, the decoder 60 generates a pulse on the signal line 60b. Then, the decoded data of one line is output to the signal line 60c.

Reference numeral 62 denotes a double buffer circuit for allowing the image signal of the next line to be written in the other buffer memory while recording the image signal in the one buffer.
This buffer is a double buffer of the transmitter (12 in Fig. 12).
(See). The two buffers are called BUF0 (buffer 0) and BUF1 (buffer 1). When the buffer BUF0 is full of image data, it outputs a signal of signal level "1" to the signal line 62a (buffer 0 full). When the image data is not full in the buffer of BUF0, the signal of the signal level "0" is output to the signal line 6a (buffer 0 full).

When the buffer of BUF1 is full of image data, the signal line 62b (buffer 1 full) has a signal level of "1".
The signal of is output. When the buffer of BUF1 is not full of image data, it outputs a signal of signal level "0" to the signal line 62b (buffer 1 full).

The control circuit 66, which will be described later, recognizes that the buffer is empty and specifies in which buffer the data should be written (that is, when the signal line 66m is at the signal level "0", the data is written in the buffer 0). When the signal line 66m is at the signal level "1", the data is written in the buffer 1), and then the recording data is output to the signal line 66n and a (write) pulse is generated on the signal line 66l.

The double buffer circuit 62 sets 1 to the buffer full of the designated buffer.

On the other hand, the recording device 64 generates a recording request pulse on the signal line 64a when the recording of the line data stored in a certain buffer is completed.

Further, the double buffer circuit 62 outputs the recording data to the signal line 62c if the buffer is full of data when the recording request pulse is detected. When all the data in the buffer is output to the recording device 64, the buffer full corresponding to that buffer is dropped. Here, the buffers used are buffer 0, buffer 1, buffer 0, buffer 1
And alternate.

64 is a recording device, and when the preparation for recording is completed, the signal line
A recording request pulse is generated at 64a. Then, the recording data output to the signal line 62c is input and recording is performed.

66 is a control circuit for performing the following control. Reception of the transmission data is processed by the interrupt routine described above, and decoding is processed by the main routine.

In order to receive data, 1-byte data is input every time a pulse is generated on the signal line 48a and stored in the FIFO memory. At this time, the pointer RMDPTR of the modem is sequentially incremented. On the other hand, when the modem pointer RMDPTR reaches the end of the FIFO memory, the modem pointer is set at the end of the FIFO memory. At this time, the REVRS flag is set to 1.

FIG. 18 is a flowchart showing a detailed control procedure relating to reception of demodulated data 8 (that is, interrupt processing).

When a pulse is generated on the signal line 48a, the interrupt process starts (step S600). In steps S602 to S606, demodulated data is input and stored in the FIFO memory.

In step S608, the modem pointer RMDPTR is incremented.

In step S610, it is determined whether or not the pointer of the modem has reached the end of the FIFO memory. If the pointer has reached the end of the FIFO memory, the modem pointer RMDPTR is set to 8400H and the REVRS flag is set to 1.

The main processing contents of the main processing process are the line end code.
It is to search for EOL. The 2 bytes connected to EOL indicate the line number. If the line number is the same as the previous one or is larger by one, it is determined that the image reception is good. At this time, the line number is updated every time a new line number is received. Therefore, when the line number is two or more larger than the last time, it is determined that the image reception is not good.
Then, the NSF signal in which the PIS signal and the retransmission start line number are stored is sent to the transmission side device, and the reception from that line number is performed.

When the image data is correctly received, it is output to the double buffer and recorded every time one line of image data is prepared. Output to the double buffer is performed alternately with buffer 0 and buffer 1.

When the encoder pointer reaches the end of the FIFO, the encoder pointer is set at the beginning of the FIFO. At this time,
Set the REVRS flag to 0.

19 (1) to (4) are detailed flowcharts of the decoding process (main process).

Step S620 to step S630 shown in FIG. 19 (1),
Represents various types of initialization.

In step S620, the pointer RMDPTR of the modem is set to 84.
Set 00H.

In step S622, the encoder pointer RMHPTR
Set 8400H to.

In step S624, 1 is set to the flag BAF (which buffer is currently used to store the recording data).

In step S626, a flag REVRS indicating that the modem pointer has returned from the end of the FIFO to the beginning is set to 0.

In steps S628 to S630, the line number is initialized (set to 0101H).

In steps S632 to S640, it is determined whether EOL is found. If EOL is found, the process proceeds to step S642.

In steps S634 to S638, 1-byte demodulation data is input from the FIFO memory.

In step S640, the encoding pointer is incremented. This will be described later (step S7).
20 to step S734).

In steps S642 to S654, it is determined whether the control decoded signal RTC signal is detected. Step S64
In 2, there is a possibility of RTC signal, that is, EO
It is determined whether or not the byte data following L is 00H. When the image signal is being received, the byte data following the EOL is the high byte data of the line number, so it does not become 00H. If there is a possibility of the RTC signal, it is determined whether the RTC signal is detected in steps S644 to S652. When the RTC signal is detected, the image reception is ended (step S564). Here, the RTC signal is detected, for example, when “EOL” is followed by “1 after 11 consecutive 0s” is detected twice.

In steps S644 to S648, 1-byte demodulation data is input from the FIFO memory.

In step S650, the encoder pointer RMHPTR
Is incremented. Here, if there is no possibility of detecting the RTC signal, that is, the byte data following EOL is 00H.
If not detected, the process proceeds to step S656.

In step S656, 2 bytes of data following the EOL signal,
That is, the line number received this time is input. In steps S658 and S660, the latest correctly received line number is input.

In step S662, it is determined whether or not the line number received this time is two or more greater than the latest correctly received line number, that is, whether an image reception error has occurred. If the line number received this time is greater than the latest correctly received line number by two or more, that is, if an image reception error occurs, step S698.
Proceed to.

If the line number received this time is equal to the latest correctly received line number, or one greater,
That is, if the image reception is good, the process proceeds to step S664.

In steps S664 and S666, the line number received this time is stored in the line number storage memory 58.

In step S668 to step S680 shown in FIG. 19 (2), demodulated data is input and decoded, and one line of recorded data is created.

In steps S668 to S672, 1-byte demodulation data is input from the FIFO memory. Step S674
In, the encoder pointer RMHPTR is incremented.

When the decoder requests byte data (step S676),
1-byte data is sent to the decoder (step S67)
8). Then, in step S680, it is determined whether or not the decoding of one line is completed. If the decoding of one line is not completed yet, the process proceeds to step S668. On the other hand, when the decoding of one line is completed, the process proceeds to step S682.

In step S682, the decoded data of one line is input, the corresponding buffer is selected and output to that buffer (steps S684 to S696). When writing one line of data to the buffer, buffer 0 and buffer 1 are selected alternately. Then, the process proceeds to step S632 to decode the next line.

If the image reception is not good, the process proceeds to step S698 shown in FIG. 19 (3). First, the PIS signal is transmitted (step S69
8 to step S700), the transmission of the transmission side device is interrupted. Then 1 for the latest correctly received line number
The line number added with is set to the NSF signal, and the NSF signal is transmitted (steps S702 to S706). Then, set 8400H to the pointer RMDPTR of the modem, 8400H to the pointer RMHPTR of the encoder, 1 to BAF and 0 to REVRS,
Performs various initializations and receives images again.

Step S720 to Step S734 shown in FIG. 19 (4),
This is a subroutine for incrementing the pointer RMHPTR of the encoder. When incrementing the pointer RMHPTR of the encoder, it is necessary to control so as not to overtake the pointer RMDPTR of the modem (steps S722 to S724).

In step S726, the encoder pointer RMHPTR
Is incremented. If the encoder pointer reaches the end of the FIFO memory, the encoder pointer
Set the start address of FO memory and set REVRS flag to 0
Is set (step S728 to step S732).

If the image reception is not good even when the image is retransmitted a certain number of times or more, fallback or line disconnection is performed.

Also, various timers are operating even while performing control, for example, when the time is over,
The line is disconnected.

Further, in the receiving side device to which the present invention is applied, since the line number is detected, it is possible to correctly recognize how much error has occurred. This makes it possible to analyze the error. For example, the receiving side can correctly identify the case where the errors are scattered all over and occur evenly, and the case where the errors occur in bursts. In this way, it is possible to correctly identify whether to fall back or to disconnect the line when retransmitting.

[Effect]

As described above, according to the present invention, when untransmitted image data that has not been transmitted by the transmitting unit is equal to or less than a predetermined amount and the page end is not detected by the detecting unit, the transmission of the untransmitted image data is prohibited, Even if the amount of untransmitted image data is less than or equal to a predetermined amount, when the end of the page is detected by the detector, the untransmitted image data is transmitted. When the amount of data reaching the trailing end portion is less than or equal to a predetermined amount, the page management on the receiving side becomes complicated when transmitting the next page, but the present invention can easily do this and If there is an error at the beginning, it can be prevented that the page cannot be recorded forever.

[Brief description of drawings]

FIG. 1 is a diagram showing an HDLC frame format, FIG. 2 is a diagram showing a concrete example in which error retransmission is performed using the HDLC frame data shown in FIG. 1, and FIG. 3 is a diagram showing two HDLC frames. , FIG. 4 is a diagram showing an example of HDLC frame transmission when there is a delay in the line, FIGS. 5 (1) to (7) are bit configuration diagrams showing specific examples of line numbers, and FIG. 6 is an encoding diagram. FIG. 7 is a diagram showing an example in which the data and the retransmission start address corresponding to each line number are stored in the memory, FIGS. 7 (1) and 7 (2) are diagrams for explaining the relationship between the FIFO memory and various pointers, and FIG. Figure showing the number of bits and bytes sent in 3 seconds at each transmission speed, Figures 9 (1) and (2) showing the relationship between the FIFO memory and various pointers, and Figure 10 showing transmission from the receiving side The figure which shows an example of the signal of 300b / s for notifying the side of the retransmission start address 11 (1) to (3) are diagrams for explaining a method of setting a retransmission start address, FIG. 12 is a block diagram showing an embodiment of a transmitting side in a facsimile apparatus to which the present invention is applied, and FIG. 13 is a retransmission FIG. 14 is a configuration diagram showing a start address storage memory, FIG. 14 is a flowchart showing an encoding process (that is, main process) of the control circuit 30 shown in FIG. 12, and FIGS. 15 (1) to 15 (9) are shown in FIG. FIG. 16 is a flowchart showing an encoding process (that is, a main process) of the control circuit 30 shown in FIG. 16, and FIG. 16 is a flowchart showing a transmission procedure (that is, an interrupt process) of encoded data controlled by the control circuit 30 shown in FIG. FIG. 17 is a block diagram showing an embodiment of a receiving side in a facsimile apparatus to which the present invention is applied, and FIG. 18 is a demodulated data reception process (that is, an interrupt process) controlled by the control circuit 66 shown in FIG. ) Showing Charts, Fig. 19 (1) to (4) is a flowchart illustrating a decoding process for controlling the control circuit 66 shown in FIG. 17 (i.e., main process). 2 ... NCU, 4 ... hybrid circuit, 6 ... retransmission request signal detection circuit, 8 ... binary signal receiving circuit, 10 ... reading device, 12 ... double buffer circuit, 14 ... line number counter circuit, 16 ... Encoding circuit, 18 ... FIFO memory, 20 ... Retransmission start address storage memory, 22 ... P / S conversion circuit, 24 ... Modulator, 26 ... DCN signal sending circuit, 28 ... Addition circuit , 30 …… control circuit, 40 …… NCU, 42 …… hybrid circuit, 44 …… signal presence / absence detection circuit, 46 …… demodulator, 48 …… S / P conversion circuit, 50 …… NSF signal sending circuit, 52 ...... Retransmission request signal sending circuit, 54 …… Adding circuit, 56 …… FIFO memory, 58 …… Line number storage memory, 60 …… Decoder, 62 …… Double buffer circuit, 64 …… Recording device.

Claims (1)

[Claims] 1. A reading unit for reading an original image, a memory unit for storing image data read by the reading unit, a transmitting unit for transmitting the image data stored in the memory unit, and the transmitted image. Receiving means for receiving an error resending request signal for data, detecting means for detecting the end of the page of the image data stored in the memory means, and reading the image data instructed by the error resending signal from the memory means. The untransmitted image data that has not been transmitted by the transmitting unit is less than a predetermined amount and the end of page is not detected by the detecting unit, the untransmitted image If the end of page is detected by the detection means even if the transmission of data is prohibited and the untransmitted image data is less than the predetermined amount. In this case, the image communication device is characterized by transmitting the untransmitted image data.