JP2566868B2 - Multilayer ceramic wiring board including through holes and method of manufacturing the same - Google Patents

Multilayer ceramic wiring board including through holes and method of manufacturing the same

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Publication number
JP2566868B2
JP2566868B2 JP4162276A JP16227692A JP2566868B2 JP 2566868 B2 JP2566868 B2 JP 2566868B2 JP 4162276 A JP4162276 A JP 4162276A JP 16227692 A JP16227692 A JP 16227692A JP 2566868 B2 JP2566868 B2 JP 2566868B2
Authority
JP
Japan
Prior art keywords
hole
substrate
wiring board
holes
multilayer ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4162276A
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Japanese (ja)
Other versions
JPH07176865A (en
Inventor
清 水島
護 毛利
基晴 宮越
和夫 手取屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikko KK
Original Assignee
Nikko KK
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Publication of JPH07176865A publication Critical patent/JPH07176865A/en
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Publication of JP2566868B2 publication Critical patent/JP2566868B2/en
Anticipated expiration legal-status Critical
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Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、基板両面に設けた絶縁
層によってスルーホールの両端開口部が覆われた構造を
有する多層セラミック配線基板に関する。さらに詳細に
は、スルーホール両端の開口部分が充分な電気的信頼性
を有し、かつ基板両面に設けた絶縁層の該開口部におけ
る凹みが小さく、従って、該両端開口部分によって絶縁
層表面の配線が妨げられずに小形化でき、かつ低コスト
で量産性に優れた多層セラミック配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic wiring board having a structure in which openings at both ends of a through hole are covered with insulating layers provided on both surfaces of the board. More specifically, the openings at both ends of the through-hole have sufficient electrical reliability, and the recesses in the openings of the insulating layer provided on both sides of the substrate are small. The present invention relates to a multilayer ceramic wiring board that can be miniaturized without hindering wiring, has low cost, and is excellent in mass productivity.

【0002】[0002]

【従来技術とその課題】近年、半導体デバイスの小形
化、高性能化が進み、これに伴いセラミック基板上に多
層回路を歩留まり良く、かつ簡単に形成する技術が求め
られている。基板の高密度化の手段として、印刷多層法
やグリーンシート多層法と呼ばれる方法で回路を多層化
した多層セラミック基板が従来用いられている。印刷多
層法とは、絶縁材ペーストをセラミック質基板表面に印
刷し、焼成して絶縁層を形成する方法であり、またグリ
ーンシート多層法とは、回路を印刷したセラミック質の
未焼成シートを多数積層し焼成して絶縁層を形成する方
法である。
2. Description of the Related Art In recent years, semiconductor devices have become smaller and higher in performance, and accordingly, a technique for forming a multilayer circuit on a ceramic substrate with a high yield and in a simple manner is required. As a means for increasing the density of a substrate, a multilayer ceramic substrate in which circuits are multilayered by a method called a printing multilayer method or a green sheet multilayer method has been conventionally used. The printing multilayer method is a method of printing an insulating material paste on the surface of a ceramic substrate and firing it to form an insulating layer.The green sheet multilayer method is a method of printing a large number of unfired ceramic sheets on which circuits are printed. It is a method of forming an insulating layer by stacking and firing.

【0003】上記印刷多層法では、基板両側を電気的に
層間接続するためにスルーホールを設けた基板を用いて
いる。ところが印刷時に絶縁材ペーストがスルーホール
に流れ込むためにスルーホールの開口部を避けて印刷し
なければならず、配線が制限される問題がある。また、
従来のグリーンシート多層法は、未焼成シートを多数積
層して焼成するため、寸法精度の頼性が低い問題があ
る。
In the above-mentioned printed multi-layer method, a substrate provided with through holes is used to electrically connect the both sides of the substrate to each other. However, since the insulating material paste flows into the through holes during printing, it is necessary to print while avoiding the openings of the through holes, and there is a problem that wiring is restricted. Also,
The conventional green sheet multilayer method has a problem that the reliability of dimensional accuracy is low because a large number of unfired sheets are laminated and fired.

【0004】このような従来のグリーンシート多層法に
対して、米国特許第4,645,552 号において、予め焼成し
たセラミック基板を用い、これにグリーンシートを積層
し、焼成して絶縁層を形成する方法が提唱されている。
この方法は、焼成した基板を用いるので製品の寸法精度
に優れ、また焼成工程と通じて強度が大きく、熱伝導性
が良く、製品を低コストで製造できる利点がある。但
し、現状の方法は、スルーホールを有する基板を使用す
る場合には基板のスルーホール部分に次のような欠陥が
生じ易い。即ち、スルーホールの両端開口を塞ぐように
グリーンシートを基板表面全体に積層すると、グリーン
シートによって基板のスルーホールが密封され、焼成時
の冷却過程でスルーホールが減圧状態になるために、半
溶融状態のセラミックシートがスルーホールの開口部に
引き込まれ、この部分に凹みを生じ、またスルーホール
開口部分のグリーンシートに微細亀裂(マイクロクラッ
ク)が発生する場合が暫々ある。亀裂が発生するとスル
ーホール開口部分の絶縁層の凹みは小さくなるが、絶縁
層表面に回路パターンを印刷した場合に亀裂の部分で回
路パターンを形成する導体ペーストが流れ、電気的な接
続不良や短絡を生じる虞がある。
In contrast to such a conventional green sheet multi-layer method, US Pat. No. 4,645,552 proposes a method in which a ceramic substrate which has been fired in advance is used, a green sheet is laminated on the substrate and fired to form an insulating layer. Has been done.
Since this method uses a fired substrate, it has excellent dimensional accuracy of the product, has high strength through the firing process, has good thermal conductivity, and has the advantage that the product can be manufactured at low cost. However, according to the current method, when a substrate having a through hole is used, the following defects are likely to occur in the through hole portion of the substrate. That is, if a green sheet is laminated on the entire surface of the substrate so as to close the openings at both ends of the through hole, the through hole of the substrate is sealed by the green sheet, and the through hole is depressurized during the cooling process during firing. The ceramic sheet in the state is drawn into the opening of the through hole, a dent is formed in this portion, and there is a case in which fine cracks (microcracks) occur in the green sheet in the opening of the through hole. When a crack occurs, the recess of the insulating layer at the opening of the through hole becomes smaller, but when a circuit pattern is printed on the surface of the insulating layer, the conductor paste that forms the circuit pattern flows at the cracked portion, causing a poor electrical connection or short circuit. May occur.

【0005】そこで、焼成時にスルーホールが減圧状態
にならないように、スルーホールの片側開口部分のグリ
ーンシートを穿孔して気密状態を解除している。ところ
が、グリーンシートにこの穿孔加工を施すのはコスト高
になり、また孔明け部分には回路の配線を印刷できない
ので、回路構成が制約される問題がある。
Therefore, in order to prevent the through hole from being in a depressurized state during firing, the green sheet at the opening on one side of the through hole is punched to release the airtight state. However, it is costly to perform the perforating process on the green sheet, and since the circuit wiring cannot be printed on the perforated portion, there is a problem that the circuit configuration is restricted.

【0006】本発明は、従来の多層セラミック回路基板
における前述の問題を解決した回路基板を提供すること
を目的とする。本発明者等は、製造プロセスと電気的信
頼性の点からスルーホールの孔径とセラミック質絶縁層
の凹み量との相関および電気的信頼性を検討した結果、
スルーホール開口部の凹みが小さく、かつマイクロクラ
ックのない絶縁層を有する基板を容易に製造できる知見
を得て、本発明を完成した。
An object of the present invention is to provide a circuit board which solves the above-mentioned problems in the conventional multilayer ceramic circuit board. The present inventors have examined the correlation and electrical reliability between the hole diameter of the through hole and the amount of depression of the ceramic insulating layer from the viewpoint of the manufacturing process and electrical reliability,
The present invention has been completed based on the knowledge that a substrate having an insulating layer having a small through-hole opening and having no microcracks can be easily manufactured.

【0007】[0007]

【課題の解決手段】本発明によれば、内層配線が非充填
スルーホールによって層間接続されている多層セラミッ
ク配線基板において、スルーホールの両端開口部が該基
板両面に設けた平坦な絶縁層によって直接覆われている
ことを特徴とする多層セラミック配線基板が提供され
る。なお、本明細書において、「平坦な絶縁層」とは、
導体印刷が可能な程度に平坦で、かつマイクロクラック
等に起因する絶縁不良が実質的に存在しない絶縁層をい
う。
According to the present invention, in a multilayer ceramic wiring substrate in which inner layer wirings are interconnected by non-filling through holes, the openings at both ends of the through holes are the bases.
Provided is a multilayer ceramic wiring board which is directly covered by flat insulating layers provided on both sides of the board . In the present specification, the “flat insulating layer” means
Flat enough to allow conductor printing and microcracks
Insulation layer that does not substantially have insulation failure due to
U.

【0008】また、その好適な態様として、スルーホー
ルの孔径が0.25mm以下である多層セラミック配線
基板が提供される。さらに、非充填スルーホールを有す
るセラミック基板上に、スルーホールの開口部が覆われ
るようにセラミック質のグリーンートを積層する工程、
該グリーンシートをスルーホール径により決定される積
層圧力の下に基板に熱圧着する工程、および該基板上の
グリーンシートを焼成する工程を含むことを特徴とす
る、スルーホールの両端開口部が該基板両面に設けた平
坦な絶縁層によって直接覆われている前記多層セラミッ
ク配線基板の製造方法が提供される。
As a preferred embodiment, there is provided a multilayer ceramic wiring board having through holes with a diameter of 0.25 mm or less. In addition, it has an unfilled through hole
The through-hole opening is covered on the ceramic substrate.
The process of laminating ceramic greens,
The product of the green sheet determined by the through hole diameter
Thermocompression bonding to the substrate under layer pressure, and on the substrate
Characterized by including a step of firing the green sheet
The openings at both ends of the through hole are flat on both sides of the board.
Said multi-layer ceramic covered directly by a flat insulating layer
A method for manufacturing a wiring board is provided.

【0009】以下、本発明を詳細に説明する。本発明に
は、スルーホールを有するセラミック質の基板が用いら
れる。通常、0.635 mm厚のアルミナ基板に厚さ 0.1〜0.
2mm 程度のガラス質セラミックグリーンシートを積層す
る場合には、孔径が0.3mm 以下、好ましくは0.15〜0.25
mmのスルーホールを有するアルミナ基板が用いられる。
スルーホールの孔径が0.3mm よりも大きいと、スルーホ
ール開口部のセラミック質絶縁層にマイクロクラックが
生じ易くなる。一般的には、0.15〜0.25mm孔径のとき、
セラミック層の凹みも小さく、かつマイクロクラックも
生じない。一方、スルーホールの孔径が0.1mm より小さ
いと、セラミック層の凹みは生じないがアルミナ基板の
製造が困難になり、またスルーホール部の導体印刷も困
難になる。
The present invention will be described in detail below. A ceramic substrate having through holes is used in the present invention. Normally, the thickness is 0.1 to 0 on a 0.635 mm thick alumina substrate.
When laminating glass ceramic green sheets of about 2 mm, the hole diameter should be 0.3 mm or less, preferably 0.15 to 0.25.
An alumina substrate with mm through holes is used.
If the diameter of the through hole is larger than 0.3 mm, microcracks are likely to occur in the ceramic insulating layer at the opening of the through hole. Generally, when the hole diameter is 0.15 to 0.25 mm,
The depression of the ceramic layer is also small, and no microcracks are generated. On the other hand, when the diameter of the through hole is smaller than 0.1 mm, the ceramic layer is not dented, but it is difficult to manufacture the alumina substrate and it is also difficult to print the conductor in the through hole portion.

【0010】なお、グリーンシートの厚さが増すのに比
例してスルーホール開口部でのマイクロクラックは発生
し難くなる。また、同様に、焼成時のセラミック層の粘
性が高いほどスルーホール部分への凹み量は小さい。従
って、アルミナ基板のスルーホールの孔径に応じてガラ
ス質セラミックグリーンシートの厚さおよび組成が選択
される。また、積層圧力を高くすると、セラミック層の
凹み量は小さくなり、次第に平衡となる。また凹み形状
も、積層圧力が低いと底が突き出した形状になるが、積
層圧力が高いと、底が平な形状になる。これはグリーン
シートが剪断応力を受けてマイクロクラックが発生し、
焼成および冷却の際にこのクラックを通じて空気が出入
りするためであると考えられる。従って、積層圧力はセ
ラミック層の凹み量が小さく、かつマイクロクラックを
生じない大きさが選択される。
Incidentally, as the thickness of the green sheet increases, microcracks are less likely to occur at the through hole openings. Similarly, the higher the viscosity of the ceramic layer during firing, the smaller the amount of depression in the through hole portion. Therefore, the thickness and composition of the vitreous ceramic green sheet are selected according to the diameter of the through hole of the alumina substrate. Moreover, when the stacking pressure is increased, the amount of depression of the ceramic layer is reduced, and the equilibrium is gradually achieved. Also, the recessed shape has a shape in which the bottom protrudes when the lamination pressure is low, but the bottom has a flat shape when the lamination pressure is high. This is because the green sheet receives shear stress and microcracks occur,
It is considered that this is because air enters and leaves through the cracks during firing and cooling. Therefore, the lamination pressure is selected so that the amount of depression of the ceramic layer is small and no microcracks are generated.

【0011】グリーンシートの焼成、冷却後、該グリー
ンシートによって形成されたセラミック質絶縁層の表面
に導体パターンが印刷され、所定の回路が形成される。
該回路には必要に応じて、抵抗、コンデンサーなどが組
み込まれ、該回路表面にはオーバーコートガラスが被せ
られる。この一連の工程を繰り返して多層回路が形成さ
れる。
After firing and cooling the green sheet, a conductor pattern is printed on the surface of the ceramic insulating layer formed by the green sheet to form a predetermined circuit.
A resistor, a capacitor and the like are incorporated in the circuit as needed, and the surface of the circuit is covered with overcoat glass. This series of steps is repeated to form a multilayer circuit.

【0012】以下に、本発明の実施例を比較例と共に示
す。なお、本実施例は例示であり本発明を限定するもの
ではない。
Examples of the present invention will be shown below together with comparative examples. It should be noted that the present embodiment is an example and does not limit the present invention.

【0013】実施例1 スルーホール(孔径 0.2mmφおよび 0.3mmφ)を中心と
して0.2 インチ角の電極を形成したアルミナ基板(82mm
×82mm、厚さ630 μm )を用い、ガラスセラミック質グ
リーンシート(厚さ: 未焼成120 μm 、焼成後65μm:デ
ュポン社製商品名852AT )を上記アルミナ基板の両面に
積層し、75℃の温度下で、各々20、40、60、8
0、100kg/cm2 の圧力で2分間押圧した後に、大気
中、60分の時間内で、850℃で10分間、焼成し
た。その後、冷却してアルミナ基板の表面にガラスセラ
ミック質の絶縁層を形成した。この基板について触針型
膜厚計を用い、積層圧力とスルーホール開口部における
絶縁層の凹み量を測定した。この結果を表1および図1
に示す。表1および図1に示すように、孔径 0.3mmφの
スルーホールを有する基板は、積層圧力が40kg/cm2
を上回ると絶縁層の凹み量が急激に減少し、凹部の底が
平らな形状になるが、これは積層圧力が増加するのに伴
い、凹み部分にマイクロクラックが発生し、ここを通じ
てスルーホールに空気が出入りするために減圧による吸
引力が低下するためである。また、孔径 0.2mmφのスル
ーホールを有する基板では、積層圧力が80kg/cm2
では絶縁層の凹み量の変化は小さく、マイクロクラック
は生じていない。しかし積層圧力が100Kg/cm2 を上
回ると凹み量は小さいがマイクロクラックが認められ
た。従って、本実施例の条件では、孔径 0.3mmφのスル
ーホールを有する基板については積層圧力40kg/cm2
以下、孔径 0.2mmφのスルーホールを有する基板につい
ては積層圧力80kg/cm2 以下が適当である。
Example 1 Alumina substrate (82 mm) having electrodes of 0.2 inch square centered on through holes (hole diameters of 0.2 mmφ and 0.3 mmφ)
× 82 mm, thickness 630 μm), glass-ceramic green sheets (thickness: unfired 120 μm, fired 65 μm: DuPont's trade name 852AT) are laminated on both sides of the above alumina substrate, and the temperature is 75 ° C. Below, 20, 40, 60, 8 respectively
After pressing with a pressure of 0,100 kg / cm 2 for 2 minutes, it was fired in the atmosphere for 60 minutes at 850 ° C. for 10 minutes. After that, it was cooled to form a glass ceramic insulating layer on the surface of the alumina substrate. With respect to this substrate, the stacking pressure and the amount of depression of the insulating layer at the opening of the through hole were measured using a stylus type film thickness meter. The results are shown in Table 1 and FIG.
Shown in As shown in Table 1 and FIG. 1, the substrate having a through hole with a hole diameter of 0.3 mmφ has a lamination pressure of 40 kg / cm 2
When it exceeds the value, the depth of the recess in the insulating layer decreases sharply and the bottom of the recess becomes flat, but as the stacking pressure increases, microcracks occur in the recess, and through this there is a through-hole. This is because the suction force due to the reduced pressure is reduced because air flows in and out. Further, in a substrate having a through hole with a hole diameter of 0.2 mmφ, the change in the amount of depression of the insulating layer was small and the microcracks did not occur up to a stacking pressure of 80 kg / cm 2 . However, when the stacking pressure exceeded 100 kg / cm 2 , microcracks were recognized although the amount of depression was small. Therefore, under the conditions of this embodiment, a substrate having a through hole having a hole diameter of 0.3 mmφ has a lamination pressure of 40 kg / cm 2
For a substrate having through holes with a hole diameter of 0.2 mmφ, a lamination pressure of 80 kg / cm 2 or less is suitable.

【0014】[0014]

【表1】 [Table 1]

【0015】実施例2 スルーホール径0.20mmφ、0.24mmφのアルミナ基板と、
スルーホールを全く設けないアルミナ基板とを用い、積
層圧力を45Kg/cm2 とした他は実施例1と同一条件に
従って多層基板を製造し、片面に対向電極として0.2 イ
ンチ角の表層電極を形成した。各スルホール径について
144 個の試料について層間絶縁抵抗値(DC100V:1分間
印加)を測定したところ全て10MΩ以上であった。ま
た各スルホール径についておのおの数十個の試料を、8
5℃、85%RHの条件下で対向電極間に25vの直流電
圧を各々100 、200 、500 時間印加し、各時間経過後の
層間絶縁抵抗値(DC1kV :1分間印加)を測定した。こ
の結果を表2および図2に示す。この結果から明らかな
ように、本実施例の多層配線基板のスルーホール開口部
はスルーホールを設けない場合と殆ど同程度の層間絶縁
抵抗を有し、電気的接続の信頼性が高い。
Example 2 An alumina substrate having through-hole diameters of 0.20 mmφ and 0.24 mmφ,
A multilayer substrate was manufactured according to the same conditions as in Example 1 except that an alumina substrate having no through holes was used and the laminating pressure was 45 kg / cm 2 , and a 0.2-inch square surface layer electrode was formed on one side as a counter electrode. . About each through hole diameter
When the interlayer insulation resistance values (DC 100 V: applied for 1 minute) of the 144 samples were measured, all were 10 MΩ or more. In addition, dozens of samples for each through hole diameter
A DC voltage of 25 V was applied between the opposed electrodes under conditions of 5 ° C. and 85% RH for 100, 200, and 500 hours, respectively, and the interlayer insulation resistance value (DC1 kV: applied for 1 minute) after each time was measured. The results are shown in Table 2 and FIG. As is clear from this result, the through hole opening of the multilayer wiring board of this embodiment has almost the same level of interlayer insulation resistance as when the through hole is not provided, and the reliability of electrical connection is high.

【0016】[0016]

【表2】 [Table 2]

【0017】比較例 スルーホールの孔径が0.5 mmφ、0.4 mmφおよび0.3 mm
φである以外は実施例2と同一のグリーンシートを用
い、実施例2と同一の条件で多層基板を製造し、層間絶
縁抵抗値を測定した。0.5 mmφおよび0.4 mmφの試料は
全て、肉眼観察でビア孔の絶縁層の凹部周縁に多数のマ
イクロクラックが認められ、表面に導体ペーストを印刷
したところマイクロクラックに導体ペーストが流れ込
み、層間絶縁抵抗は数Ωであり、絶縁基板として用いる
ことができなかった。同様に、0.3 mmφの試料は、その
約1割が層間抵抗値10MΩ以下であり、絶縁不良であ
った。
Comparative Example Through-hole diameters of 0.5 mmφ, 0.4 mmφ and 0.3 mm
A multilayer substrate was manufactured under the same conditions as in Example 2 using the same green sheet as in Example 2 except for φ, and the interlayer insulation resistance value was measured. For all 0.5 mmφ and 0.4 mmφ samples, a large number of microcracks were observed on the periphery of the concave part of the insulating layer of the via hole by visual observation, and when the conductor paste was printed on the surface, the conductor paste flowed into the microcracks and the interlayer insulation resistance was It was several Ω and could not be used as an insulating substrate. Similarly, about 10% of the 0.3 mmφ sample had an interlayer resistance value of 10 MΩ or less, indicating poor insulation.

【0018】[0018]

【発明の効果】本発明の多層セラミック配線基板は、絶
縁層のスルーホール開口部でのマイクロクラックがな
く、スルーホール部分での電気的接続の信頼性が高く、
また絶縁層表面の回路配線も凹み部分での制約を殆ど受
けないので、回路の構成が容易である。さらに、本発明
の多層セラミック配線基板は、その製造が容易であり、
信頼性の高い製品を容易に得ることができる。
The multilayer ceramic wiring board of the present invention has no microcracks at the through hole openings of the insulating layer and has high reliability of electrical connection at the through holes.
Further, the circuit wiring on the surface of the insulating layer is hardly restricted by the recessed portion, so that the circuit configuration is easy. Further, the multilayer ceramic wiring board of the present invention is easy to manufacture,
A reliable product can be easily obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例1におけるグリーンシートの
積層圧力と凹み量(焼成後の平均値)の関係を示すグラ
フ。
FIG. 1 is a graph showing a relationship between a stacking pressure of a green sheet and an amount of dents (average value after firing) in Example 1 of the present invention.

【図2】 本発明の実施例における層間絶縁抵抗値の印
加時間に対する変化を示すグラフ。
FIG. 2 is a graph showing a change of an interlayer insulation resistance value with respect to an application time in an example of the present invention.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 手取屋 和夫 石川県松任市相木町383番地 ニッコー 株式会社内 (56)参考文献 特開 平3−261196(JP,A) 特開 平3−259596(JP,A) 特開 昭60−47495(JP,A) 特開 昭63−156393(JP,A) 実開 昭62−174373(JP,U) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Tetoriya 383 Aikimachi, Matsuto-shi, Ishikawa Nikko Co., Ltd. (56) References JP-A-3-261196 (JP, A) JP-A-3-259596 ( JP, A) JP 60-47495 (JP, A) JP 63-156393 (JP, A) Actual development 62-174373 (JP, U)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 内層配線が非充填スルーホールによって
層間接続されている多層セラミック配線基板において、
スルーホールの両端開口部が該基板両面に設けた平坦な
絶縁層によって直接覆われていることを特徴とする多層
セラミック配線基板。
1. A multilayer ceramic wiring board in which inner layer wirings are interconnected by non-filling through holes,
The openings at both ends of the through hole are flat on both sides of the board.
A multilayer ceramic wiring board which is directly covered with an insulating layer .
【請求項2】 スルーホールの孔径が 0.25mm 以下であ
る請求項1の多層セラミック配線基板。
2. The multilayer ceramic wiring board according to claim 1, wherein the through hole has a hole diameter of 0.25 mm or less.
【請求項3】 非充填スルーホールを有するセラミック
基板上に、スルーホールの開口部が覆われるようにセラ
ミック質のグリーンートを積層する工程、該グリーンシ
ートをスルーホール径により決定される積層圧力の下に
基板に熱圧着する工程、および該基板上のグリーンシー
トを焼成する工程を含むことを特徴とする、請求項1ま
たは2に記載の多層セラミック配線基板の製造方法。
3. A ceramic having unfilled through holes.
On the board, cover the through hole opening with a ceramic
The process of laminating Mick green rust,
Under the stacking pressure determined by the through hole diameter
The process of thermocompression bonding to the substrate and the green sheet on the substrate
The method according to claim 1, further comprising a step of firing the toast.
Or a method for manufacturing a multilayer ceramic wiring board according to item 2.
JP4162276A 1992-05-28 1992-05-28 Multilayer ceramic wiring board including through holes and method of manufacturing the same Expired - Lifetime JP2566868B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4162276A JP2566868B2 (en) 1992-05-28 1992-05-28 Multilayer ceramic wiring board including through holes and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4162276A JP2566868B2 (en) 1992-05-28 1992-05-28 Multilayer ceramic wiring board including through holes and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH07176865A JPH07176865A (en) 1995-07-14
JP2566868B2 true JP2566868B2 (en) 1996-12-25

Family

ID=15751399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4162276A Expired - Lifetime JP2566868B2 (en) 1992-05-28 1992-05-28 Multilayer ceramic wiring board including through holes and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2566868B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5285719B2 (en) * 2011-01-28 2013-09-11 アンリツ株式会社 High-frequency connection wiring board and optical modulator module having the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047495A (en) * 1983-08-25 1985-03-14 株式会社日立製作所 Ceramic circuit board
JPS62174373U (en) * 1986-04-25 1987-11-05
JPS63156393A (en) * 1986-12-19 1988-06-29 松下電器産業株式会社 Manufacture of ceramic multilayer circuit board
JPH03259596A (en) * 1990-03-09 1991-11-19 Matsushita Electric Ind Co Ltd Multilayer interconnection board and its manufacture
JPH03261196A (en) * 1990-03-12 1991-11-21 Matsushita Electric Ind Co Ltd Multilayer wiring board and fabrication thereof

Also Published As

Publication number Publication date
JPH07176865A (en) 1995-07-14

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