JP2565262B2 - Image defect correction device for solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, the present invention will be described in the following order.

A Industrial Field B Outline of the Invention C Prior Art D Problems to be Solved by the Invention E Means for Solving Problems F Action G Example G ₁ Configuration of Video Camera to which the Present Invention is Applied (No. (Figs. 1 and 2) G ₂ CCD image sensor defect test (Fig. 3) G ₃ memory map (Fig. 4) G ₄ Correction signal generation circuit and its peripheral circuits (Example 5)
Figure) G ₅ correcting operation (Figure 6, Figure 7, Figure 8) FIELD The present invention on the effect A industry H invention, a charge coupled device (CCD: Charge Coupled Devic
The image defect correction device for a solid-state imaging device, which corrects the image quality deterioration due to the imaging output from the defective pixel included in the solid-state imaging device such as e) by signal processing, and particularly, the position of the defective pixel included in the solid-state imaging device and The data about the defect component level included in the output signal is read from the storage means, the defect correction signal is formed at the timing of the output signal of the defective pixel among the output signals of the solid-state image sensor, and the output of the solid-state image sensor is output. The present invention relates to an image defect correction device for a solid-state imaging device that corrects a defect by adding it to a signal.

B Outline of the Invention The present invention reads data about the position of a defective pixel included in a solid-state image sensor such as a CCD and the defect component level included in the output signal from the storage unit, and outputs the data from the output signal of the solid-state image sensor. In a solid-state image pickup device image defect correction apparatus for performing defect correction by forming a defect correction signal at the timing of the output signal of the defective pixel and adding it to the output signal of the solid-state image pickup device, as position data of the defective pixel, The relative distance between defective pixels is encoded and used, and the position of each defective pixel can be efficiently determined by setting a dummy defective pixel when the relative distance between the defective pixels is large. .

C Conventional technology In general, in a solid-state imaging device formed of a semiconductor such as a CCD, a defective pixel in which a constant bias voltage is always added to an imaging output corresponding to the amount of incident light due to a local crystal defect of the semiconductor or the like. It is known that the image quality is deteriorated due to the imaging output from the defective pixel. The image defect in which a constant bias voltage is always added to the image pickup output is called a white defect because it appears as a high-luminance spot on the monitor screen if the image defect signal is processed as it is.

Conventionally, in order to correct the image quality deterioration due to the imaging output from the defective pixel included in the solid-state image sensor as described above by signal processing, for example, information indicating the presence or absence of a defect for each pixel of the solid-state image sensor is stored in a memory Then, based on the information in the memory, instead of the imaging output from the defective pixel, the signal interpolated by the imaging output obtained from the pixel adjacent to the defective pixel is used. Incidentally, in order to store the information indicating the presence or absence of a defect for each pixel of the solid-state image sensor in the memory in this way, since a memory having a huge storage capacity corresponding to the total number of pixels of the solid-state image sensor has to be used, The applicant of the present application, instead of sequentially storing the presence or absence of a defect for each pixel, as the data indicating the position of the defective pixel included in the solid-state imaging device, by encoding the distance between the defective pixels and storing it in the memory, We have previously proposed a technology to reduce the storage capacity (see Japanese Patent Publication No. 60-34872).

Further, conventionally, in the correction processing by the above interpolation, a large correction error occurs unless the image pickup outputs obtained in the pixels in the vicinity of the defective pixel have a correlation. Therefore, the position of the defective pixel included in the solid-state image sensor and its Data about the defect component level included in the output signal is stored in a memory, and the defect correction signal is output at the timing of the output signal of the defective pixel among the output signals of the solid-state imaging device based on the data read from the memory. An image defect correction device for a solid-state image pickup device has also been proposed in which a defect is corrected by forming a signal and adding it to the output signal of the solid-state image pickup device (see JP-A-60-513780).

D Problems to be Solved by the Invention As described above, the data about the position of the defective pixel included in the solid-state image sensor and the defect component level included in the output signal thereof is stored in the memory, and the data read from the memory is stored. If the defect correction is performed based on the above, it becomes possible to perform the defect correction satisfactorily without any correction error. However, the data about the position of the defective pixel and the defect component level included in the output signal There is a problem that the amount of data stored in the memory increases. In particular, if the position of each defective pixel is indicated by an absolute address, the number of bits of the position data of each defective pixel can be increased when using a solid-state image sensor that increases the number of pixels to obtain high image resolution. Is increased, and the storage capacity of the memory becomes a problem.

Therefore, in view of the above conventional problems, the present invention is
The position of the defective pixel included in the solid-state image sensor is efficiently represented by position data having a relatively small number of bits, the storage unit and its peripheral circuits are simplified, and the image defect correction process is efficiently performed. An image defect correction device for a solid-state image pickup device having a novel structure capable of obtaining an image pickup output signal with good image quality.

E Means for Solving Problems In order to solve the above-mentioned conventional problems, the image defect correcting device for a solid-state image pickup device according to the present invention has a position of a defective pixel included in a solid-state image pickup device and an output signal thereof. And a storage unit storing data on a defect component level included in the storage unit, and a defect correction signal is generated at the timing of the output signal of the defective pixel among the output signals of the solid-state imaging device based on the data read from the storage unit. Correction signal generating means, and a correction means for performing defect correction by synthesizing a defect correction signal generated by the correction signal generating means with an output signal of the solid-state image sensor, and as the position data of the defective pixel,
Other defect positions except the first defect position A _o counted from the reference point
A _n (n is an arbitrary integer) encodes the distance from the preceding defect position A _n-1 and stores it in the storage means.
If the relative distance from any defective pixel to the next defective pixel is large, set a dummy defective pixel between those pixels,
It is characterized in that the data is stored in the storage means.

F action In the image defect correction device for a solid-state imaging device according to the present invention,
As the position data of the defective pixel, other defect positions A _n (n is an arbitrary integer) excluding the first defect position A _o counted from the reference point are the distances from the immediately preceding defect position A _n-1. The converted relative address data is stored in the storage means. When the relative distance from any defective pixel to the next defective pixel is large, dummy defective pixels are set between the pixels and the data is stored in the storage means. In this way, by indicating the position of each defective pixel by the relative address, 1
The amount of data required to indicate the position of one defective pixel is reduced. Furthermore, by setting a dummy defective pixel,
The maximum value of the relative distance between the defective pixels, that is, the maximum value of the relative address becomes a small value.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Embodiment shown in the block diagram of a configuration Figure 1 in G ₁ camcorder, red (R) imaging light by the imaging optical system 1, green (G), and object image color-separated into three primary components of blue (B) The present invention is applied to a color video camera that performs color imaging using a three-plate imaging unit 2 including three solid-state image sensors formed on an imaging surface.

In this embodiment, as a solid-state image sensor constituting the imaging unit 2, for example, as shown in FIG.
A large number of light receiving sections S corresponding to pixels arranged in a matrix, a vertical transfer register section VR provided along one side of each light receiving section S in the vertical direction, and a vertical transfer register section
The horizontal transfer register section HR is provided at each terminal side of VR, and the signal charges corresponding to the amount of received light obtained in each light receiving section S correspond to each vertical line for each field period or each frame period. The signal charges are transferred to each vertical transfer register unit VR, the signal charges are transferred to the horizontal transfer register unit HR through the vertical transfer register units VR, and the signal charges for each horizontal line are output from the horizontal transfer register unit HR as an imaging output. Three interline transfer type CCD image sensors 2R, 2G, 2B that are taken out are used.

The drive circuit 3 of the image pickup section 2 is supplied with a vertical transfer pulse φ _V and a horizontal transfer pulse φ _H from the timing generator 5 in synchronization with the synchronization signal SYNC given by the sync generator 4 shown in FIG. , Above CCD
A field read mode in which all signal charges corresponding to the amount of received light obtained in each light receiving unit S of the image sensors 2R, 2G, and 2B are read out during one field period, and the signal charges obtained in each of the light receiving units S are all read out in one frame period. A read mode designation signal for designating a frame read mode to be read,
A shutter control signal and the like for controlling the charge accumulation time of the CCD image sensors 2R, 2G and 2B to control the so-called electronic shutter speed are supplied from the system controller 6.

Here, the CCD image sensor 2 constituting the imaging unit 2
R, 2G, 2B, the charge storage amount is 1/2 of the frame read mode in the field read mode where the charge storage time is 1/6 second, as opposed to the frame read mode that has 1/30 second charge storage time. Therefore, by adding and reading the signal charges obtained by the two light receiving portions S adjacent in the vertical direction, the sensitivity is made equal to that in the frame reading mode.

The RGB three-channel color imaging outputs (S _R ), (S _G ), and (S _B ) obtained by the imaging unit 2 configured by the three CCD image sensors 2R, 2G, and 2B are output from the preamplifier 7. After being supplied to the signal processing system 9 via the correction signal adding circuit 8 and subjected to the defect correction processing by the correction signal adding circuit 8, the signal processing system 9 performs the process processing together with the gamma correction and the shading correction. A video signal (S) conforming to a specified standard television system standardized by the CCIR (International Advisory Committee on Radio Communications) and EIA (Electronic Industries Association of America)
_OUT ) and output.

In this embodiment, the CCD image sensors 2R, 2R
For G and 2B, a defect test for analyzing the position of the defective pixel, the type of the defect, the level of the defect, etc. is performed in advance, and these data are stored in the memory 10 as correction data. Based on the correction data read from the memory 10, the white defect correction signal (W _CP ), the black defect correction signal (B _CP ), the white defect correction signal is output at the timing of the output signal of the defective pixel of the CCD image sensor 2R, 2G, 2B. Shading correction signals (W _SH ), black shading correction signals (B _SH ), etc. are formed and these correction signals (W _CP ), (B _CP ), (W _CP ),
_SH ) and (B _SH ) are supplied to the correction signal addition circuit 8 and the signal processing system 9 via the correction signal switching circuit 12 so that the correction signal addition circuit 8 and the signal processing system 9 have image defects. Is to be corrected.

Further, the imaging unit 2 is provided with a temperature sensor 13, which detects the temperatures of the CCD image sensors 2R, 2G, and 2B, and corrects each correction signal for white defect and black shading whose temperature depends on the defect level. Temperature correction processing is performed on (W _CP ) and (B _SH ) by temperature correction circuits 14 and 15 based on the detection output of the temperature sensor 12, respectively.
The temperatures of the CCD image sensors 2R, 2G, and 2B indicated by the detection output of the temperature sensor 13 are digitized by an analog / digital (A / D) converter 16 and supplied to the memory 10 as address data. Have been.

Defect Test of G ₂ CCD Image Sensor The defect test for the CCD image sensors 2R, 2G, and 2B is performed at a test temperature higher than room temperature where image defects easily appear. In the defect test, for example, as shown in FIG. 3, the positions A ₁ , A _2, ... Of white defect pixels and black defect pixels of the CCD image sensors 2R, 2G, 2B are confirmed. , The type of the defect and the levels l ₁ , l ₂ ..., And the position data of each defective pixel is obtained as follows. That is, counted from the reference point A ₀ represents at first defective pixel position A ₁ is of a predetermined bit encodes the distance d ₁ from the reference point A ₀ digital data, and other defective pixel position A _n ( n is an arbitrary integer) is the previous defective pixel position A
The distance d _n from _n-1 is encoded and represented by digital data of predetermined bits, and further, the first defective pixel position A ₁ and the second defective pixel position whose relative distance is d in the example of FIG. If the relative distance from any defective pixel to the next defective pixel is too large to be represented by the digital data of the predetermined bit, such as the dummy defective pixel position A _DM1 between A ₂ and them, A dummy defective pixel is set between the defective pixels, and the relative distance d is calculated from the distance d ₂ from the first defective pixel position A ₁ to the dummy defective pixel position A _DM1 and the dummy defective pixel position A _DM1. Distance to _second defective pixel position A ₂
It is divided into d ₃ and represented by digital data of the above predetermined bits.

Here, when the positions A ₁ , A ₂ ... Of the defective pixels of the CCD image sensors 2R, 2G, 2B are represented by two-dimensional absolute addresses, for example, 10 bits in the horizontal direction and 10 bits in the vertical direction Although a total of 20 bits of address data are required, the defective pixel position _An (n is an arbitrary integer) is encoded as the distance d _n from the previous defective pixel position _An-1 as described above. By employing a relative address represented by digital data of predetermined bits, the address data can be compressed to the number of bits necessary to represent the maximum value of the relative address. 8-bit data compression is performed for the position of one defective pixel.
The relative distance that can be represented by the 12-bit relative address data is, for example, a maximum of 4.5 lines, and the relative distance from one defective pixel position _An to the next defective pixel position _{An + 1.}
If d _n is more than 4.5 lines away, the relative distance d
by dividing the _n to be within 4.5 lines, the defective pixel position A _n, by setting the A _{n + 1} 1 single or a plurality of dummy defective pixel position A _DM between, 12 relative address bits The defective pixel position _{An + 1} can be represented by the data.
Thus, if it can not be represented in the relative distance d _n is the predetermined bit too large digital data from any defective pixel position A _n up to the next defective pixel position A _{n + 1,} between those of the defective pixel And set the relative distance d _n
, All defective pixel positions can be represented by digital data of a predetermined bit.
The dummy defective pixel position A _DM1 may adversely affect the quality of the imaging output signal by setting it within the blanking period BLK of the imaging output signal read from the CCD image sensor 2R, 2G, 2B. There can be no.

G ₃ Memory Map In this example, the memory 9, as is shown in the memory map of FIG. 4, the frame readout area ARFM from field readout area ARFD and address 4096 from address 0 to 4095 through address 8191 The read areas ARFD and ARFM are further divided into a minimum correction amplitude data area ARSA, a correction data area ARCM, and a shutter speed data area ARSS.

In the minimum correction amplitude data area ARSA, N pieces of minimum correction amplitudes to be corrected according to the image pickup conditions such as temperature and shutter speed are applied to the image pickup outputs of the CCD image sensors 2R, 2G, 2B. Minimum corrected amplitude data (DSA)
Is written. Minimum correction amplitude data (DSA) above
Is the minimum corrected amplitude data (DSAR) of each RGB channel,
Each of (DSAG) and (DSAB) is composed of 2 bytes of data in which 4 bits are used, 2 bits are used for cycle time data, and the remaining 2 bits are unused.

In the correction data area ARCM, correction data (DCM) obtained by performing the above-mentioned defect test on the CCD image sensors 2R, 2G, 2B is written. The correction data (DCM) includes 8-bit amplitude data (DCMA) corresponding to the defect level, 2-bit mode select data (DMS) indicating the type of defect, and 2-bit color code data (DCC) indicating the correction channel. ) And 12-bit relative address data (RAD) indicating the distance to the next defective pixel position
R) consists of 3 bytes of data. This correction data (DCM) also includes correction data (DCM ') for the above-described dummy defective pixel.

Furthermore, in the shutter speed data area ARSS,
Shutter data (SHD) for converting 4-bit shutter speed data indicating the setting shutter speed of the electronic shutter into 3-bit data, and 12-bit first address data (FADR) indicating the start address of the correction data area ARCM, that is, address 2N. 15 pieces of 2-byte data consisting of the following are written.

In embodiments this embodiment of the G ₄ correction signal generating circuit and its peripheral circuits, so that the correction signal generation circuit 11 is shown a specific example in Figure 5 along with its peripheral circuits, various read from the memory 10 There are provided seven latch circuits 21, 22, 23, 24, 25, 26, 27 to which data is supplied, and a strobe generating circuit 28.

The correction signal generation circuit 11 performs an imaging operation in an operation mode set in the system controller 6,
The initial setting operation is performed during the blanking period of one field or one frame, and
In accordance with the image pickup operation conditions such as the shutter speed set to and the temperature data given from the above temperature sensor 13 through the A / D converter 16, each RGB read from the minimum correction amplitude data area ARSA of the memory 10 While latching the minimum corrected amplitude data (DSAR), (DSAG), (DSAB) of the channel in the first to third latch circuits 21, 22, 23,
The shutter data (SHD) read from the shutter speed data area ARSS of the memory 10 is stored in a fourth latch circuit 2.
4 and the first address data (FA) read from the shutter speed data area ARSS.
DR), the strobe generating circuit 28 causes the address counter 40 to read the correction data (DCM) ₁ from the beginning of the correction data area ARCM of the memory 10, that is, address 2N, and to read the first defective pixel from the origin A ₀ relative address data indicating the distance to the position a ₁ (RADR) the strobe generating circuit
At the same time, the amplitude data (DCMA), the color code data (DCC) and the mode select data (DMS) are latched by the fifth to seventh latch circuits 25, 26 and 27.

Then, when the strobe pulse generation circuit 28 ends the initial setting operation and enters the correction operation state, the strobe pulse generating circuit 28 detects the first defective pixel position A ₁ based on the relative address data (RADR) latched in the initial setting operation. A strobe pulse is output at a timing, the address counter 40 is incremented, the next correction data (DCM) ₂ is read from the correction data area ARCM of the memory 10, and the distance to the next defective pixel position A ₁ is determined. The relative address data shown is latched in the strobe generating circuit 28, and the amplitude data (MCMA), color code data (DCC) and mode select data (DMS) are latched in the fifth to seventh latch circuits 25, 26, 27. Then, the strobe pulse is sequentially output at the timing of each defective pixel position A _N.

The first to third latch circuits 21, 22, and 23 are read from the minimum correction amplitude data area ARSA of the memory 10.
Minimum corrected amplitude data (DSAR) of each RGB channel, (DSA)
G) and (DSAB) and latch the minimum corrected amplitude data (D
SAR), (DSAG), and (DSAB) are supplied to the comparator 30 via the selector 29.

Further, the fourth latch circuit 24 latches shutter data (SHD) read from the shutter speed data area ARSS of the memory 10, and outputs the shutter data (SH
D) is supplied to the bit shift circuit 31 as control data.

Further, the fifth to seventh latch circuits 25, 26, 27
Latches amplitude data (DCMA), color code data (DCC), and mode select data (DMS) among the correction data (DCM) read from the correction data area ARCM of the memory 10.

The amplitude data (DCMA) latched by the fifth latch circuit 25 is supplied to the comparator 30 and is also supplied to the first switch circuit 32 directly and via the bit shift circuit 31. First switch circuit
It is supplied from 32 to a digital / analog (D / A) converter 33. The color code data (DCC) latched by the sixth latch circuit 26 is supplied to the selector 29 as control data and also to the first decoder 43 described later as control data. Furthermore, the mode select data (DMS) latched by the seventh latch circuit 27
Is supplied as control data to the first switch circuit 32, and is also supplied as control data to a second switch circuit 41 and a second decoder 47, which will be described later.

The selector 29 includes the first to third latch circuits.
For the minimum corrected amplitude data (DSAR), (DSAG), and (DSAB) of each RGB channel latched on 21, 22, and 23,
The minimum amplitude correction data (DSA) of any of the RGB channels designated by the color code data (DCC) supplied as control data from the sixth latch circuit 26 is selected and supplied to the comparator 30. Comparator 30 above
Compares the minimum correction amplitude data (DSA) selected by the selector 29 with the amplitude data (DCMA) latched in the fifth latch circuit 25, and uses the comparison output as control data. 3 is supplied to the switch circuit 42, and the amplitude data (DCMA) is converted to the minimum corrected amplitude data (DSA).
If it is larger than the above, the third switch circuit 42 is closed.

Further, the bit shift circuit 31 responds to the amplitude data (DCMA) supplied from the fifth latch circuit 25 according to the shutter data (SHD) supplied as control data from the fourth latch circuit 24. For example, a bit shift process as shown in Table 1 is performed, The bit-shifted amplitude data (DCMA) is supplied to the D / A converter 34 via the first switch circuit 32.

The first switch circuit 32 is connected to the seventh latch circuit.
When the mode select data (DMS) indicates the white defect mode, the bit shift circuit is used as the control data.
31 is selected, and in the case of another defect mode, the fifth latch circuit 25 is controlled to be selected.

Then, the D / A converter 33 converts the amplitude data (DCMA) supplied through the first switch circuit 32 into an analog signal. The analog amplitude signal obtained by the D / A converter 33 is supplied to first and second level adjustment circuits 34 and 35 and is also supplied to first and second temperature correction circuits 14 and 15.
, And selectively output as various amplitude correction signals from these circuits 34, 35, 14, 15 via first to fourth signal switching circuits 36, 37, 38, 39. .

Further, the strobe generation circuit 28 is provided with the first address data (FADR) read from the shutter speed data area ARSS of the memory 10 and the correction data (DCM) read from the correction data area ARCM of the memory 10.
Of the CCD image sensors 2R, 2G, 2B constituting the imaging unit 2 based on the relative address data (RADR)
Of the defective pixel position A ₁ , A ₂ ... At the timing corresponding to the defective pixel position, the strobe pulse is generated directly from the second switch circuit 41 and the third switch 42.
The first address data and the relative address data are preset to the address counter 40 of the memory 10 while being supplied to the first decoder 43 via the.

The second switch circuit 41 is connected to the seventh latch circuit 27.
When the mode select data (DMS) indicates the white defect mode, the third switch circuit
42, and in the case of another defect mode, the first decoder 43 is controlled so as to select the first decoder 43. The strobe pulse of the white defect mode is supplied to the first decoder 43 via the third switch circuit 42. 43, and a strobe pulse of another defect mode is directly supplied to the first decoder 43. The third switch circuit 42 is connected to the comparator 30
Open / close control is performed using the output of the
Only when the amplitude data (DCMA) latched by the fifth latch circuit 25 is larger than the minimum correction amplitude data (DSA) selected by the selector 29, the signal is passed through the second switch circuit 41. The supplied white defect mode strobe pulse is supplied to the first decoder 43.

The first decoder 43 uses the 2-bit color code data (DCC) supplied as control data from the sixth latch circuit 26 to select and designate one of the RGB channels or as shown in Table 2. The strobe pulse is supplied to the second decoder 47 via the D-type flip-flops 44, 45, and 46 of all the channels.

Each of the D-type flip-flops 44, 45, and 46 is provided with the above-described CCD.
Clock pulses (φ _R ), (φ _G ), and (φ _B ) that match the phases of the color components of the imaging output obtained by the image sensors 2R, 2G, and 2B, that is, the phases of the RGB channels are input from the timing generator 5 to the respective clock inputs. Supplied to the end,
Regarding the strobe pulse supplied from the first decoder 43, the clock pulses (φ _R ), (φ _G ),
The phase is adjusted at (φ _B ).

Here, the CCD image sensor 2G for the green (G) image pickup
When the imaging unit 2 is configured by using a spatial picture element shifting method in which the image signal is shifted by 1/2 picture element with respect to the other CCD image sensors 2R and 2B, the clock pulse (φ _R ), (Φ _G ) and (φ _B ), the clock pulse (φ _G ) for the G channel is reversed in phase with the clock pulses (φ _R ) and (φ _B ) of the other R and B channels. can do.

The second decoder 47 selects the 2-bit mode select data (DSM) supplied as control data from the seventh latch circuit 27 according to the correction mode specified as shown in Table 3. Control data is formed from the strobe pulse and applied to each control input terminal of the first to fourth correction signal switching circuits 36, 37, 38, 39.

The first to fourth correction signal switching circuits 36, 3
7, 38 and 39 are provided from the D / A converter 33 to the first or second
The analog amplitude signals output via the level adjustment circuits 34 and 35 or the first or second temperature correction circuits 14 and 15 are switched as follows in accordance with the selection control data by the second decoder 47. And outputs as various correction signals.

That is, the mode select data (DMS) is [L
L] indicates the white defect mode, the third correction signal switching circuit 38 white damages the analog amplitude signal output from the D / A converter 33 via the first temperature correction circuit 14. The defect correction signal (W _CP ) is selectively output to the RGB channel indicated by the color code data (DCC). When the mode select data (DMS) indicates the black defect mode by [LH], the first correction signal switching circuit 36 sends the first correction signal switching circuit 36 from the D / A converter 33 to the first level adjustment circuit 34. as black analog amplitude signal outputted through the flaw defect compensation signal (B _CP), selectively outputs the RGB channels that are indicated by the color code data (DCC). Further, when the mode select data (DMS) indicates the black shading mode by [HL], the fourth correction signal switching circuit 39 is transmitted from the D / A converter 33 via the second temperature correction circuit 15. The analog amplitude signal output as a black shading correction signal (B _SH ) is selectively output to the RGB channel indicated by the color code data (DCC). Furthermore, when the mode select data (DMS) is [HH] indicating the white shading mode, the second correction signal switching circuit 37 causes the D / A converter 33 to move the second level adjusting circuit 35. The analog amplitude signal output via the white shading correction signal (W _SH ) is selectively output to the RGB channels indicated by the color code data (DCC).

Further, in this embodiment, the correction data (DCM) is read from the correction data area ARCM of the memory 10 and various correction signals (W _CP ), (B _CP ), (W _SH ),
At the time of forming (B _SH ), as shown in FIG. 6, the timing of reading signal charges from each defective pixel of each of the CCD image sensors 2R, 2G, and 2B constituting the imaging section 2, that is, the above-described correction Data (DCM) read timing (t _R )
The power supply to the memory 10 is cut off or the power save control is performed except for a period (T _R ) of several tens of clocks before and after that. Thus, unnecessary power consumption by the memory 10 is prevented, and power consumption is reduced.

G ₅ correcting operation and, in this embodiment, color imaging output of each RGB channel obtained by the imaging section 2 (S _R),
(S _G ) and (S _B ) are the first and third correction signal switching circuits 36 that constitute the correction signal switching circuit 12 for the analog amplitude signal output from the D / A converter 33. , 3
At 8, the white pixel defect correction signal (W _CP ) and the black pixel defect correction signal (B _CP ) obtained by switching and selecting according to the defect mode at the timing of each defective pixel position A ₁ , A ₂ ... ,
By being added by the correction signal adding circuit 8,
Correction processing of an image defect due to a white defect and a black defect is performed.

As shown in FIG. 7, the white defect correction signal (W _CP ) selected by the first correction signal switching circuit 36 is the amplitude of the analog amplitude signal output from the D / A converter 33 ( l _W ) in the first temperature correction circuit 14 to which the detection output of the temperature sensor 13 for detecting the temperature of each CCD image sensor 2R, 2G, 2B constituting the image pickup unit 2 is supplied. Amplitude (l _W ′) that optimally corrects white defects at the operating temperature in the actual imaging state by performing temperature correction processing.
Then, by adding the image pickup output obtained by the image pickup unit 2 by the correction signal addition circuit 8, it is possible to optimally correct the white defect having temperature dependency.

Here, the defect level of the white defect having temperature dependency is extremely small at room temperature and is a level that does not cause a problem as a defect, and increases exponentially as the temperature increases, so the white defect correction signal (W _If there is a correction error in the first temperature correction circuit 14 or the like that performs temperature correction processing on _CP ), overcorrection or uncorrection occurs in the white defect correction by the white defect correction signal (W _CP ), which is a so-called correction. Scratches will remain in the image output that has been subjected to the defect correction processing. Therefore, in this embodiment, the minimum correction amplitude data (DSA) read out from the minimum correction amplitude data area ARSA of the memory 10 by using the data such as the shutter speed and the operating temperature as the address data by the above-described initial setting operation is used to generate the correction signal. Latched by the first to third latch circuits 21, 22, and 23 of the circuit 11, the correction data area of the memory 10 during an actual imaging operation.
Correction processing is performed for white defect with a small defect level where the correction amplitude data (DCMA) read from the ARCM is smaller than the minimum correction amplitude data (DSA) and correction flaws due to white defect correction become a problem. By performing the correction process selectively only on the white defect having a high defect level without performing the white defect defect correction process, the white defect correction process is made more effective.

Further, in each of the CCD image sensors 2R, 2G, and 2B constituting the imaging unit 2, when an electronic shutter function is added by controlling the charge accumulation time, an image pickup output is generated according to the charge accumulation time, that is, the shutter speed. The signal level of the included white defect signal changes. In this embodiment, the bit shift circuit 31 uses the shutter data latched in the fourth latch circuit 24 of the correction signal generation circuit 11 by the above-described initial setting operation to cause the bit shift circuit 31 to perform the above-mentioned first operation during the actual imaging operation.
The bit shift processing shown in the table is applied to the corrected amplitude data (DC
MA), the gain of the white defect correction signal (W _CP ) is made to correspond to the set shutter speed, so that the optimum white defect correction process can always be performed. The white defect correction signal (W _CP ) is applied to the set shutter speed.
In addition to the bit shift circuit 31, for example, a multiplication process in which a digital or analog multiplication process is performed on the white defect correction signal (W _CP ) using the shutter speed, that is, the charge accumulation time as a coefficient. A vessel may be provided.

Further, the CCD image sensors 2R, 2G, 2
In B, when the electronic shutter function by controlling the charge storage time is added, the signal charge amount obtained by halving the charge storage period in the field read mode is also the normal mode as shown in FIG. Although it becomes 1/2, the effective charge storage time in frame read mode is 1/4 of that in normal mode, and even if the same shutter speed is set, the effective charge storage time differs depending on the read mode for signal charges. In addition, the signal level of the white defect signal included in the image output is also different. In this embodiment, a field readout area ARFD and a frame readout area ARFM are provided in the memory 10, and minimum correction amplitude data (DSA), correction data (DCM), shutter data (SHD), etc. in each readout mode are written in advance. Then, by reading data from the field readout area ARFD or the frame readout area ARFM corresponding to the actually set readout mode and performing the above-described initial setting operation and correction operation, optimal defect correction can be performed in either readout mode. Processing can be performed.

Further, in this embodiment, the correction signal switching circuit 12 is configured in the signal processing system 9 with respect to the image pickup output which has been subjected to the image defect correction processing due to the white defect and the black defect as described above. Black shading correction signal (B _SH ) obtained by switching and selecting the analog amplitude signal output from the D / A converter 33 in the second and fourth correction signal switching circuits 36 and 38 according to the defect mode.
Shading correction processing is performed using the white shading correction signal (W _SH ).

The black shading correction signal (B _SH ) selected by the fourth correction signal switching circuit 39 is a detection output of the temperature sensor 13 for the amplitude of the analog amplitude signal output from the D / A converter 33. By performing the temperature correction processing in the supplied second temperature correction circuit 15, it is possible to correct the black shading to the minimum state at the operating temperature in the actual imaging state.

H Effect of the Invention In the image defect correction device for a solid-state imaging device according to the present invention,
As the position data of the defective pixel, other defect positions A _n (n is an arbitrary integer) excluding the first defect position A ₀ counted from the reference point are the distances from the immediately preceding defect position A _n-1. Since the converted relative address data is stored in the storage means, the amount of data required to indicate the position of one defective pixel is reduced, and the position data of each defective pixel is efficiently stored in the storage means. You can If the relative distance from any defective pixel to the next defective pixel is large, a dummy defective pixel is set between those pixels and the dummy is stored in the storage means. The maximum value of the relative distance between them, that is, the maximum value of the relative address becomes a small value, and the position data of each defective pixel can be read from the storage means by an address counter having a small number of stages. Therefore, according to the present invention, the position of the defective pixel included in the solid-state image sensor is efficiently represented by the position data having a relatively small number of bits, and the storage unit and its peripheral circuit are simplified, and at the same time, the image defect is generated. It is possible to provide an image defect correction device for a solid-state image pickup device having a novel configuration, which is capable of efficiently performing the correction process of 1. to obtain an image pickup output signal with good image quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video camera to which the present invention is applied, FIG. 2 is a schematic diagram showing a structure of a CCD image sensor constituting an imaging unit of the video camera, and FIG. FIG. 4 is a schematic diagram for explaining a pixel defect of a CCD image sensor and its imaging output, and FIG.
FIG. 5 is a memory map of a memory for storing data on pixel defects of the CCD image sensor. FIG. 5 is a diagram showing a specific configuration of a correction signal generation circuit for reading correction data from the memory and forming various correction signals, and peripheral circuits thereof. FIG. 6 is a timing chart showing a power saving control operation of the memory by the correction signal generation circuit, and FIG. 7 is a defect correction using a correction signal formed by the correction signal generation circuit. FIG. 8 is a waveform diagram for explaining the processing operation, and FIG. 8 is a waveform diagram for explaining the relationship between the charge accumulation time and the charge accumulation amount in the field read mode and the frame read mode of the CCD image sensor. 2 ... Imaging unit 2R, 2G, 2B ... CCD image sensor 3 ... CCD drive circuit 4 ... Sync generator 5 ... Timing generator 6 ... System controller 8 ... Correction signal addition circuit 10 ... Memory 11 ... Correction signal generation circuit 12: Correction signal switching circuit

Claims (1)

(57) [Claims] 1. A storage means for storing data on a position of a defective pixel included in a solid-state image sensor and a defect component level included in an output signal of the solid-state image sensor, and the solid-state image sensor of the solid-state image sensor based on the data read from the memory means. Of the output signals, the output signal of the defective pixel is a defect by combining the output signal of the solid-state image pickup device with a correction signal generation unit that generates a defect correction signal at a timing. and a correcting means for correcting, as the position data of the defective pixel (where n is an arbitrary integer) other defect position a _n except the first defect position a ₀ counted from the reference point one before the defect stores in the storage means by coding the distance from the position a _n-1, if the relative distance from any defective pixel to the next defective pixel is large, the dummy defective pixels between them pixels Set, the solid-state imaging device for an image defect correction apparatus characterized by the data so as to store in the storage means.