JP2605746B2 - Image defect correction device for solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, the present invention will be described in the following order.

A Industrial Field of Use B Summary of the Invention C Prior Art D Problems to be Solved by the Invention E Means for Solving the Problems F Function G Example G ₁ Configuration of Video Camera to which the Present Invention is Applied G ₂ CCD image defect test G ₃ memory map G ₄ correction signal generating circuit and fIELD the present invention on the effect a industrial embodiment G ₅ correcting operation H invention of the peripheral circuit of the sensor is a charge coupled device (CCD: charge coupled Devic
e) The present invention relates to an image defect correction device for a solid-state imaging device that corrects image quality deterioration due to an imaging output from a defective pixel included in the solid-state imaging device by signal processing, and particularly relates to a position and a position of a defective pixel included in the solid-state imaging device. The data about the defect component level included in the output signal is read from the storage means, and a defect correction signal is formed at the timing of the output signal of the defective pixel among the output signals of the solid-state image sensor, and the output of the solid-state image sensor is output. The present invention relates to an image defect correction device for a solid-state imaging device that performs defect correction by adding to a signal.

B SUMMARY OF THE INVENTION The present invention reads out data on the position of a defective pixel included in a solid-state imaging device such as a charge-coupled device CCD and the level of a defective component included in an output signal thereof from storage means,
An image defect correction device for a solid-state imaging device that performs defect correction by forming a defect correction signal at the timing of the output signal of the defective pixel among the output signals of the solid-state imaging device and adding the defect correction signal to the output signal of the solid-state imaging device Operating the storage means only for a predetermined period before and after including the timing for reading out the data necessary for forming the defect correction signal from the storage means, and controlling the storage means to be in an inactive state during other periods. Thus, unnecessary power consumption by the storage means for storing a large amount of data can be prevented, and power consumption can be reduced.

C Conventional technology In general, in a solid-state imaging device formed of a semiconductor such as a CCD, a defective pixel in which a constant bias voltage is always added to an imaging output corresponding to the amount of incident light due to a local crystal defect of the semiconductor or the like. It is known that the image quality is deteriorated due to the imaging output from the defective pixel. An image defect in which a constant bias voltage is always added to the image pickup output appears as a high-brightness spot on a monitor screen if this image defect signal is processed as it is, and is called a white defect.

Conventionally, in order to correct image quality deterioration caused by image pickup output from a defective pixel included in a solid-state imaging device as described above by signal processing, for example, information indicating presence or absence of a defect for each pixel of the solid-state imaging device is stored in a memory. And, based on the information in the memory, a signal interpolated with an imaging output obtained from a pixel adjacent to the defective pixel instead of an imaging output from the defective pixel. Note that storing the information indicating the presence or absence of a defect for each pixel of the solid-state imaging device in the memory in this manner requires using a memory having a huge storage capacity corresponding to the total number of pixels of the solid-state imaging device. Instead of sequentially storing the presence or absence of a defect for each pixel, the present applicant encodes the distance between the defective pixels as data indicating the position of the defective pixel included in the solid-state imaging device and stores the encoded data in a memory. A technique for reducing storage capacity has been proposed (see Japanese Patent Publication No. 60-34872).

In addition, in the correction processing by the interpolation, a large correction error occurs if there is no correlation between the imaging outputs obtained at the pixels in the vicinity of the defective pixel. Therefore, the position of the defective pixel included in the solid-state imaging device and the output signal thereof are generated. The data about the defect component level included is stored in a memory, and a defect correction signal is formed at the timing of the output signal of the defective pixel among the output signals of the solid-state imaging device based on the data read from the memory. An image defect correction apparatus for a solid-state imaging device which performs defect correction by adding the output signal to the output signal of the solid-state imaging device has been proposed (see Japanese Patent Application Laid-Open No. 60-513780).

D Problems to be Solved by the Invention By the way, in the conventional image defect correction device for a solid-state imaging device, the storage capacity can be reduced by encoding the distance between defective pixels and storing it in the memory as described above. However, there is a problem in that the above-mentioned memory is always operated, so that wasteful power consumption is large and the power consumption of the entire apparatus is large.

Therefore, the present invention has been made in view of the above-described conventional problems,
Prevents wasteful power consumption by storage means for storing data on the position of a defective pixel included in the solid-state imaging device and the level of a defective component included in an output signal thereof, thereby reducing the power consumption of the entire apparatus without hindering the correction operation. It is an object of the present invention to provide an image defect correction device for a solid-state imaging device having a novel configuration designed to be used.

E Means for Solving the Problems In order to solve the conventional problems as described above, the present invention provides data on the position of a defect image included in a solid-state imaging device and the level of a defect component included in an output signal thereof. A storage means for storing, and a defect correction signal generating means for generating a defect correction signal at a timing of an output signal of the defective pixel among output signals of the solid-state imaging device based on data read from the storage means, In the image defect correction device for a solid-state imaging device configured to perform defect correction by adding a defect correction signal generated from a defect correction signal generation unit to an output signal of the solid-state imaging device, control for controlling an operation of the storage unit Means for storing the data of the defective pixel from the storage means, including the timing of reading the data from the storage means, for a predetermined pixel period before and after the storage. Operating the stage, during other periods is characterized by controlling said memory means inoperative.

F action In the image defect correction device for a solid-state imaging device according to the present invention,
With respect to the output signal of the solid-state imaging device, the operation of the storage unit storing the data of the defective pixel is controlled by the control unit, and the timing of reading the data of the defective pixel from the storage unit is included in a predetermined pixel extending before and after the timing. The storage means is operated only during the period of, and the defect correction processing is performed based on the data read from the storage means.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Embodiment shown in the block diagram of a configuration Figure 1 in G ₁ camcorder, red (R) imaging light by the imaging optical system 1, green (G), and object image color-separated into three primary components of blue (B) The present invention is applied to a color video camera that performs color imaging using a three-plate imaging unit 2 including three solid-state image sensors formed on an imaging surface.

In this embodiment, as a solid-state image sensor constituting the imaging unit 2, for example, as shown in FIG.
A large number of light receiving sections S corresponding to pixels arranged in a matrix, a vertical transfer register section VR provided along one side of each light receiving section S in the vertical direction, and a vertical transfer register section
It comprises a horizontal transfer register section HR provided on each end side of the VR, and a signal charge corresponding to the amount of received light obtained in each light receiving section S corresponds to each vertical line for every one field period or every one frame period. The signal charges are transferred to each vertical transfer register unit VR, the signal charges are transferred to the horizontal transfer register unit HR through the vertical transfer register units VR, and the signal charge for each horizontal line is taken as an image output from the horizontal transfer register unit HR. Three interline transfer type CCD image sensors 2R, 2G, and 2B that are taken out are used.

The driving circuit 3 of the imaging section 2, together with the vertical transfer pulse phi _V and a horizontal transfer pulse phi _H which blend into the synchronization signal SYNC supplied by ink generator 4 shown in FIG. 1 is supplied from the timing generator 5 , CCD above
A field read mode in which all signal charges corresponding to the amount of received light obtained in each light receiving unit S of the image sensors 2R, 2G, and 2B are read out during one field period, and the signal charges obtained in each of the light receiving units S are all read out in one frame period. A read mode designation signal for designating a frame read mode to be read,
A shutter control signal and the like for controlling the charge accumulation time of the CCD image sensors 2R, 2G and 2B to control the so-called electronic shutter speed are supplied from the system controller 6.

Here, the CCD image sensor 2 constituting the imaging unit 2
R, 2G, and 2B have a charge storage amount of 1/2 of the above-described frame read mode in the field read mode in which the charge storage time is 1/60 second in the frame read mode having a charge storage time of 1/30 second. Therefore, by adding and reading the signal charges obtained from the two light receiving units S adjacent in the vertical direction, the sensitivity is made equal to that in the frame reading mode.

The RGB three-channel color imaging outputs (S _R ), (S _G ), and (S _B ) obtained by the imaging unit 2 configured by the three CCD image sensors 2R, 2G, and 2B are output from the preamplifier 7. After being supplied to the signal processing system 9 via the correction signal adding circuit 8 and subjected to the defect correction processing by the correction signal adding circuit 8, the signal processing system 9 performs the process processing together with the gamma correction and the shading correction. A video signal (S) conforming to a specified standard television system standardized by the CCIR (International Advisory Committee on Radio Communications) and EIA (Electronic Industries Association of America)
_OUT ) and output.

In this embodiment, the CCD image sensors 2R, 2R
For G and 2B, a defect test for analyzing the position of the defective pixel, the type of the defect, the level of the defect, and the like is performed in advance, and these data are stored in the memory 10 as correction data. Based on the correction data read from the memory 10, the white defect correction signal (W _CP ), the black defect correction signal (B _CP ), and the white defect correction signal (B _CP ) are output at the timing of the output signals of the defective pixels of the CCD image sensors 2R, 2G, and 2B. A shading correction signal (W _SH ), a black shading correction signal (B _SH ) and the like are formed, and these correction signals (W _CP ), (B _CP ), (W
By supplying _SH ) and ( _BSH ) to the correction signal addition circuit 8 and the signal processing system 9 via the correction signal switching signal 12, the correction signal addition circuit 8 and the signal processing system 9 cause image defects. Is corrected.

Further, the imaging unit 2 is provided with a temperature sensor 13, which detects the temperatures of the CCD image sensors 2R, 2G, and 2B, and corrects each correction signal for white defect and black shading whose temperature depends on the defect level. Temperature correction processing is performed on (W _CP ) and (B _SH ) by temperature correction circuits 14 and 15 based on the detection output of the temperature sensor 12, respectively.
The temperatures of the CCD image sensors 2R, 2G, 2B indicated by the detection output by the temperature sensor 13 are digitized by an analog / digital (A / D) converter 16 and supplied to the memory 10 as address data. Have been.

Defect Test of G ₂ CCD Image Sensor The defect test for the CCD image sensors 2R, 2G, and 2B is performed at a test temperature higher than room temperature where image defects easily appear. In the defect test, for example, as shown in FIG. 3, the positions A ₁ , A _2, ... Of white defect pixels and black defect pixels of the CCD image sensors 2R, 2G, 2B are confirmed. , The type of the defect and the levels l ₁ , l ₂ ..., And the position data of each defective pixel is obtained as follows. That is, counted from the reference point A ₀ represents at first defective pixel position A ₁ is of a predetermined bit encodes the distance d ₁ from the reference point A ₀ digital data, and other defective pixel position A _n ( n is an arbitrary integer) is the previous defective pixel position A
the distance d _n from _n-1 each coding represents at a predetermined bit of the digital data, further, the first defective pixel position A ₁ and the second defective pixel position of the relative distance d in the example of FIG. 3 as the dummy defective pixel position a _DM1 between a _2, if it can not be the relative distance is too large from any defective pixel to the next defective pixel be represented in digital data of the predetermined bit, they defects by setting the dummy defective pixel among pixels, from the distance d ₂ and the dummy defective pixel position a _DM1 of the relative distance d from the first defective pixel position a ₁ to the dummy defective pixel position a _DM1 respectively as expressed by the predetermined bit of the digital data by dividing the second to the distance d ₃ to the defective pixel position a ₂ of the.

Here, when the positions A ₁ , A ₂ ... Of the defective pixels of the CCD image sensors 2R, 2G, 2B are represented by two-dimensional absolute addresses, for example, 10 bits in the horizontal direction and 10 bits in the vertical direction Although a total of 20 bits of address data are required, the defective pixel position _An (n is an arbitrary integer) is encoded as the distance d _n from the previous defective pixel position _An-1 as described above. By employing a relative address represented by digital data of predetermined bits, the address data can be compressed to the number of bits necessary to represent the maximum value of the relative address. 8-bit data compression is performed for the position of one defective pixel.
The relative distance that can be represented by the 12-bit relative address data is, for example, a maximum of 4.5 lines, and the relative distance from one defective pixel position _An to the next defective pixel position _{An + 1.}
If d _n is more than 4.5 lines away, the relative distance d
by dividing the _n to be within 4.5 lines, the defective pixel position A _n, by setting the A _{n + 1} 1 single or a plurality of dummy defective pixel position A _DM between, 12 relative address bits The defective pixel position _{An + 1} can be represented by the data.
Thus, if it can not be represented in the relative distance d _n is the predetermined bit too large digital data from any defective pixel position A _n up to the next defective pixel position A _{n + 1,} between those of the defective pixel set the dummy defective pixel by dividing the relative distance d _n and, it is possible to represent all of defective pixel locations at a predetermined bit of the digital data. Note that the dummy defective pixel position A _DM1 may adversely affect the quality of the imaging output signal by being set within the blanking period BLK of the imaging output signal read from the CCD image sensors 2R, 2G, 2B. There can be no.

G ₃ Memory Map In this example, the memory 9, as is shown in the memory map of FIG. 4, the frame readout area ARFM from field readout area ARFD and address 4096 from address 0 to 4095 through address 8191 The read areas ARFD and ARFM are further divided into a minimum correction amplitude data area ARSA, a correction data area ARCM, and a shutter speed data area ARSS.

In the minimum correction amplitude data area ARSA, N pieces of minimum correction amplitudes that should be subjected to correction processing on the imaging outputs of the CCD image sensors 2R, 2G, and 2B according to imaging conditions such as temperature and shutter speed are provided. Minimum corrected amplitude data (DSA)
Is written. Above minimum corrected amplitude data (DSA)
Is the minimum corrected amplitude data (DSAR) of each RGB channel,
Each of (DSAG) and (DSAB) is composed of 2 bytes of data in which 4 bits are used, 2 bits are used for cycle time data, and the remaining 2 bits are unused.

In the correction data area ARCM, correction data (DCM) obtained by performing the above-described defect test on the CCD image sensors 2R, 2G, and 2B is written. The correction data (DCM) includes 8-bit amplitude data (DCMA) corresponding to the defect level, 2-bit mode select data (DMS) indicating the type of defect, and 2-bit color code data (DCC) indicating the correction channel. ) And 12-bit relative address data (RAD) indicating the distance to the next defective pixel position
R) consists of 3 bytes of data. This correction data (DCM) also includes correction data (DCM ') for the above-described dummy defective pixel.

Further, in the shutter speed data area ARSS,
Shutter data (SHD) for converting 4-bit shutter speed data indicating the setting shutter speed of the electronic shutter into 3-bit data, and 12-bit first address data (FADR) indicating the start address of the correction data area ARCM, that is, address 2N. 15 pieces of 2-byte data consisting of the following are written.

In embodiments this embodiment of the G ₄ correction signal generating circuit and its peripheral circuits, so that the correction signal generation circuit 11 is shown a specific example in Figure 5 along with its peripheral circuits, various read from the memory 10 There are provided seven latch circuits 21, 22, 23, 24, 25, 26, 27 to which data is supplied, and a strobe generating circuit 28.

The correction signal generation circuit 11 performs an imaging operation in an operation mode set in the system controller 6,
The initial setting operation is performed during the blanking period of one field or one frame, and
RGB read out from the minimum correction amplitude data area ARSA of the memory 10 in accordance with the imaging operation conditions such as the shutter speed set in the memory 10 and the temperature data given from the temperature sensor 13 via the A / D converter 16. The minimum correction amplitude data (DSAR), (DSAG), and (DSAB) of the channel are latched by first to third latch circuits 21, 22, and 23,
The shutter data (SHD) read from the shutter speed data area ARSS of the memory 10 is stored in a fourth latch circuit 2.
4 and the first address data (FA) read from the shutter speed data area ARSS.
DR), the strobe generating circuit 28 causes the address counter 40 to read out the correction data (DCM) ₁ from the beginning of the correction data area ARCM of the memory 10, that is, from address 2N, and the first failed pixel from the origin A ₀ relative address data indicating the distance to the position a ₁ (RADA) the strobe generating circuit
At the same time, the amplitude data (DCMA), the color code data (DCC) and the mode select data (DMS) are latched by the fifth to seventh latch circuits 25, 26 and 27.

Then, when the strobe pulse generating circuit 28 ends the initial setting operation and enters the correction operation state, based on the relative address data (RADR) latched in the initial setting operation, the first defective pixel position A ₁ outputs a strobe pulse at the timing indicates the distance from the correction data area ARCM of the memory 10 is incremented to the address counter 40 reads out the next correction data (DCM) _2, to the next defective pixel position a ₁ The relative address data is latched in the strobe generating circuit 28, and the amplitude data (MCMA), color code data (DCC) and mode select data (DMS) are stored in the fifth to seventh latch circuits 25, 26, 27. latches, performing sequentially output to operate the strobe pulse at the timing of the defective pixel position a _N.

The first to third latch circuits 21, 22, and 23 are read from the minimum correction amplitude data area ARSA of the memory 10.
Minimum corrected amplitude data (DSAR) for each RGB channel, (DSA
G) and (DSAB) and latch the minimum corrected amplitude data (D
SAR), (DSAG), and (DSAB) are supplied to the comparator 30 via the selector 29.

Further, the fourth latch circuit 24 latches shutter data (SHD) read from the shutter speed data area ARSS of the memory 10, and outputs the shutter data (SH
D) is supplied to the bit shift circuit 31 as control data.

Further, the fifth to seventh latch circuits 25, 26, 27
Latches amplitude data (DCMA), color code data (DCC), and mode select data (DMS) among the correction data (DCM) read from the correction data area ARCM of the memory 10.

The amplitude data (DCMA) latched by the fifth latch circuit 25 is supplied to the comparator 30 and is also supplied to the first switch circuit 32 directly and via the bit shift circuit 31. First switch circuit
It is supplied from 32 to a digital / analog (D / A) converter 33. The color code data (DCC) latched by the sixth latch circuit 26 is supplied as control data to the selector 29 and is also supplied as control data to a first decoder 43 described later. Furthermore, the mode select data (DMS) latched by the seventh latch circuit 27
Is supplied as control data to the first switch circuit 32, and is also supplied as control data to a second switch circuit 41 and a second decoder 47, which will be described later.

The selector 29 includes the first to third latch circuits.
For the minimum corrected amplitude data (DSAR), (DSAG), and (DSAB) of each RGB channel latched on 21, 22, and 23,
The minimum amplitude correction data (DSA) of one of the RGB channels specified by the color code data (DCC) supplied as control data from the sixth latch circuit 26 is selected and supplied to the comparator 30. The above comparator
Reference numeral 30 compares the minimum correction amplitude data (DSA) selected by the selector 29 with the amplitude data (DCMA) latched by the fifth latch circuit 25, and outputs the comparison output as control data. To the third switch circuit 42 as
The amplitude data (DCMA) is the minimum corrected amplitude data (DS
If it is larger than A), the third switch circuit 42 is closed.

Further, the bit shift circuit 31 responds to the amplitude data (DCMA) supplied from the fifth latch circuit 25 in accordance with shutter data (SHD) supplied as control data from the fourth latch circuit 24, For example, a bit shift process as shown in Table 1 is performed, The bit-shifted amplitude data (DCMA) is supplied to the D / A converter 34 via the first switch circuit 32.

The first switch circuit 32 is connected to the seventh latch circuit.
When the mode select data (DMS) indicates the white defect mode, the bit shift circuit is used as the control data.
31 is selected, and in the case of another defect mode, the fifth latch circuit 25 is controlled to be selected.

Then, the D / A converter 33 converts the amplitude data (DCMA) supplied through the first switch circuit 32 into an analog signal. The analog amplitude signal obtained by the D / A converter 33 is supplied to first and second level adjustment circuits 34 and 35 and is also supplied to first and second temperature correction circuits 14 and 15.
, And selectively output as various amplitude correction signals from these circuits 34, 35, 14, 15 via first to fourth signal switching circuits 36, 37, 38, 39. .

Further, the strobe generating circuit 28 is provided with first address data (FADR) read from the shutter speed data area ARSS of the memory 10 and correction data (DCM) read from the correction data area ARCM of the memory 10.
Of the CCD image sensors 2R, 2G, 2B constituting the imaging unit 2 based on the relative address data (RADR)
Are generated at timings corresponding to the defective pixel positions A ₁ , A _2, ..., And these strobe pulses are sent directly from the second switch circuit 41 and to the third switch 42.
The first address data and the relative address data are supplied to the address decoder 40 of the memory 10 while being supplied to the first decoder 43 through the first decoder 43.

The second switch circuit 41 is connected to the seventh latch circuit 27.
When the mode select data (DMS) indicates the white defect mode, the third switch circuit
42, and in the case of another defect mode, the first decoder 43 is controlled so as to select the first decoder 43. The strobe pulse of the white defect mode is supplied to the first decoder 43 via the third switch circuit 42. 43, and a strobe pulse of another defect mode is directly supplied to the first decoder 43. The third switch circuit 42 is connected to the comparator 30
Open / close control is performed using the output of the
Only when the amplitude data (DCMA) latched by the fifth latch circuit 25 is larger than the minimum correction amplitude data (DSA) selected by the selector 29, the signal is passed through the second switch circuit 41. The supplied white defect mode strobe pulse is supplied to the first decoder 43.

The first decoder 43 uses the 2-bit color code data (DCC) supplied as control data from the sixth latch circuit 26 to select and designate one of the RGB channels or as shown in Table 2. The strobe pulse is supplied to the second decoder 47 via the D-type flip-flops 44, 45, and 46 of all the channels.

Each of the D-type flip-flops 44, 45, and 46 is provided with the above-described CCD.
Clock pulses (φ _R ), (φ _G ), and (φ _B ) that match the phases of the color components of the imaging output obtained by the image sensors 2R, 2G, and 2B, that is, the phases of the RGB channels are input from the timing generator 5 to the respective clock inputs. Supplied to the end,
Regarding the strobe pulse supplied from the first decoder 43, the clock pulses (φ _R ), (φ _G ),
The phase is adjusted at (φ _B ).

Here, the above-mentioned CCD image sensor 2G for green (G) imaging
When the imaging unit 2 is configured by using a spatial picture element shifting method in which the image signal is shifted by 1/2 picture element with respect to the other CCD image sensors 2R and 2B, the clock pulse (φ _R ), (Φ _G ) and (φ _B ), the clock pulse (φ _G ) for the G channel is reversed in phase with the clock pulses (φ _R ) and (φ _B ) of the other R and B channels. can do.

The second decoder 47 uses the 2-bit mode select data (DMS) supplied as control data from the seventh latch circuit 27 to perform selection according to the correction mode specified as shown in Table 3. The control data is formed from the strobe pulse and supplied to the control input terminals of the first to fourth correction signal switching circuits 36, 37, 38 and 39.

The first to fourth correction signal switching circuits 36, 3
7, 38 and 39 are provided from the D / A converter 33 to the first or second
The analog amplitude signals output via the level adjustment circuits 34 and 35 or the first or second temperature correction circuits 14 and 15 are switched as follows in accordance with the selection control data by the second decoder 47. And outputs as various correction signals.

That is, the mode select data (DMS) is [L
L] indicates the white defect mode, the third correction signal switching circuit 38 converts the analog amplitude signal output from the D / A converter 33 through the first temperature correction circuit 14 into a white defect mode. As a defect correction signal (W _CP ), it selectively outputs to the RGB channel indicated by the color code data (DCC). When the mode select data (DMS) indicates the black defect mode by [LH], the first correction signal switching circuit 36 sends the first correction signal switching circuit 36 from the D / A converter 33 to the first level adjustment circuit 34. as black analog amplitude signal outputted through the flaw defect compensation signal (B _CP), selectively outputs the RGB channels that are indicated by the color code data (DCC). Further, when the mode select data (DMS) indicates the black shading mode by [HL], the fourth correction signal switching circuit 39 is transmitted from the D / A converter 33 via the second temperature correction circuit 15. The analog amplitude signal output as a black shading correction signal (B _SH ) is selectively output to the RGB channel indicated by the color code data (DCC). Further, when the mode select data (DMS) indicates the white shading mode by [HH], the second correction signal switching circuit 37 controls the second level adjusting circuit 35 from the D / A converter 33. The analog amplitude signal output via the selector is selectively output as a white shading correction signal (W _SH ) to the RGB channel indicated by the color code data (DCC).

Further, in this embodiment, the correction data (DCM) is read from the correction data area ARCM of the memory 10, and the various correction signals (W _CP ), (B _CP ), (W _SH ),
At the time of forming (B _SH ), as shown in FIG. 6, the timing of reading signal charges from each defective pixel of each of the CCD image sensors 2R, 2G, and 2B constituting the imaging section 2, that is, the above-described correction Data (DCM) read timing (t _R )
The power supply to the memory 10 is cut off or the power save control is performed except for a period (T _R ) of several tens of clocks before and after that. Thus, unnecessary power consumption by the memory 10 is prevented, and power consumption is reduced.

G ₅ correcting operation and, in this embodiment, color imaging output of each RGB channel obtained by the imaging section 2 (S _R),
(S _G ) and (S _B ) are the first and third correction signal switching circuits constituting the correction signal switching circuit 12 for the analog amplitude signal output from the D / A converter 33. 36,3
The white defect correction signal (W _CP ) and the black defect correction signal (B _CP ) obtained by switching and selecting according to the defect mode at the timing of each defective pixel position A ₁ , A _2. ,
By being added by the correction signal adding circuit 8,
Correction processing of an image defect due to a white defect and a black defect is performed.

As shown in FIG. 7, the white defect correction signal (W _CP ) selected by the first correction signal switching circuit 36 is the amplitude (A) of the analog amplitude signal output from the D / A converter 33. l _W ) in the first temperature correction circuit 14 to which the detection output of the temperature sensor 13 for detecting the temperature of each of the CCD image sensors 2R, 2G, 2B constituting the imaging section 2 is output. by performing the temperature correction processing, amplitudes for optimally correcting the white defects at the operating temperature in the actual imaging state (l _W ')
Then, by adding the image pickup output obtained by the image pickup section 2 to the image pickup output by the correction signal adding circuit 8, it is possible to optimally correct the temperature-dependent white defect.

Here, the defect level of the temperature-dependent white defect is extremely small at room temperature and does not cause a problem as a defect, and increases exponentially as the temperature increases. Therefore, the white defect correction signal (W _If there is a correction error in the first temperature correction circuit 14 or the like that performs the temperature correction process on the _CP , the white defect correction by the white defect correction signal (W _CP ) may be excessively positive or uncorrected, so-called correction. The flaw is left on the image output after the defect correction processing. Therefore, in this embodiment, the minimum correction amplitude data (DSA) read out from the minimum correction amplitude data area ARSA of the memory 10 by using the data such as the shutter speed and the operating temperature as the address data by the above-described initial setting operation is used to generate the correction signal. Latched by the first to third latch circuits 21, 22, and 23 of the circuit 11, the correction data area of the memory 10 during an actual imaging operation.
Correction processing is performed for white defect with a small defect level where the correction amplitude data (DCMA) read from the ARCM is smaller than the minimum correction amplitude data (DSA) and correction flaws due to white defect correction become a problem. By performing the correction process selectively only on the white defect having a high defect level without performing the white defect defect correction process, the white defect correction process is made more effective.

In the 2R, 2G, and 2B by the CCD image sensors constituting the imaging unit 2, when an electronic shutter function is added by controlling the charge deposition time, the imaging output is performed according to the charge accumulation time, that is, the shutter speed. , The signal level of the white defect signal included in the image changes. In this example,
The bit shift circuit 31 based on the shutter data latched in the fourth latch circuit 24 of the correction signal generation circuit 11 by the above-described initial setting operation causes the bit shown in Table 1 during the actual imaging operation to be performed. by performing shift processing on the correction amplitude data (DCMA), it can be performed in correspondence to the gain of the set shutter speed white defects correction signal (W _CP), always optimal white defects correction process .
In order to make the gain of the white defect correction signal (W _CP ) correspond to the set shutter speed, in addition to the bit shift circuit 31, for example, the shutter speed, that is, the charge accumulation time is used as a coefficient to perform the white defect correction. Signal (W _CP )
May be provided with a multiplier for performing digital or analog multiplication processing.

Further, the CCD image sensors 2R, 2G, 2
In B, when the electronic shutter function is added by controlling the charge storage time, as shown in FIG. 8, for example, as shown in FIG. However, the effective charge accumulation time in the frame readout mode is 1/4 that of the normal mode, and the effective charge accumulation time differs depending on the signal charge readout mode even if the same shutter speed is set. In addition, the signal level of the white defect signal included in the imaging output is also different. In this embodiment, a field readout area ARFD and a frame readout area ARFM are provided in the memory 10, and minimum correction amplitude data (DSA), correction data (DCM), shutter data (SHD), etc. in each readout mode are written in advance. Then, by reading data from the field readout area ARFD or the frame readout area ARFM corresponding to the actually set readout mode and performing the above-described initial setting operation and correction operation, optimal defect correction can be performed in either readout mode. Processing can be performed.

Further, in this embodiment, for the image pickup output that has been subjected to the image defect correction processing by the white defect and the black defect as described above, the correction signal switching circuit 12 in the signal processing system 9 is used. A black shading correction signal (B _SH) obtained by switching and selecting the analog amplitude signal output from the D / A converter 33 in the second and fourth correction signal switching circuits 36 and 38 according to the defect mode. ) And a white shading correction signal (W _SH ).

The black shading correction signal (B _SH ) selected by the fourth correction signal switching circuit 39 is a detection output of the temperature sensor 13 for the amplitude of the analog amplitude signal output from the D / A converter 33. By performing the temperature correction processing in the supplied second temperature correction circuit 15, it is possible to correct the black shading to the minimum state at the operating temperature in the actual imaging state.

H Effect of the Invention In the image defect correction device for a solid-state imaging device according to the present invention,
By controlling the operation of the storage means storing the defective pixel data of the solid-state imaging device by the control means, the storage means is stored for a predetermined pixel period before and after the timing including the timing of reading the data of the defective pixel from the storage means. By operating, the data of the defective pixel can be reliably read from the storage means, and the defect correction processing can be appropriately performed on the output signal of the solid-state imaging device based on the data read from the storage means. . In addition, during the period other than the predetermined period required for forming the defect correction signal, the storage unit is controlled to be in an inoperative state, so that unnecessary power consumption in the storage unit can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a video camera to which the present invention is applied, FIG. 2 is a schematic diagram showing a structure of a CCD image sensor constituting an imaging unit of the video camera, and FIG. FIG. 4 is a schematic diagram for explaining a pixel defect of a CCD image sensor and its imaging output, and FIG.
FIG. 5 is a memory map of a memory for storing data on pixel defects of the CCD image sensor. FIG. 5 is a diagram showing a specific configuration of a correction signal generation circuit for reading correction data from the memory and forming various correction signals, and peripheral circuits thereof. FIG. 6 is a timing chart showing a power saving control operation of the memory by the correction signal generation circuit, and FIG. 7 is a defect correction using a correction signal formed by the correction signal generation circuit. FIG. 8 is a waveform diagram for explaining the processing operation, and FIG. 8 is a waveform diagram for explaining the relationship between the charge accumulation time and the charge accumulation amount in the field read mode and the frame read mode of the CCD image sensor. 2 ... Imaging unit 2R, 2G, 2B ... CCD image sensor 3 ... CCD drive circuit 4 ... Sync generator 5 ... Timing generator 6 ... System controller 8 ... Correction signal addition circuit 10 ... Memory 11 ... Correction signal generation circuit 12: Correction signal switching circuit

Claims (1)

(57) [Claims] 1. A storage means for storing data on the position of a defect image included in a solid-state imaging device and the level of a defect component included in an output signal of the solid-state imaging device. A defect correction signal generating means for generating a defect correction signal at the timing of the output signal of the defective pixel among the output signals, wherein a defect correction signal generated from the defect correction signal generating means is added to the output signal of the solid-state imaging device. In the image defect correction apparatus for a solid-state imaging device, the control unit controls the operation of the storage unit, and includes a timing for reading the data of the defective pixel from the storage unit. Operating the storage means only for a predetermined pixel period, and controlling the storage means to a non-operation state during other periods. An image defect correction device for a solid-state imaging device, which is characterized by