JP2561914B2 - Gate circuit for driving FET - Google Patents

Description

TECHNICAL FIELD The present invention relates to a gate circuit for driving an FET.

[Prior Art] A drive circuit of POWER-MOS-FET used for high-speed switching operation of a power device of a power source using an inverter is described in, for example, Transistor Technology (12-1985 P446).

 Such a conventional gate circuit will be described with reference to FIG.

In the figure, 1 is a switching element FET, 2 is a pulse transformer, 3 is a discharging transistor, 4 and 5 are diodes, 6 is a capacitor that serves as a power source of the discharging transistor 3, 7 to
11 is a resistance.

Next, the operation will be described. FET1 to pulse transformer 2
When a pulse that turns on the gate of is generated, the current at the rising edge of the pulse flows through the gate capacitor 6 of diode 4 FET1 and diode 5 of diode 1. At this time, the equivalent input capacitance of FET1 is rapidly charged and FET1 turns on. After being turned on, a current flows through the resistor C and the capacitor 6 is further charged. The voltage of the capacitor 6 becomes the current of the transistor 3 at the time of rising shown below. Here, the voltage of the resistor C is applied as the gate-source voltage of the FET1.
Next, in the operation at the fall, the pulse of the pulse transformer 2 is turned off and the base of the transistor 3 is positively biased. As a result, the transistor 3 is turned on, and the electric charge accumulated in the equivalent input capacitance of the FET 1 is discharged through the path of the resistor 8 transistor 3 and the capacitor 6. Therefore FE
The gate-source voltage of T1 drops rapidly and FET1 turns off. Here, the resistors a, c, and d are used to suppress the bounce voltage of the LCR of the circuit.

[Problems to be solved by the invention]

Since the conventional FET drive circuit is configured as described above, when the transistor is positively biased and turned on, the pulse input to the pulse transformer is turned on during the period when the gate voltage of the FET is negative voltage. It is limited to the period when the exciting current of the pulse transformer is consumed in the circuit from the time when it is turned off. Therefore, the gate voltage of the FET cannot be pulled to a negative voltage at any time, and in the case of a pulse with a long pulse period, that is, with a long OFF period, the state in which the gate voltage of the FET becomes 0 V is long. Will continue. Therefore, when an attempt is made to configure a ribbing type inverter power supply using the conventional FET drive circuit described above, there is a drawback that the FET during the idle period turns on due to the switching noise at the rise and fall of the other FET. Atsuta Also, there is a problem that the number of parts increases due to the use of transistors and the like.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a device having a simple drive circuit configuration and capable of preventing malfunction due to switching noise.

[Means for solving problems]

The FET driving gate circuit according to the present invention includes a first pulse transformer for generating a gate pulse for turning on the FET, and the FET.
It is composed of a second pulse transformer that generates a gate pulse to turn off, and they are connected in parallel.

[Action]

The first and second pulse transformers according to the present invention are
Since they are connected in parallel to each other and are configured to operate independently without interference, the FETs can be turned on and off reliably.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a gate circuit for driving the FET of the inverter. In the figure, 21 is POWER, which is the switching element of the inverter.
MOS FET, 22 is the first pulse transformer that turns on the FET,
23 is a second pulse transformer for turning off the FET, 24 is a rectifying diode A, 25 is a rectifying diode B, and 26 is a zener diode.

Next, the operation will be described. First pulse transformer 22
When a pulse to turn on the FET21 is applied to, the current flows in the order of the rectifying diode A24 → the gate of the FET21 → the zener diode. Then, FET21 is on and the gate of FET21 −
The input capacitance between the sources is charged. In this case, the pulse voltage input to the first pulse transformer 22 is selected as a value obtained by adding the gate voltage required to turn on the FET and the zener voltage of the zener diode 26. Next, when turning off the FET 21 at high speed, when the pulse applied to the first pulse transformer 22 turns from ON to OFF, the second pulse transformer 23 is turned on by F
Apply a pulse to turn off ET21. Then the current is FET21
Source → rectifier diode B25 in that order, the charge charged in the input capacitance of FET21 is rapidly discharged, and FET21 is turned off. In this case, the Zener diode 26 functions to prevent interference with the first pulse transformer 22 due to the signal that turns off the FET 21. Then, the Zener voltage is selected to be the same value as the pulse voltage applied to the second pulse transformer 23. The period for applying the pulse for turning off the FET 21 may be any time as long as the first pulse transformer 22 is in the off state. Not only can it be set at an arbitrary time, but a plurality of pulses are applied and the FET It is also possible to pull the gate potential to a negative potential.

When the FET driving gate circuit according to the present invention is applied to the full-bridge type inverter circuit, the malfunction due to the switching noise of the FET banks can be prevented.

This will be described in detail below. FIG. 2 shows an embodiment in which the gate circuit according to the present invention is applied to a full-bridge type inverter power supply using a magnetron as a load. In the figure, 30 to 33 are POWER-MOS-FETs Q1 to Q4, and the gate circuits shown in FIG. 1 are respectively connected between the gate sources of four FETs (not shown). 34 is a high voltage transformer, 35 is a voltage doubler capacitor, 36 is a diode, and 37 is a magnetron. The operation of this circuit is that FET Q1Q2 is the first bank and FET
When Q3 and Q4 are used as the second bank to turn on and off each other, a high frequency voltage is generated in the high voltage transformer 34, and the magnetron 37 is activated by the DC voltage obtained by the voltage doubler capacitor 35 and the diode 36. The method for preventing malfunctions due to switching noise of the FETs in the first bank and the second bank is such that the pulse of the gate circuit shown in FIG. This is done by applying to a transformer. That is, in FIG. 3 (a), first, when the pulse of the Q1Q2ON signal falls, a Q1Q2OFF signal pulse is generated to pull the gate potential to a negative potential.
Switch at high speed. Next, the Q1Q2OFF signal is generated at the rising and falling edges of the Q3Q4ON signal pulse, and the gate potential of Q1Q2 is pulled to a negative potential to prevent malfunction of the FET Q1Q2 due to switching noise. Similarly Q1Q2O
At the rising and falling edges of the N signal pulse, the Q3Q4OFF signal is generated to prevent malfunction. With the above gate pulse
The gate voltage of the FET is shown in FIG. 3 (b), which works without malfunction. However, as shown in Fig. 3 (c), if the gate potential of the FET of another bank is not drawn to a negative potential at the rise and fall of the FET of the other bank, the switching noise indicated by the arrow is induced in the gate of the FET. , FET malfunctions.

〔The invention's effect〕

As described above, according to the present invention, the first gate circuit which is made up of the rectifying diode and the Zener diode connected to the secondary side of the first pulse transformer and turns on the FET, and the secondary circuit of the second pulse transformer. It is composed of a second gate circuit composed of a rectifying diode connected to the side to turn off the FET, and the zener voltage of the zener diode is set to the same value as the voltage of the second pulse transformer. By using the first and second pulse transformers, the charge charged in the input capacitance of the FET can be rapidly discharged, and the gate voltage of the FET can be changed to a negative voltage at any width regardless of the ON width of the FET. It can be set, and malfunction due to switching noise can be prevented. Further, the Zener voltage of the Zener diode is selected to be the same value as the voltage of the second pulse transformer, so the Zener diode can prevent the interference of the signal for turning off the FET21 to the first pulse transformer, and further malfunction. There is an effect that can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a FET driving gate circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 is a diagram for explaining the operation of the gate circuit. FIG. 4 is a circuit diagram showing a conventional FET driving gate circuit. In the figure, 21 is a FET, 22 is a first pulse transformer, 23 is a second pulse transformer, 24 is a rectifying diode A, 25 is a rectifying diode B, and 26 is a zener diode. In the figure, the same reference numerals indicate the same or corresponding parts.

Claims (4)

(57) [Claims] 1. An inverter circuit using a FET, comprising: a first pulse transformer for generating a first gate pulse;
Turns on the FET, which consists of a rectifying diode and a zener diode connected to the secondary side of the first pulse transformer.
And a rectifying diode connected to the secondary side of the second pulse transformer and a second pulse transformer for generating a second gate pulse.
And a second gate circuit for turning off T, and the zener voltage of the zener diode is selected to be the same value as the voltage of the second pulse transformer.
Driving gate circuit. 2. The inverter circuit comprises 4 FETs, 2
The FET driving gate circuit according to claim 1, wherein the other two FETs are turned off while the other FETs are turned on. 3. The gate potential of the other two FETs is kept at a negative potential at the rising edge of turning on the two FETs and at the falling edge of turning off the two FETs. Described
Gate circuit for FET drive. 4. The load of the inverter circuit comprises a high frequency transformer, a voltage doubler capacitor and a rectifier diode connected to the secondary side of the high frequency transformer, and a magnetron. The FET driving gate circuit according to the item 1.