JPH01155715A - Gate drive circuit for semiconductor switching element - Google Patents
Gate drive circuit for semiconductor switching elementInfo
- Publication number
- JPH01155715A JPH01155715A JP62313196A JP31319687A JPH01155715A JP H01155715 A JPH01155715 A JP H01155715A JP 62313196 A JP62313196 A JP 62313196A JP 31319687 A JP31319687 A JP 31319687A JP H01155715 A JPH01155715 A JP H01155715A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- terminal
- source
- switching element
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004804 winding Methods 0.000 abstract description 9
- 238000007599 discharging Methods 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
- H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、MOSFET等の半導体スイッチング素子の
ゲート駆動回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate drive circuit for a semiconductor switching element such as a MOSFET.
第5図はMOSFETのゲート駆動回路の従来例を示す
もので、図中3はMOS F ET、2はMOSFET
3のゲート端子、ソース端子間に接続されるパルストラ
ンスである。該パルストランス2の1次巻線の両端子a
、bには駆動信号源1が接続され、またパルストランス
2の2次巻線の両端子c、dのうちCは抵抗4、ダイオ
ード5を介してMOSFET3のゲート端子に、bはM
OSFET3のソート端子に接続される。Figure 5 shows a conventional example of a MOSFET gate drive circuit, in which 3 is a MOSFET and 2 is a MOSFET.
This is a pulse transformer connected between the gate terminal and source terminal of No. 3. Both terminals a of the primary winding of the pulse transformer 2
, b are connected to the drive signal source 1, and of both terminals c and d of the secondary winding of the pulse transformer 2, C is connected to the gate terminal of the MOSFET 3 via a resistor 4 and a diode 5, and b is connected to the gate terminal of the MOSFET 3.
Connected to the sort terminal of OSFET3.
さらに、前記端子Cは分岐されて抵抗6を介してトラン
ジスタ7のベース端子に接続され、このトランジスタ7
のエミッタ端子は前記ダイオード5とMOSFET3の
ゲート端子の接続中点に、コレクタ端子はパルストラン
ス2の端子dとMOSFET3のソート端子との接続中
点に接続される。Further, the terminal C is branched and connected to the base terminal of a transistor 7 via a resistor 6.
The emitter terminal is connected to the midpoint between the diode 5 and the gate terminal of the MOSFET 3, and the collector terminal is connected to the midpoint between the terminal d of the pulse transformer 2 and the sort terminal of the MOSFET 3.
第6図は、前記第5図の回路の動作波形図である。FIG. 6 is an operational waveform diagram of the circuit shown in FIG. 5.
第6・図上部に示すような方形波の駆動信号を信号源1
からパルストランス2の1次巻線に印加すると、2次巻
線側には相似で大きさは巻線比に比例した電圧が発生す
る。その際、MOSFET3のゲート、ソース間の電圧
波形は第6図下部のようになる。このゲート、ソース間
電圧Vsは最大値v1まで上昇すると入力容量Ciss
を充電する際に生じる消費電力は1 / 2 Ciss
Vz 2となる。6. A square wave drive signal as shown in the upper part of the figure is sent to the signal source 1.
When applied to the primary winding of the pulse transformer 2, a similar voltage is generated on the secondary winding side, the magnitude of which is proportional to the turns ratio. At this time, the voltage waveform between the gate and source of MOSFET 3 becomes as shown in the lower part of FIG. When this gate-source voltage Vs rises to the maximum value v1, the input capacitance Ciss
The power consumption generated when charging is 1/2 Ciss
Vz becomes 2.
また、入力容量C15sに蓄積されたエネルギー1/2
CissV1’はトランジスタ7を通じて放電するため
、1回の充放電で最小のC15sV12のエネルギーを
消費し、周波数がfの場合、少なくともf −C15s
V12の電力が消費されるという問題があった。Also, 1/2 of the energy stored in the input capacitor C15s
Since CissV1' is discharged through the transistor 7, it consumes the minimum energy of C15sV12 in one charge/discharge, and when the frequency is f, at least f −C15s
There was a problem that the power of V12 was consumed.
本発明の目的は前記従来例の不都合を解消し、より少な
い消費電力の半導体スイッチング素子のゲート駆動回路
を提供することにある。An object of the present invention is to eliminate the disadvantages of the conventional example and provide a gate drive circuit for a semiconductor switching element that consumes less power.
本発明は前記目的を達成するため、MOSFET等の半
導体スイッチング素子のゲート端子及びソース端子間に
パルストランスを接続し、駆動信号をこのパルストラン
スを介して該スイッチング素子に与え、ゲート端子とソ
ース端子間の電圧を変化することによりそのオン、オフ
動作を行わせるいわゆる電圧制御形のゲート駆動回路に
おいて、前記パルストランスと直列に該半導体スイッチ
ング素子のゲート、ソース間のしきい値電圧付近の電圧
源を接続したことを要旨とするものである。In order to achieve the above object, the present invention connects a pulse transformer between the gate terminal and source terminal of a semiconductor switching element such as a MOSFET, applies a drive signal to the switching element via this pulse transformer, and connects the gate terminal and the source terminal. In a so-called voltage-controlled gate drive circuit that turns on and off by changing the voltage between, a voltage source near the threshold voltage between the gate and source of the semiconductor switching element is connected in series with the pulse transformer. The gist is that the two are connected.
本発明によれば、MOS F ET等半導体スイッチン
グ素子のゲート端子及びソース端子間に接続されるパル
ストランスと直列にそのしきい値電圧付近の直流バイア
ス電圧を与えておくことにより、ゲート、ソース間電圧
の変化幅を狭くし該半導体スイッチング素子の入力容量
の充放電時の消費電力を低減できる。According to the present invention, by applying a DC bias voltage near the threshold voltage in series with a pulse transformer connected between the gate terminal and source terminal of a semiconductor switching element such as a MOS FET, By narrowing the range of voltage change, it is possible to reduce power consumption during charging and discharging of the input capacitance of the semiconductor switching element.
以下、図面について本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第1図は本発明の半導体のスイッチング素子のゲート駆
動回路の第1実施例を示す回路図で、前記従来例を示す
第5図と同一構成要素には同一参照符号を付したもので
ある。FIG. 1 is a circuit diagram showing a first embodiment of a gate drive circuit for a semiconductor switching element according to the present invention, and the same components as in FIG. 5 showing the conventional example are given the same reference numerals.
半導体のスイッチング素子としてのMOSFET3のゲ
ート端子とソース端子間にパルストランス2の2次巻線
の端子g、hが接続され、該パルストランス2の1次巻
線の端子e、fは駆動信号の信号源lに接続される点は
従来と同じであるが、本発明はパルストランス2の2次
巻線端子りとMOSFET3のソース端子間に定電圧源
10を直列に接続した。The terminals g and h of the secondary winding of the pulse transformer 2 are connected between the gate terminal and the source terminal of the MOSFET 3 as a semiconductor switching element, and the terminals e and f of the primary winding of the pulse transformer 2 are connected to the drive signal. The connection to the signal source 1 is the same as in the conventional case, but in the present invention, a constant voltage source 10 is connected in series between the secondary winding terminal of the pulse transformer 2 and the source terminal of the MOSFET 3.
この定電圧源10の電圧vOは、MOSFET3のゲー
ト、ソース間電圧V’sに直流バイアスを与えるもので
、この電圧vOをMOSFET3の入力容量Cissに
関し、該MO5FET3のゲート、ソース間のしきい値
電圧vth付近に設定する。The voltage vO of this constant voltage source 10 gives a DC bias to the voltage V's between the gate and source of MOSFET3. Set around voltage vth.
次に、動作について説明する。第2図は動作波形を示す
もので、方形波の駆動信号を信号源lからパルストラン
ス2の1次巻線に印加すると、2次側には1次側と相似
で大きさは巻数比に比例した電圧が発生する。この1次
側端子e、f間の電圧をVer、2次側端子g、h間の
電圧をVghとする。Next, the operation will be explained. Figure 2 shows the operating waveform. When a square wave drive signal is applied from signal source 1 to the primary winding of pulse transformer 2, the secondary side is similar to the primary side and the magnitude is proportional to the turns ratio. A proportional voltage is generated. The voltage between the primary terminals e and f is Ver, and the voltage between the secondary terminals g and h is Vgh.
駆動信号源1からの駆動信号によりVghが負から正に
なるとMOSFET3のゲート、ソース間電圧V&sは
Vo+Vgh(第2図中v2と表示)となり、入力容量
Cissが充電され、この電圧がvth以上となると、
MOSFET3はオン状態となる。When Vgh changes from negative to positive due to the drive signal from the drive signal source 1, the voltage V&s between the gate and source of MOSFET 3 becomes Vo+Vgh (indicated as v2 in Figure 2), the input capacitance Ciss is charged, and this voltage exceeds vth. Then,
MOSFET3 is turned on.
次に信号源lからの駆動信号の極性が反転しVghが正
から負になると、V’sはVo−Vgh(第4図中v3
と表示)となり入力容量Cissは放電し、この電圧が
しきい値電圧vth以下となるとMOSFET3はオフ
状態となる。Next, when the polarity of the drive signal from signal source 1 is reversed and Vgh changes from positive to negative, V's becomes Vo-Vgh (v3 in Figure 4).
), the input capacitance Ciss is discharged, and when this voltage becomes equal to or lower than the threshold voltage vth, the MOSFET 3 is turned off.
このようにして、定電圧源lOはV’sに直流バイアス
を与えるもので、この電圧vOをvth付近に設定し、
Vo+VghでVthを超え、Vo−Vghでv th
を下回るよう動作させれば、MOS F ET 3をオ
ン、オフできる。これによりオン、オフ時の電圧変化幅
V2−V3を従来回路より充分小さくでき、入力容量C
issの充放電時の消費電力を少なくできる。In this way, the constant voltage source lO gives a DC bias to V's, and this voltage vO is set near vth,
Vo+Vgh exceeds Vth, Vo-Vgh exceeds vth
MOS FET 3 can be turned on and off by operating the voltage below this level. As a result, the voltage change width V2-V3 during on and off can be made sufficiently smaller than the conventional circuit, and the input capacitance C
Power consumption during charging and discharging of the iss can be reduced.
第3図は本発明の第2実施例を示すもので、パルストラ
ンス2は2次側に3つの端子に、 It、 mをもち
、端子には抵抗16とダイオード17の直列接続回路を
介してMOSFET3のソース端子に、端子lはゲート
端子に、端子mはコンデンサ14と抵抗15の並列接続
回路を介してソース端子にそれぞれ接続される。FIG. 3 shows a second embodiment of the present invention, in which a pulse transformer 2 has three terminals It and m on the secondary side, and a resistor 16 and a diode 17 are connected in series to the terminals. The terminal l is connected to the source terminal of the MOSFET 3, the terminal l is connected to the gate terminal, and the terminal m is connected to the source terminal via a parallel connection circuit of a capacitor 14 and a resistor 15.
第4図は前記第3図回路の動作波形図で、パルストラン
ス2の1次側電圧vijが負になると、2次側端子に、
m間にはv4が生じ、端子m−抵抗15およびコンデン
サ14→ダイオード17→抵抗16→端子にの経路に電
流が流れコンデンサ14が充電される。このコンデンサ
電圧VcはVSからダイオード17の順方向電圧降下V
、を引いた電圧を抵抗15と抵抗16とで分圧した値と
なる。FIG. 4 is an operating waveform diagram of the circuit shown in FIG. 3. When the primary side voltage vij of the pulse transformer 2 becomes negative, the secondary side terminal
A voltage v4 is generated between the terminal m and the resistor 15, and current flows through the path from the terminal m to the resistor 15 and the capacitor 14, the diode 17, the resistor 16, and the terminal, and the capacitor 14 is charged. This capacitor voltage Vc is the forward voltage drop V of the diode 17 from VS.
It is the value obtained by dividing the voltage obtained by subtracting , by the resistor 15 and the resistor 16.
次に、vijが負から正になると2次側端子l。Next, when vij changes from negative to positive, the secondary terminal l.
m間に■5が生じ、V4sはVc+Vsとなり前記第1
図の第1実施例同様MO3FET3をオンできる。この
コンデンサ14と抵抗15の時定数を、MOSFET3
のスイッチング周期より十分大きくすればVcはほぼ一
定電圧となり第1図の定電圧源10と等価であると考え
られる。■5 occurs between m, and V4s becomes Vc+Vs, and the first
As in the first embodiment shown in the figure, the MO3FET 3 can be turned on. The time constant of this capacitor 14 and resistor 15 is set to MOSFET 3.
If the switching period is made sufficiently larger than the switching period of , Vc becomes a substantially constant voltage, which is considered to be equivalent to the constant voltage source 10 of FIG.
なお、以上の実施例では半導体スイッチング素子として
MOS F ETの場合について説明したが、これに限
定することなく、他の電圧制御形の各種半導体素子のゲ
ート駆動回路にも本発明は通用できるものである。In the above embodiments, the case where a MOS FET is used as the semiconductor switching element has been explained, but the present invention is not limited to this, and can be applied to gate drive circuits of various other voltage-controlled semiconductor elements. be.
以上述べたように本発明の半導体スイッチング素子のゲ
ート駆動回路は、MOSFET等の半導体スイッチング
素子のゲート端子及びソース端子間にパルストランスを
接続し、駆動信号をこのパルストランスを介して該スイ
ッチング素子に与え、ゲート端子とソース端子間の電圧
を変化することによりそのオン、オフ動作を行わせるい
わゆる電圧制御形のゲート駆動回路において、ゲート、
ソース間電圧の振幅を狭くして入力容量の充放電時の消
費電力を低減することができるものである。As described above, the gate drive circuit for a semiconductor switching element of the present invention connects a pulse transformer between the gate terminal and source terminal of a semiconductor switching element such as a MOSFET, and transmits a drive signal to the switching element via this pulse transformer. In a so-called voltage-controlled gate drive circuit, the gate is turned on and off by changing the voltage between the gate terminal and the source terminal.
By narrowing the amplitude of the source-to-source voltage, power consumption during charging and discharging of the input capacitor can be reduced.
第1図は本発明の半導体スイッチング素子のゲート駆動
回路の第1実施例を示す回路図、第2図は同上動作波形
図、第3図は第2実施例を示す回路図、第4図は同上動
作波形図、第5図は従来例を示す回路図、第6図はこの
第5図回路の動作波形図である。
1・・・駆動信号源 2・・・パルストランス3・
・・MOSFET 4.6.15.16−・・抵抗5
.17・・・ダイオード 7・・・トランジスタ10・
・・定電圧源 14・・・コンデンサC15s・
・・入力容量FIG. 1 is a circuit diagram showing a first embodiment of a gate drive circuit for a semiconductor switching element of the present invention, FIG. 2 is an operation waveform diagram of the same as above, FIG. 3 is a circuit diagram showing a second embodiment, and FIG. FIG. 5 is a circuit diagram showing a conventional example, and FIG. 6 is an operation waveform diagram of the circuit shown in FIG. 1... Drive signal source 2... Pulse transformer 3.
・・MOSFET 4.6.15.16−・・Resistance 5
.. 17...Diode 7...Transistor 10.
・・Constant voltage source 14...Capacitor C15s・
・・Input capacity
Claims (1)
及びソース端子間にパルストランスを接続し、駆動信号
をこのパルストランスを介して該スイッチング素子に与
え、ゲート端子とソース端子間の電圧を変化することに
よりそのオン、オフ動作を行わせるいわゆる電圧制御形
のゲート駆動回路において、前記パルストランスと直列
に該半導体スイッチング素子のゲート、ソース間のしき
い値電圧付近の電圧源を接続したことを特徴とする半導
体スイッチング素子のゲート駆動回路。A pulse transformer is connected between the gate terminal and source terminal of a semiconductor switching element such as a MOSFET, and a drive signal is applied to the switching element via this pulse transformer, and the voltage between the gate terminal and the source terminal is changed to turn on the switching element. , a semiconductor switching device characterized in that, in a so-called voltage-controlled gate drive circuit that performs an OFF operation, a voltage source near a threshold voltage between the gate and source of the semiconductor switching element is connected in series with the pulse transformer. Gate drive circuit for the device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62313196A JPH01155715A (en) | 1987-12-11 | 1987-12-11 | Gate drive circuit for semiconductor switching element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62313196A JPH01155715A (en) | 1987-12-11 | 1987-12-11 | Gate drive circuit for semiconductor switching element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01155715A true JPH01155715A (en) | 1989-06-19 |
Family
ID=18038259
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62313196A Pending JPH01155715A (en) | 1987-12-11 | 1987-12-11 | Gate drive circuit for semiconductor switching element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01155715A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03126315A (en) * | 1989-10-12 | 1991-05-29 | Nagano Japan Radio Co | Driving circuit for switching regulator |
JP2005086917A (en) * | 2003-09-09 | 2005-03-31 | Mitsubishi Electric Corp | Semiconductor driving circuit |
JP2008136326A (en) * | 2006-11-29 | 2008-06-12 | Densei Lambda Kk | Gate drive circuit for switching element |
JP2008259275A (en) * | 2007-04-02 | 2008-10-23 | Densei Lambda Kk | Gate drive circuit of switching element |
CN108631560A (en) * | 2018-04-28 | 2018-10-09 | 北京机械设备研究所 | A kind of low-loss driving circuit for opening MOSFET suitable for no-voltage |
-
1987
- 1987-12-11 JP JP62313196A patent/JPH01155715A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03126315A (en) * | 1989-10-12 | 1991-05-29 | Nagano Japan Radio Co | Driving circuit for switching regulator |
JP2005086917A (en) * | 2003-09-09 | 2005-03-31 | Mitsubishi Electric Corp | Semiconductor driving circuit |
JP2008136326A (en) * | 2006-11-29 | 2008-06-12 | Densei Lambda Kk | Gate drive circuit for switching element |
JP2008259275A (en) * | 2007-04-02 | 2008-10-23 | Densei Lambda Kk | Gate drive circuit of switching element |
CN108631560A (en) * | 2018-04-28 | 2018-10-09 | 北京机械设备研究所 | A kind of low-loss driving circuit for opening MOSFET suitable for no-voltage |
CN108631560B (en) * | 2018-04-28 | 2020-10-30 | 北京机械设备研究所 | Low-loss driving circuit suitable for zero-voltage switching-on MOSFET |
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