JP3348022B2 - Gate drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IGBT (Insu
The present invention relates to a driving circuit for a MOS gate transistor such as a related gate bipolar transistor (MOSFET).

[0002]

2. Description of the Related Art FIG.
FIG. 1 is a circuit diagram showing a conventional gate drive circuit of a MOS gate transistor described in Japanese Unexamined Patent Application Publication No. H10-209,004. Where M
IGBT which is a device having both high-speed switching characteristics of a MOS gate and high withstand voltage and high conduction characteristics by a bipolar transistor operation as an OS gate transistor
Is used. In the figure, 1 is an IGBT, 2, 3, and 4 are I
A gate (G), a collector (C), and an emitter (E) 5 as control terminals of the GBT 1 are capacitance between the gate 2 and the emitter 4. Reference numeral 6 denotes a gate protection resistor connected to the gate 2, 7 denotes a positive voltage source, 8 denotes a first capacitor charged by the voltage source 7, and 9 denotes a P-type MO.
The SFET 10 is configured by connecting an electrostatic capacitance 5, a gate protection resistor 6, a P-type MOSFET 9 and a first capacitor 8 in series, and turns ON / OF the P-type MOSFET 9.
5 is a first circuit that is opened and closed by F. Reference numeral 11 denotes a negative voltage source, 12 denotes a second capacitor charged by the voltage source 11, 13 denotes an N-type MOSFET, 14 denotes a capacitance 5, a gate protection resistor 6, an N-type MOSFET 13, and Two capacitors 12 connected in series,
This is a second circuit that is opened and closed by turning on / off an N-type MOSFET 13. 15 is a P-type MOSFET 9
And a control signal (A) input to the mutually connected gates of the N-type MOSFET 13.

[0003] As shown in the figure, the emitter 4 is grounded,
The reference potential of the voltage sources 7 and 11 and the connection point of the first and second capacitors 8 and 12 are provided. In the gate drive circuit configured as described above, the gate 2 of the IGBT 1
The charging voltage charged in the capacitance 5 between the emitters 4 is IG
By controlling this gate voltage as the gate voltage of BT1, ON / OFF switching control of IGBT1 is performed. The operation of the gate drive circuit will be described below.

First, a first capacitor 8 is charged to a positive polarity by a voltage source 7, while a second capacitor 12 is charged to a negative polarity by a voltage source 11. When the control signal 15 has a negative voltage, the gate of the P-type MOSFET 9 has a negative voltage with respect to the source, and the gate of the N-type MOSFET 13 has substantially the same voltage with respect to the source. That is, P-type M
OSFET 9 is turned on, and N-type MOSFET 13 is
F, the first circuit 10 is closed, and the capacitance 5 becomes the first voltage in the forward direction where the gate 2 has a positive voltage with respect to the emitter 4.
A charging current flows from the capacitor 8 of, and is charged up to the voltage of the voltage source 7. The first circuit 10 is closed and the second circuit 14
This state is maintained while is open, and the capacitance 5 is charged in the forward direction, so that the gate voltage of the IGBT 1 becomes a positive voltage, so that the IGBT 1 is turned on.

Next, when the control signal 15 is a positive voltage,
The gate of the P-type MOSFET 9 has substantially the same voltage with respect to the source, and the gate of the N-type MOSFET 13 has a positive voltage with respect to the source. That is, since the P-type MOSFET 9 is turned off and the N-type MOSFET 13 is turned on, the first circuit 10 is opened, the second circuit 14 is closed, and the capacitance 5 has the gate 2 with the gate 2 negative with respect to the emitter 4. The charging current flows from the second capacitor 12 in the reverse direction of the voltage, and the charging is performed up to the voltage of the voltage source 11. The first circuit 10 opens,
This state is maintained while the second circuit 14 is closed, and the electrostatic charge 5 is charged in the reverse direction so that the IGB
Since the gate voltage of T1 becomes a negative voltage, IGBT1
FF. To turn off the IGBT 1, it is sufficient that the gate 2 has substantially the same potential as the emitter 4. However, in order to surely keep the OFF state so as not to be erroneously turned on due to the influence of noise or the like, the gate voltage is set to a negative voltage. I do.

Also, by changing the polarity of the control signal 15,
The ON / OFF switching control of the IGBT 1 is performed. At this time, the rate of change of the control signal 15 is limited by an amplifier, and the limited signal is amplified and used, so that the P-type MO is controlled.
O at the time of ON of SFET 9 and N-type MOSFET 13
The first and second circuits 10, 1 and 1 prevent the N resistance from suddenly changing from high impedance to low impedance.
Limit the current starting to flow to 4. As a result, the rate of change of the rise and fall of the capacitance 5, that is, the gate voltage of the IGBT 1 can be controlled.

[0007]

Since the conventional gate drive circuit of the IGBT 1 is configured as described above,
Two voltage sources 7 and 11 are required to charge the capacitance 5 in the forward direction and the reverse direction, and two power supply circuits are required, which hinders miniaturization and cost reduction. In addition, when the IGBT 1 is turned on and turned off, charging power to the capacitance 5 is required. Therefore, when the ON / OFF repetition frequency is high, the power consumption of the gate drive circuit increases. There is a problem that the circuit becomes large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has a single voltage source, so that power consumption can be reduced, and miniaturization and cost reduction can be achieved. And a gate drive circuit for a MOS gate transistor.

[0009]

According to a first aspect of the present invention, there is provided a gate drive circuit, wherein a charge voltage charged to a capacitance between control terminals of a MOS gate transistor is set as a gate voltage, and the MOS gate transistor is connected to the gate drive circuit. ON /
A first circuit configured to connect the capacitance, a first diode, and a first switch in series, the first circuit being opened and closed by operating the first switch; and A second circuit that is formed by connecting a capacitor charged by a voltage source, the capacitance, and a second switch in series, and that opens and closes by operating the second switch; When the second circuit is closed alternately, the charging voltage charged forward in the capacitance when the second circuit is closed is discharged through the first diode when the first circuit is closed. Thereafter, the capacitance is charged in the reverse direction and held by the inductance component present in the first circuit, and the held reverse voltage is charged to the charging voltage of the capacitor when the second circuit is closed. Again with the above electrostatic Those used to charge the amount in the forward direction.

According to a second aspect of the present invention, in the first aspect, the capacitance of the capacitor charged by the voltage source is sufficiently larger than the capacitance between the control terminals of the MOS gate transistors. Things.

According to a third aspect of the present invention, there is provided a gate drive circuit according to the first or second aspect, wherein the first circuit and the second circuit share a predetermined region including a capacitance,
A gate protection resistor connected to the gate of the MOS gate transistor is provided in the shared region, and the gate protection resistor R, the inductance L present in the first circuit, and the capacitance C of the capacitance are determined by One is connected in series in one circuit, and satisfies (4L / C) ≧ R ² .

According to a fourth aspect of the present invention, there is provided a gate drive circuit according to the first or second aspect, wherein the first circuit and the second circuit share a predetermined region including a capacitance,
A resistor R1 for controlling the reverse charging of the capacitance and a resistor R2 serving as a gate protection resistor connected to the gate of the MOS gate transistor are respectively provided in the shared region in parallel with a diode. Are connected to each other in the opposite direction, so that the resistance R1 is connected to the resistance R2 when the capacitance is charged in the first circuit in the reverse direction.
Is used for forward charging the capacitance in the second circuit, and the resistance R1, the inductance L present in the first circuit, and the capacitance C of the capacitance are Connected in series in the first circuit, (4L
/ C) ≧ (R1) ² .

According to a fifth aspect of the present invention, there is provided a gate drive circuit according to any one of the first to fourth aspects.
In this circuit, a saturable reactor is inserted in series between the positive electrode side of the first diode and the capacitance.

According to a sixth aspect of the present invention, there is provided a gate drive circuit according to the fifth aspect, wherein the first circuit and the second circuit share a predetermined area including a capacitance, and
Is connected in series with the first switch, the saturable reactor, and the second switch in the second circuit.

According to a seventh aspect of the present invention, in the gate drive circuit according to the sixth aspect, a delay circuit is connected to the second switch so that the first and second switches are closed after only the second circuit is closed. A period in which both of the circuits are closed is provided. During that period, the charged voltage of the capacitor in the second circuit is discharged to the saturable reactor in the first circuit to store electromagnetic energy in the supersaturated reactor. When only the circuit is closed, the charging voltage charged in the forward direction to the electromagnetic energy and the capacitance stored in the supersaturated reactor is discharged, and then the capacitance is charged in the reverse direction.

According to a eighth aspect of the present invention, there is provided the gate drive circuit according to any one of the first to sixth aspects.
The reactor is inserted in series in the circuit of the above, a delay circuit is connected to the second switch, and after a time when only the second circuit is closed, a period in which both the first and second circuits are closed is provided. During the period, the charging voltage of the capacitor in the second circuit is discharged to the reactor in the first circuit to store electromagnetic energy in the reactor, and thereafter, when only the first circuit is closed, the voltage is stored in the reactor. And discharging the charging voltage charged to the electromagnetic energy and the capacitance in the forward direction, and then charging the capacitance in the reverse direction.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a gate drive circuit of a MOS gate transistor according to a first embodiment of the present invention. In the figure, 16
Are IGBTs 17 as MOS gate transistors,
Reference numerals 18 and 19 denote a gate (G), a collector (C), and an emitter (E) as control terminals of the IGBT 16;
Is the capacitance between the gate 17 and the emitter 19. 21 is a gate protection resistor connected to the gate 17, 2
2, a first diode; 23, a saturable reactor connected to the positive electrode of the first diode 22; 24, an N-type MOSFET as a first switch;
0, gate protection resistor 21, supersaturated reactor 23, first
The diode 22 and the N-type MOSFET 24 are connected in series to form a first circuit that opens and closes by ON / OFF operation of the N-type MOSFET 24.

Reference numeral 25 denotes a capacitor charged by a positive voltage source 26, and 27 denotes a P-type MO as a second switch.
In the SFET, the capacitance 20, the gate protection resistor 21, the P-type MOSFET 27, and the capacitor 25 are connected in series to form a second circuit that is opened and closed by the ON / OFF operation of the P-type MOSFET 27. Reference numeral 28 denotes the capacitance 20 and the gate protection resistor 21 of the first and second circuits.
At the branch point of the shared region including the supersaturated reactor 23, the first diode 22, and the N-type MOSFET 24 in the first circuit via the branch point 28, and the P-type MOSFET 27 and the capacitor in the second circuit. 25 in series. Reference numeral 29 denotes a control signal (A) input to the mutually connected gates of the N-type MOSFET 24 and the P-type MOSFET 27. Further, as shown in the figure, the emitter 19 is grounded and becomes the reference potential of the voltage source 26.

In the gate drive circuit configured as described above, the charging voltage charged in the capacitance 20 between the gate 17 and the emitter 19 of the IGBT 16 is set as the gate voltage of the IGBT 16 and the IGBT is controlled by controlling the gate voltage.
ON / OFF switching control of the BT 16 is performed. FIG. 2 is a current path diagram in each operation of the gate drive circuit according to the first embodiment, and FIG. 3 is a timing chart showing operation waveforms. The operation of this gate drive circuit will be described below with reference to FIGS. explain. In FIG. 2, for the sake of convenience, the gate protection resistor 21 and the supersaturated reactor 23 are provided.
Is omitted. In FIG. 3, A indicates a control signal 29, IG indicates a current flowing through the capacitance 20, VG indicates a voltage charged in the capacitance 20 serving as a gate voltage, and the gate 17 has a positive voltage with respect to the emitter 19. Is the forward direction.

The capacitor 25 is charged by a voltage source 26, and the charged voltage is positive and substantially equal to the output voltage of the voltage source 26. Here, the capacitance of the capacitor 25 is IGBT
It is assumed that the capacitance is sufficiently larger than the capacitance 20 between the gate 17 and the emitter 19. First, when the control signal 29 is IG
When the level is substantially equal to the potential of the emitter 19 of the BT 16, that is, at the “L” level, the gate of the P-type MOSFET 27 has a negative voltage with respect to the source, and the N-type MOSFET 27 has a negative voltage.
The gate of 24 has substantially the same voltage with respect to the source. That is, the P-type MOSFET 27 is turned on, and the N-type MOSFET 27 is turned on.
24 is turned off, and as shown in FIG.
Is closed, the charging current flows from the capacitor 25 to the capacitance 20 in the forward direction, and the capacitor 20 is charged to almost the output voltage of the voltage source 26. The forward charging voltage at this time is V1
And This state is maintained while the second circuit 30a is closed and the first circuit 31 (see FIG. 2B) is open, and the capacitance 20 is charged in the forward direction by the IG.
Since the gate voltage of the BT 16 becomes a positive voltage, the IGBT 1
6 turns ON.

In this state, the control signal 29 is then supplied to the voltage source 26.
At the level substantially equal to the output voltage of the N-type MOSFET, that is, the "H" level, the gate of the N-type MOSFET 24 has a positive voltage with respect to the source, and the gate of the P-type MOSFET 27 has the same voltage with respect to the source. That is, the N-type MOSFET 2
4 turns on and the P-type MOSFET 27 turns off.
As shown in FIG. 2B, the second circuit 30a (FIG.
(See (a)), and the first circuit 31 is closed. As a result, the forward charging of the capacitance 20 in the second circuit 30a is stopped, and the charging voltage of the capacitance 20 is discharged by the first circuit 31. , The capacitance 20 is charged in the opposite direction. In this case, since the supersaturated reactor 23 is provided in the first circuit 31, the inductance component in the first circuit 31 is determined by the inductance of the supersaturated reactor 23 as the air-core reactor after saturation.

The reason why the charged voltage of the discharged capacitance 20 is inverted and charged and oscillated in the opposite direction is that the inductance L in the circuit connected in series in the first circuit 31 and the capacitance When the capacitance C and the gate protection resistor R are (4L /
C) It is necessary to satisfy ≧ R ² . As the gate protection resistance R increases, the reverse charging voltage decreases, and (4 L / C)
= When the R ^2, the charging voltage of reverse direction is zero. The discharge current flows in the same direction until the charging voltage of the capacitance 20 is inverted and becomes maximum in the opposite direction. Further, while attempting to continue the oscillation by reversing the current direction, the oscillation is stopped by the first diode 22, so that the charging voltage of the capacitance 20 is maintained at the maximum value in the opposite direction. The charging voltage in the reverse direction at this time is defined as V2. This state is maintained while the first circuit 31 is closed and the second circuit 30a is open, and the gate voltage of the IGBT 16 becomes negative by charging the capacitance 20 in the reverse direction. Is OFF
I do. To turn off the IGBT 16, the gate 17 only needs to be at substantially the same potential as the emitter 19. I do.

The operation of supersaturated reactor 23 in first circuit 31 when control signal 29 is at "H" level will be described below. When the control signal 29 becomes “H” level, the first
When the circuit 31 is closed and a discharge current flows, the supersaturated reactor 23 blocks the discharge current due to its high inductance. During this time, the voltage of the capacitance 20 is applied to both ends of the supersaturated reactor 23, and the supersaturated reactor 23 saturates to have a low inductance due to the passage of time exceeding a predetermined voltage and time product, and the discharge current flows. Normally, a MOS serving as a switch in the first and second circuits 31, 30a
The operation times of the ON operation and the OFF operation of the FETs 24 and 27 are not the same, and the operation time of the ON operation is slightly faster. Therefore, when the control signal 29 becomes "H" level, both the first and second circuits 31, 30a are momentarily closed. However, the first circuit 31 reduces the current at the start of discharge by the supersaturated reactor. 23, it is possible to completely separate the forward charging operation to the capacitance by the second circuit 30a and the discharging operation by the first circuit 31. Further, when the discharge current flows and the charging voltage of the capacitance 20 is inverted and becomes maximum in the opposite direction, the first diode 2
2 turns off. At this time, normally, a reverse current called a recovery current flows through the diode for a predetermined short period. However, since the recovery current of the first diode 22 can be blocked by the saturable reactor 23, the capacitance 2
The charging voltage in the reverse direction of 0 can be maintained almost completely at the maximum value V2 without decreasing.

Next, when the control signal 29 becomes "L" level again, the N-type MOSFET 24 is turned off and the P-type MOSFET is turned off.
Since the FET 27 is turned on, as shown in FIG.
The second circuit 30b (see FIG. 2B) is closed, and the first circuit 31 is opened. At this time, in the second circuit 30b, the charging voltage of the capacitor 25 is in the same direction as the charging voltage of the capacitance 20 in the opposite direction, so that the charging voltage V2 in the opposite direction held by the capacitance 20 is , Together with the charging voltage of the capacitor 25, is used to charge the capacitance 20 again in the forward direction. The charging current charges the capacitance 20 to almost the output voltage V1 of the voltage source 26, and the IGBT 16 is turned on. .

After that, the control signal 29 becomes "H" level and "H" level.
When the L ″ level is repeated, the state shown in FIG.
The state shown in (c) is repeated. As shown in FIG. 3, when the control signal 29 changes from “H” level to “L” level,
A forward charging current that reaches the maximum value I1 flows for T1 time,
The capacitance 20 is charged with the forward charging voltage V1,
Next, the voltage is maintained for a time T2 until the control signal 29 becomes the “H” level. Then, the control signal 29 becomes "
When the level becomes H level, a reverse charge current flowing to the local maximum value I2 flows for T3, and the reverse charge voltage V2 is charged in the capacitance 20, and then the control signal 29 becomes "L" level. Until that time, the voltage is maintained.

In this embodiment, since the gate drive circuit of the IGBT 16 operates as described above by the control signal 29, the electrostatic energy of the charging voltage charged to the capacitance 20 in the forward direction to turn on the IGBT 16 The IGBT 16 is turned off by charging the capacitance 20 in the reverse direction and holding the charging voltage in the reverse direction. further,
The electrostatic energy of the charging voltage held in the reverse direction is used again to charge the capacitance 20 in the forward direction. Therefore, only one voltage source is required, power consumption can be reduced, and the size and cost of the gate drive circuit can be reduced. Further, since the capacitance of the capacitor 25 charged by the voltage source 26 is sufficiently larger than the capacitance of the capacitance 20, the capacitance 20 can be charged in a short time in the forward direction by using the charging voltage of the capacitor 25, and the IGBT 16 Switching 0
N operation can be speeded up.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing a gate drive circuit of a MOS gate transistor according to a second embodiment of the present invention. As shown in the figure, the capacitance 20 of the first and second circuits in the first embodiment described above.
In place of the gate protection resistor 21, a resistor (R1) 32 and a resistor (R2) 34 having diodes 33 and 35, respectively, are inserted in parallel into the shared region including. Diode 3
3, 35 are disposed in opposite directions to each other, and a resistor (R1) 32
Is used when the capacitance 20 is charged in the reverse direction in the first circuit, and the resistor (R2) 34 is used as a gate protection resistor when the capacitance 20 is charged in the forward direction in the second circuit. .

When the capacitance 20 is charged in the reverse direction in the first circuit, the inductance L, the capacitance C of the capacitance 20 and the resistance (R1) in the circuits connected in series in the first circuit. ) 32 is set such that the resistance (R1) 32 satisfies (4L / C) ≧ (R1) ² . R1 within the above conditions
Can be controlled to control the charging voltage and the rate of change when charging the capacitance 20 in the reverse direction. If the value R1 of the resistor (R1) 32 is substantially 0, the reverse charging voltage has a value substantially equal to the forward charging voltage, and the value R1
Increases, the charging voltage in the reverse direction decreases, and the rate of change is small, resulting in a slow voltage waveform. When the value R1 is (4L /
When C) = (R1) ² is satisfied, the reverse charging voltage becomes substantially equal to zero. The resistance (R2) 34 is the capacitance 2
The rate of change of the gate protection resistance and the charging voltage when 0 is charged in the forward direction is controlled. As the value R2 increases, the rate of change becomes a small and slow voltage waveform.

In this embodiment, a different resistance 32 is applied to the capacitance 20 between the time of forward charging and the time of reverse charging.
By using the resistor 34, desired resistance values can be individually set for forward charging and reverse charging, respectively, and controllability is improved.

The resistance (R1) 32 and the resistance (R2) 3
4 may be a variable resistor, which further improves controllability.

Embodiment 3 The control of the charging voltage and the rate of change when the capacitance 20 is charged in the reverse direction is performed by controlling the inductance L in a circuit connected in series in the first circuit, the capacitance C of the capacitance 20, and the resistance (R1). 32 is (4L /
C) Within the condition that ≧ (R1) ² , the inductance L
Can be set to a desired value. When the inductance L is large, the charging voltage in the reverse direction increases, the rate of change decreases, and a slow voltage waveform is obtained. Conversely, when the inductance L is small, the charging voltage in the reverse direction is small, the rate of change is large, and a steep voltage waveform is obtained.

In the first and second embodiments, the inductance L is the inductance after saturation of the saturable reactor 23. However, even if a reactor having a constant inductance is provided instead of the saturable reactor 23, A reactor may be connected in series with 23.

Embodiment 4 FIG. Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram showing a gate drive circuit of a MOS gate transistor according to a fourth embodiment of the present invention. As shown in the figure, in the first embodiment, the P-type MOSFET 2
7 is connected to a delay circuit 37 composed of a variable resistor 36a and a capacitor 36b to delay the timing at which the control signal 29 is input to the P-type MOSFET 27. Reference numeral 38 denotes a supersaturated reactor 23 in the first circuit.
Is a reactor provided in place of, and is a diode.

FIG. 6 is a timing chart showing operation waveforms of the gate drive circuit according to the fourth embodiment. The operation of the gate drive circuit will be described below with reference to FIGS. In FIG. 6, A is a control signal 29, X is a signal input to the P-type MOSFET 27,
Y is a signal input to the N-type MOSFET 24. When the control signal 29 changes from “L” level to “H” level,
N-type MOSFET 24 of the first circuit is ON from OFF
In addition, the P-type MOSFET 27 of the second circuit changes from 0N to OFF due to the timing delay, and the N-type and P-type MOSFETs 24 and 27 change from the state where only the second circuit is closed.
Are both set to 0N and both the first and second circuits are closed, and thereafter, only the first circuit is closed.

In a period in which both the first and second circuits are closed, the N-type MOSFET of the first circuit is closed.
24, reactor 38, and P-type MOS of the second circuit
The FET 27 is connected in series via a branch point 28.
Thereby, the charging voltage of the capacitor 25 flows from the second circuit side to the first circuit side via the branch point 28, and the electromagnetic energy is accumulated in the reactor 38. During this time, the first
In the above circuit, the forward charging voltage of the capacitance 20 is discharged and decreases. The diode 39 provided in the second circuit, during this time, the current flows from the first circuit side to the second
To the circuit side. Thereafter, when only the first circuit is closed, the current flowing from the second circuit to the first circuit stops. The forward charging voltage of the capacitance 20 continues discharging, and the capacitance 20 is charged in the reverse direction by the inductance component in the first circuit, in this case, the inductance of the reactor 38. At this time, the second circuit The reactor 38 depends on the charging voltage of the capacitor 25 in the
The capacitor 20 is also discharged from the electromagnetic energy stored in the capacitor 20 and charges the capacitance 20 in the reverse direction.

The voltage charged in the capacitance 20 in the reverse direction is held at the local maximum value V2, and then the control signal 29
Becomes "L" level, the N-type MOSFET 24
F, the P-type MOSFET 27 is turned on with a delay in timing, and the charging voltage of the capacitor 25 is in the same direction as the charging voltage in the opposite direction of the capacitance 20 in the second circuit. The reverse charging voltage is used together with the charging voltage of the capacitor 25 to charge the capacitance 20 again in the forward direction.
Is charged to almost the output voltage V1 of the voltage source 26,
The IGBT 16 turns on.

In this embodiment, the delay circuit 37 is provided to generate a period in which both the first and second circuits are closed when the capacitance 20 is charged in the reverse direction.
Since not only the charging voltage charged to the capacitance 20 in the forward direction but also the electromagnetic energy stored in the reactor 38 during the timing delay time of the P-type MOSFET 27 is used, as shown in FIG. Charging current (maximum value I
2) increases, and the reverse charging voltage (maximum value V2) of the capacitance 20 also increases.

By changing the resistance value of the variable resistor 36a of the delay circuit 37, the timing delay time of the P-type MOSFET 27 is adjusted, the amount of electromagnetic energy stored in the reactor 38 is adjusted, and the capacitance 20 Can be controlled in the reverse direction.

In this embodiment, the reactor 3
8, the supersaturated reactor 23 used in the first embodiment may be used.
The electromagnetic energy stored in the supersaturated reactor 23 after saturation can be similarly used. Further, the supersaturated reactor 23
And the reactor 38 can be connected in series, and the electromagnetic energy stored in both the reactors 23 and 38 can be used.

In the first to fourth embodiments, the IGBT 16
IGBT1 has been described using the gate drive circuit of FIG.
However, the present invention is not limited to 6, and can be similarly applied to a MOS gate transistor such as a MOSFET.

[0041]

As described above, according to the first aspect of the present invention,
The gate drive circuit according to the first aspect includes a first circuit that is configured by connecting a capacitance, a first diode, and a first switch in series, and that opens and closes by operating the first switch;
A second circuit that is formed by connecting a capacitor charged by a voltage source, the capacitance, and a second switch in series, and that opens and closes by operating the second switch; When the second circuit is closed alternately, the charging voltage charged forward in the capacitance when the second circuit is closed is discharged through the first diode when the first circuit is closed. Thereafter, the capacitance is charged in the reverse direction and held by the inductance component present in the first circuit, and the held reverse voltage is charged to the charging voltage of the capacitor when the second circuit is closed. At the same time, since the capacitance is used to charge the capacitance again in the forward direction, only one voltage source is required, the power consumption can be reduced, and the size and cost of the gate drive circuit can be reduced.

In the gate drive circuit according to the present invention, the capacitance of the capacitor charged by the voltage source is sufficiently larger than the capacitance between the control terminals of the MOS gate transistor. Therefore, the capacitance can be charged in a short time in the forward direction by using the charging voltage of the capacitor, and the switching operation of the MOS gate transistor can be sped up.

According to a third aspect of the present invention, there is provided a gate drive circuit according to the first or second aspect, wherein the first circuit and the second circuit share a predetermined region including a capacitance, and a MOS gate transistor. The gate protection resistor R, the inductance L existing in the first circuit, and the capacitance C of the capacitance are provided in the shared region. In order to satisfy (4L / C) ≧ R ² , it is possible to discharge the forward charging voltage of the capacitance and charge and hold the capacitor in the reverse direction without fail. The effect of unification and reduction of power consumption is reliably obtained.

According to a fourth aspect of the present invention, there is provided a gate drive circuit according to the first or second aspect, wherein the first circuit and the second circuit share a predetermined area including a capacitance, and Inside, a resistor R1 for controlling the reverse charging of the capacitance and a resistor R2 serving as a gate protection resistor connected to the gate of the MOS gate transistor are respectively provided with diodes and inserted in parallel. By connecting in the direction, the resistor R1 uses the capacitance in the first circuit at the time of reverse charging, and the resistor R2 uses the capacitance at the time of forward charging in the second circuit. And the resistance R2 and the first
The inductance L and the capacitance C of the above-described capacitance are connected in series in the first circuit.
Since (4L / C) ≧ (R2) ² , the resistance in the circuit can be individually set to a desired resistance value at the time of forward charging and at the time of reverse charging, and controllability is improved.

According to a fifth aspect of the present invention, there is provided a gate drive circuit according to any one of the first to fourth aspects, wherein the supersaturation is provided between the positive electrode of the first diode and the capacitance in the first circuit. Since the reactor is inserted in series, the recovery current of the first diode can be blocked by the saturable reactor, the charging voltage charged in the opposite direction to the capacitance can be almost completely held, and the power consumption can be reduced effectively. .

According to a sixth aspect of the present invention, in the gate drive circuit according to the fifth aspect, the first circuit and the second
Circuit shares a predetermined area including the capacitance, the first switch in the first circuit, the saturable reactor, and the second switch in the second circuit are connected in series, The current at the start can be blocked by the supersaturated reactor,
The forward charging operation and the reverse discharging operation for the capacitance can be completely separated, and the reliability is improved.

According to a seventh aspect of the present invention, there is provided a gate drive circuit according to the sixth aspect, wherein a delay circuit is connected to the first switch, and after the second circuit alone is closed, the first switch is closed.
And a period in which both the second circuit and the second circuit are closed. During that period, the charging voltage of the capacitor in the second circuit is changed to the first voltage.
The supersaturated reactor in the circuit is discharged to accumulate electromagnetic energy in the supersaturated reactor. Thereafter, when only the first circuit is closed, the electromagnetic energy and the capacitance stored in the supersaturated reactor are charged in the forward direction. Since the charged voltage is discharged, and then the capacitance is charged in the reverse direction, the charging voltage in the reverse direction of the capacitance can be increased.

According to a eighth aspect of the present invention, in the gate drive circuit according to any one of the first to sixth aspects, a reactor is inserted in series in the first circuit, and a delay circuit is connected to the first switch. And after the closing of only the second circuit,
A period is provided in which both the first and second circuits are closed, and during that period, the charging voltage of the capacitor in the second circuit is discharged to the reactor in the first circuit to store electromagnetic energy in the reactor. Then, when only the first circuit is closed, the charging voltage charged in the forward direction to the electromagnetic energy and the capacitance stored in the reactor is discharged, and then the capacitance is charged in the reverse direction. In addition, the charging voltage in the opposite direction of the capacitance can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a gate drive circuit according to a first embodiment of the present invention.

FIG. 2 is a current path diagram in each operation of the gate drive circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing operation waveforms of the gate drive circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a gate drive circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a gate drive circuit according to a fourth embodiment of the present invention.

FIG. 6 is a timing chart showing operation waveforms of a gate drive circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional gate drive circuit.

[Explanation of symbols]

16 IGBT as MOS gate transistor, 1
7 Gate as control terminal, 19 Emitter as control terminal, 20 Capacitance, 21 Gate protection resistance, 2
2 First diode, 23 Supersaturated reactor, 24
N-type MOSFET as first switch, 25 capacitor, 26 voltage source, 27 P-type MOSFET as second switch, 30a, 30b second circuit, 3
1 first circuit, 32 resistor R1, 33 diode,
34 resistor R2, 35 diode, 37 delay circuit,
38 Reactor.

Claims (8)

(57) [Claims] A charge voltage charged to a capacitance between control terminals of a MOS gate transistor is defined as a gate voltage.
In the gate drive circuit for controlling ON / OFF switching of the MOS gate transistor, the gate drive circuit is configured by connecting the above-mentioned capacitance, a first diode, and a first switch in series, and opens and closes by operating the first switch. A first circuit, and a second circuit that is formed by connecting a capacitor charged by a voltage source, the capacitance, and a second switch in series and that opens and closes by operating the second switch. By alternately closing the first and second circuits, the charging voltage charged in the forward direction to the capacitance when the second circuit is closed, and the first voltage when the first circuit is closed. After that, the capacitance is charged and held in the reverse direction by the inductance component present in the first circuit, and the held reverse voltage is applied when the second circuit is closed. The gate drive circuit, characterized by using to charge again the electrostatic capacitance with the charging voltage of the capacitor in the forward direction. 2. The gate drive circuit according to claim 1, wherein the capacitance of the capacitor charged by the voltage source is sufficiently larger than the capacitance between the control terminals of the MOS gate transistor. 3. The first circuit and the second circuit share a predetermined region including a capacitance, and a gate protection resistor connected to a gate of a MOS gate transistor is provided in the common region. A protection resistor R, an inductance L existing in the first circuit, and a capacitance C of the capacitance;
Are connected in series in the first circuit, and (4L / C) ≧
^3. The gate drive circuit according to claim 1, wherein R ² is satisfied. 4. A first circuit and a second circuit share a predetermined area including a capacitance, and a resistance R1 and a MOS gate for controlling reverse charging of the capacitance are provided in the shared area. A resistor R2 serving as a gate protection resistor connected to the gate of the transistor is provided in parallel with a diode.
By connecting the diodes in opposite directions,
The resistor R1 is used for reverse charging the capacitance in the first circuit, and the resistor R2 is used for forward charging the capacitance in the second circuit. , The inductance L existing in the first circuit, and the capacitance C of the capacitance are connected in series in the first circuit, and satisfy (4L / C) ≧ (R) ^2. 3. The gate drive circuit according to claim 1, wherein: 5. The method according to claim 1, wherein a supersaturated reactor is inserted in series between the positive electrode of the first diode and the capacitance in the first circuit. Gate drive circuit. 6. A first circuit and a second circuit share a predetermined area including capacitance, a first switch, a saturable reactor in the first circuit, and a saturable reactor in the second circuit. The gate drive circuit according to claim 5, wherein the second switch and the second switch are connected in series. 7. A delay circuit is connected to the second switch,
After the closing of only the second circuit, there is provided a period in which both the first and second circuits are closed, during which period the charging voltage of the capacitor in the second circuit is reduced by the supersaturated reactor in the first circuit. And accumulates electromagnetic energy in the supersaturated reactor. Thereafter, when only the first circuit is closed, the charging voltage charged in the forward direction to the electromagnetic energy and the capacitance stored in the supersaturated reactor is discharged. 7. The gate drive circuit according to claim 6, wherein said capacitance is charged in a reverse direction thereafter. 8. A reactor in which a reactor is inserted in series in a first circuit, a delay circuit is connected to a second switch, and after only the second circuit is closed, both the first and second circuits are closed. Is closed, during which period the charging voltage of the capacitor in the second circuit is discharged to the reactor in the first circuit to accumulate electromagnetic energy in the reactor, and then the first
When only the circuit is closed, the charging voltage charged in the forward direction to the electromagnetic energy and the capacitance stored in the reactor is discharged, and then the capacitance is charged in the reverse direction. The gate drive circuit according to claim 1.