JP2561039B2 - Method of connecting semiconductor chip and circuit board - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting electrodes of a semiconductor chip and electrodes of a circuit board.

[0002]

2. Description of the Related Art A conventional method of connecting a semiconductor chip mounting structure using an electroless plating method for connecting an electrode of a semiconductor chip and an electrode of a circuit board is disclosed in, for example, Japanese Patent Laid-Open No. 2-6695.
It is disclosed in Japanese Patent No.

Referring to FIG. 7 (a), a conventional method for connecting a semiconductor chip mounting structure is such that titanium, copper, gold or titanium, platinum, gold, titanium, palladium, gold or the like is formed on a semiconductor element 71. Sputtering with a combination of metals,
The micro bumps 72 are formed by performing plating or the like, and the first insulating layer 73 is formed of an organic film such as polyimide in other regions. Further, on the circuit board 74, metallization of titanium, copper, nickel or the like is performed to form a board electrode 75, and a second insulating layer 76 is formed in the other region by an organic film such as polyimide.

Next, a photocurable resin is dropped onto a part of the semiconductor element 71 and the circuit board 74 except the micro bumps 72 and the substrate electrodes 75 to form a resin layer 77.

Next, the semiconductor element 71 and the circuit board 74 are aligned with each other with a space sufficient for plating later, and after the alignment is completed, ultraviolet rays are irradiated to bond the semiconductor element 71 and the circuit board 74. It is a composition.

Next, referring to FIG. 7B, in this connection method, both the semiconductor element 71 and the circuit board 74 are dipped in a nickel plating solution or a gold plating solution to perform electroless plating, and nickel or gold is used. Forming a connection electrode 78 containing The connection electrodes 78 electrically connect the micro bumps 72 to the substrate electrodes 75.

[0007]

However, the conventional method of connecting the electrode of the semiconductor chip and the electrode of the circuit board using the electroless plating method has the following problems.

First, the positioning of the semiconductor chip,
Since the photo-curable resin is used for supporting and the like, positioning for the curing time and stopping of the supporting device are required, and the index of the device falls.

Further, in order to secure the distance between the semiconductor chip and the circuit board with high accuracy, it is necessary to irradiate the photocurable resin with ultraviolet rays while holding it by the positioning device and the supporting device. I have to.

Furthermore, the photo-curable resin that has struck just below the semiconductor chip, or the photo-curable resin that has been shaded by ultraviolet irradiation due to the mounting location of the semiconductor chip and the relationship with other parts, has uncured and semi-cured parts. Must occur. When the photo-curable resin enters the electroless plating solution in an uncured or semi-cured state, it dissolves in the solution and increases the concentration of organic substances and impurities in the electroless plating solution, rendering the solution unusable. I will end up.

Further, even if the plating is carried out in a state where the concentration of organic substances and impurities is high, good plating cannot be obtained. Even after washing and drying after completion of electroless plating, the plating solution residue remains on the uncured and semi-cured portions of the photocurable resin. K, S, Cl, N, which are harmful to semiconductor chips, remain in the plating solution residue.
Since a and the like are included, the reliability of the semiconductor device is adversely affected.

Secondly, since the non-plating portions of the semiconductor chip and the circuit board are not covered with an insulating material, the material of the semiconductor chip is generally a semiconductor, and thus the non-plating portions (mainly the back surface and end surface of the semiconductor chip). ) Is plated, causing a short circuit. There is no problem if an insulating material is used as the material of the circuit board, but since the silicon circuit board is also a semiconductor, unnecessary parts (mainly the back surface and end surface of the circuit board) are plated,
A short circuit occurs. Further, it is very difficult to completely remove the plating thin film formed on the plating unnecessary portion.

[0013]

A method of connecting a semiconductor chip and a circuit board according to the present invention relates to a method of connecting a semiconductor chip and a circuit board using an electroless plating method for connecting an electrode of the semiconductor chip and an electrode of the circuit board. A step of using a plating resist in the step of positioning and supporting the electrodes of the semiconductor chip and the electrodes of the circuit board, and removing the plating resist after the connection between the electrodes of the semiconductor chip and the circuit board is completed. It is a configuration including.

The method of connecting a semiconductor chip and a circuit board of the present invention can also be configured so as to include a step of forming a first insulator on a portion of the semiconductor chip where plating is unnecessary.

Furthermore, the method of connecting a semiconductor chip and a circuit board according to the present invention may be configured to include a step of forming a second insulating material on a plating unnecessary portion of the circuit board.

Furthermore, the first insulator in the method of connecting a semiconductor chip and a circuit board of the present invention may be the plating resist or a silicon dioxide film, and the method of connecting a semiconductor chip and a circuit board can be used. The second insulator may be the plating resist or the silicon dioxide film.

[0017]

The present invention will be described below with reference to the drawings.

1 to 3 are sectional views of a mounting structure of a semiconductor device processed by the method of connecting a semiconductor chip and a circuit board according to the first embodiment of the present invention.

First, in the connection method of this embodiment, the resist 3 is applied to the back surface of the chip 1 in the wafer whose electrical characteristics have been checked, and pre-curing is performed. Pads 2 are formed on the chip 1 (FIG. 1A). Next, chip 1
Resist 4 is applied to the surface of and the pre-curing is performed (Fig. 1
(B)).

Further, the wafer surface is aligned and both surfaces are exposed and developed to form a resist 4 having a desired height (FIG. 1 (c)). The height of the resist 4 is adjusted to match the distance between the chip 1 and the circuit board 10 formed by electroless plating. Generally, the height is about 10 to 100 μm. Attach the tape 5 to the chip 1 at a temperature of 50 to 60 ° C and a load of 0.5 to
It is attached under the condition of about 5 kg / cm ² (Fig. 1 (d)).

Further, full-cut dicing is performed using a diamond wheel having a blade width of 40 to 50 μm to form the dicing groove 6 (FIG. 2 (a)). After that, a resist is applied to the dicing groove 6 by spin coating or a dispensing method, and exposure, development, and precure are performed,
A resist 7 is formed. Next, dicing is performed using a diamond wheel having a blade width of 20 to 30 μm to form the dicing groove 8 (FIG. 2B). The wafer 1 is divided into individual chips 1 (FIG. 2C).

Through the processing steps up to this point, the chip 1 has the resist 3 formed on the back surface and the resist 7 formed on the end surface thereof, for maintaining the space between the chip 1 and the circuit board 10 for supporting and positioning. The resist 4 is formed.

Therefore, the chip 1 processed by the connection method of this embodiment has two functions, that is, a non-plating function by resist formation on an unnecessary plating portion, a space maintenance between the chip 1 and the circuit board 10, and a supporting and positioning function. It will have a function.

Next, using the mounting machine, the circuit board pads 9 of the circuit board 10 and the pads 2 of the chip 1 are aligned with each other, lightly pressed down, and bonded by using the adhesive force of the resist 4. The distance between the chip 1 and the circuit board 10 is substantially determined by the height of the resist 4 (FIG. 2 (d)).

Next, the completed mounting is immersed in the electroless plating solution 11. Although the immersion time varies depending on the electroless plating solution, the deposition rate, the solution temperature, etc., the immersion time is a little longer than the time obtained by dividing the distance between the circuit board pad 9 and the pad 2 of the chip 1 by the deposition rate. By immersing for a predetermined time, the deposited metal 12 completes the electrical connection (FIG. 3A).

As a final step, the resist 3 formed on the back surface of the chip 1, the resist 7 formed on the end surface, and the resist 4 formed on the front surface are respectively removed by a resist removing agent (Ta = 25 in MEK, for example). 0 ° C.
It is removed in about 5 to 5 minutes) and dried (FIG. 3 (b)).

The effects of the method of connecting the semiconductor chip and the circuit board according to the first embodiment of the present invention described above are as follows.

First of all, since the plating resist having a desired height is provided for positioning and supporting the chip, the distance between the chip and the circuit board can be accurately formed. Further, since the resist can be removed after the connection is completed, the adverse effect of the plating solution residue on the semiconductor device is eliminated.

Secondly, since the non-plating portion of the chip is covered with an insulating material, there is no plating, so that no short circuit occurs in the circuit. Further, the removing step is also unnecessary. Further, since the resist can be removed after the connection is completed, there is no adverse effect on the semiconductor device due to the plating solution residue.

In the description of the connection method of the present embodiment, only the semiconductor chip is described, but it can also be applied to a circuit board, and is particularly effective for a silicon circuit board or a circuit board based on a conductive material.

Next, a method of connecting the semiconductor chip and the circuit board according to the second embodiment of the present invention will be described.

4 to 6 are sectional views of the mounting structure of the semiconductor element processed by the connecting method of this embodiment.

First of all, in the connection method of this embodiment, the back surface of the chip 1 in the wafer with the checked electrical characteristics is oxidized to form the silicon dioxide film 13. The oxidation is performed at a temperature of 500 ° C. or lower in an oxidizing atmosphere (for example, air, O ₂ ). The film thickness of the silicon dioxide film 13 may be at the level of a natural oxide film, and therefore can be easily processed in a short time (FIG. 4A).

Next, the back surface oxidized chip 1 is attached to the attaching tape 5 for full cut dicing. For this adhesive tape, use a material with high heat resistance (Fig. 4
(B)).

Next, full cut dicing is performed using a diamond wheel having a blade width of about 20 to 50 μm to form the dicing groove 6 (FIG. 4 (c)). Further, the silicon dioxide film 13 is heated on the end surface of the chip 1 which has been subjected to full-cut dicing in an oxidizing atmosphere (air, O _2, etc.) (3
It is formed at 50 ° C. or lower) (FIG. 4D).

Thereafter, a dry film for resist 14 is attached to the surface of the chip 1 (FIG. 5A). Further, alignment, exposure, development, and precure are performed to form a resist dry film 14, and the wafer 1 is divided into individual chips 1 (FIG. 5B).

Through the processing steps up to this point, a silicon dioxide film 13 is formed on the back surface and the end surface of the chip 1, and a resist dry film for maintaining the distance between the chip 1 and the circuit board 10 and supporting and positioning the same on the front surface. The film 14 is formed.

Therefore, the chip 1 processed by the connection method of this embodiment has two functions of non-plating by forming a silicon dioxide film on the non-plating portion, maintenance of the space between the chip 1 and the circuit board 10, and support and positioning. It will have two functions (Fig. 5 (c)).

Next, the circuit board pad 9 of the circuit board 10 and the pad 2 of the chip 1 are aligned with each other using a mounting machine, lightly pressed down, and bonded by utilizing the adhesive force of the dry film 14 for resist. . The distance between the chip 1 and the circuit board 10 is determined by the height of the dry film 14 for resist (FIG. 5D).

Then, the completed mounting is immersed in the electroless plating solution 11. Although the immersion time varies depending on the electroless plating solution, the deposition rate, the solution temperature, etc., the immersion time is slightly added to the time obtained by dividing the interval between the circuit board pad 9 and the pad 2 of the chip 1 by the deposition rate. By immersing for a predetermined time, the deposited metal 12 completes the electrical connection (FIG. 6A).

In the final step, the resist dry film 14 is removed with a remover and dried (FIG. 6B).

The effects of the connection method of the second embodiment described above are as follows.

First, since the plating resist dry film having a desired height is provided for positioning and supporting the chip, the interval between the chip and the circuit board can be accurately formed. Further, since the dry film for the plating resist can be removed after the connection is completed, the adverse effect on the semiconductor device due to the residue of the plating solution is eliminated.

Second, since the non-plating portion of the chip is covered with the inorganic insulator of the silicon dioxide film, there is no plating, so that no short circuit occurs in the circuit. Moreover, there is no contamination of the plating solution. Further, the adverse effect on the semiconductor device due to the plating solution residue is eliminated.

Although only the semiconductor chip is described in the description of the connection method of this embodiment, it can be applied to a circuit board, and the effect is particularly great on a silicon circuit board.

Further, in both of the two examples of the present invention, since the contamination of the plating solution can be prevented to a minimum, the life of the solution is prolonged,
Since management can be facilitated, a stable and highly precipitated metal can be obtained.

As a result, a highly reliable connection between the electrode of the chip and the electrode of the circuit board can be obtained.

[0048]

As described above, according to the present invention, a plating resist is used for positioning and supporting the semiconductor chip in the connection method using the electroless plating method for connecting the electrode of the semiconductor chip and the electrode of the circuit board. Since the connection is removed after the connection is completed, the distance between the semiconductor chip and the circuit board can be accurately formed, the contamination of the plating solution can be minimized, and the semiconductor device due to the residue of the plating solution can be removed. It is possible to prevent adverse effects and to increase the mounting index UP of the semiconductor chip after mounting.

Further, since the plating resist and the insulating material such as the oxide film are formed on the portions of the semiconductor chip, the circuit board and the like which do not require plating, the circuit is not short-circuited because the plating is not formed. Further, the step of removing the plating thin film is unnecessary, and the effect of minimizing the contamination of the plating solution is obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip to which a method for connecting a semiconductor chip and a circuit board according to a first embodiment of the present invention is applied, and FIGS. 1A to 1D are cross-sectional views for each process flow. It is a figure.

FIG. 2 is a cross-sectional view of a semiconductor chip to which the method for connecting a semiconductor chip and a circuit board according to the first embodiment of the present invention is applied, and FIGS. 2A to 2D are cross-sectional views for each process flow. It is a figure.

3A and 3B are cross-sectional views of a semiconductor chip and a circuit board to which the method for connecting a semiconductor chip and a circuit board according to the first embodiment of the present invention is applied, and FIGS. It is sectional drawing according to process flow.

FIG. 4 is a cross-sectional view of a semiconductor chip to which a method for connecting a semiconductor chip and a circuit board according to a second embodiment of the present invention is applied, and FIGS. 4A to 4D are cross-sectional views for each process flow. It is a figure.

5A and 5B are cross-sectional views of a semiconductor chip and a circuit board to which a method for connecting a semiconductor chip and a circuit board according to a second embodiment of the present invention is applied, and FIGS. It is sectional drawing according to process flow.

FIG. 6 is a cross-sectional view of a semiconductor chip and a circuit board to which the method for connecting a semiconductor chip and a circuit board according to the first embodiment of the present invention is applied, and FIGS. It is sectional drawing according to process flow.

7A and 7B are cross-sectional views of a semiconductor chip and a circuit board to which a conventional method for connecting a semiconductor chip and a circuit board is applied, and FIGS. 7A and 7B are cross-sectional views for each process flow. is there.

[Explanation of symbols]

 1 Semiconductor Chip 2 Pad 3, 4, 7 Resist 5 Adhesive Tape 6, 8 Dicing Groove 9 Circuit Board Pad 10, 74 Circuit Board 11 Electroless Plating Liquid 12 Precipitated Metal 13 Silicon Dioxide Film 14 Dry Film 71 Semiconductor Element 72 Micro Bump 73 , 76 Insulating film 75 Substrate electrode 77 Resin layer 78 Connection electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Teruo Kusaka, Inventor Teruo Kusaka 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (56) Reference JP-A-48-95773 (JP, A) JP-A 7-86340 (JP, A) JP-A-6-224265 (JP, A) JP-A-2-66953 (JP, A) JP-A-62-296431 (JP, A)

Claims (5)

(57) [Claims] 1. A method of connecting a semiconductor chip electrode and a circuit board electrode using an electroless plating method for connecting a semiconductor chip electrode and a circuit board electrode, wherein a step of positioning the electrode of the semiconductor chip and the electrode of the circuit board, and A method of connecting a semiconductor chip and a circuit board, which comprises using a plating resist in a supporting step, and removing the plating resist after the connection between the electrode of the semiconductor chip and the circuit board is completed. 2. A first portion of the semiconductor chip that does not require plating.
2. The method of connecting a semiconductor chip and a circuit board according to claim 1, further comprising the step of forming the insulating material. 3. The method of connecting a semiconductor chip and a circuit board according to claim 1, further comprising the step of forming a second insulating material on a portion of the circuit board that does not require plating. 4. The method for connecting a semiconductor chip and a circuit board according to claim 2, wherein the first insulator is the plating resist or a silicon dioxide film. 5. The method of connecting a semiconductor chip and a circuit board according to claim 3, wherein the second insulator is the plating resist or a silicon dioxide film.