JP3726115B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3726115B2
JP3726115B2 JP2002144124A JP2002144124A JP3726115B2 JP 3726115 B2 JP3726115 B2 JP 3726115B2 JP 2002144124 A JP2002144124 A JP 2002144124A JP 2002144124 A JP2002144124 A JP 2002144124A JP 3726115 B2 JP3726115 B2 JP 3726115B2
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Japan
Prior art keywords
solder
semiconductor substrate
solder core
core
electrode
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Expired - Fee Related
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JP2002144124A
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JP2003338515A (en
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博之 倉田
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New Japan Radio Co Ltd
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New Japan Radio Co Ltd
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、小型、薄型、軽量、低価格を達成し得る半導体装置の製造方法に関する。さらに詳しくは、微細な電極端子を有しながらリードフレームやインターポーザなどを用いないで、直接マザーボードなどにマウントすることができる構造の半導体装置を安価に得る半導体装置の製造方法に関する。
【０００２】
【従来の技術】
半導体装置は、一般的には、たとえば図１５に示されるように、半導体チップ２１をリードフレームのダイパッド２２にダイボンディングし、電極パッド２１ａとリードフレームのリード２３とを金線２４によりワイヤボンディングして、樹脂でモールドすることによりパッケージ２５を形成することにより製造されている。
【０００３】
また、小型、薄型、軽量化を実現させる手段として、図１６または図１７に示されるように、半導体チップ２１周囲の電極パッド２１ａを半導体チップ２１の平面積全体に分散させてハンダボールを形成するチップサイズパッケージが考えられている。すなわち、図１６に示される例は、セラミック基板、ポリイミドなどの有機材基板、フィルムテープなどからなるインターポーザー２６の一面に配線（図示せず）を形成して半導体チップの電極パッド２１ａとその配線とを金線２４などを用いたワイヤボンディングにより接続し、そのインターポーザー２６の裏面にその配線とそれぞれ接続してハンダボールなどからなる外部電極２７を形成し、半導体チップ２１側を樹脂２５により被覆する技術である。なお、図１７に示される例は、半導体チップ２１の電極パッド２１ａと配線との接続をワイヤボンディングによらないで、電極パッド（図示せず）にハンダバンプ２１ｂを形成し、そのバンプ２１ｂとインターポーザーの配線とを直接接合するもので、他の構成は図１６に示される例と同じである。２８は半導体チップを固定する樹脂層である。
【０００４】
このようなインターポーザーを介在させることにより、半導体チップの周囲に非常に狭い間隔で設けられている電極パッドを半導体チップの面積全体に分散させて回路基板などに直接接続することを可能としている。すなわち、近年の半導体チップの高集積化および小型化に伴い、その電極パッドは半導体チップの周囲に１００〜２００μｍ程度の間隔で設けられている。しかし、半導体装置がマウントされる回路基板の配線は、０.５ｍｍ程度の間隔があり、半導体チップの電極パッドにバンプ電極を形成しても直接回路基板にマウントすることができないが、このインターポーザーを介在させることにより、半導体チップの面積全体に電極を分散させることができるため、直接回路基板にマウントすることができる。
【０００５】
【発明が解決しようとする課題】
前述のように、チップサイズパッケージは小型化が可能であるが、インターポーザーとそれに接続する接続工程が必要となる。このインターポーザーは、リードフレームを使用する半導体装置に比べて、流通量、すなわち生産量が少なく、また、微細な成型が要求されるものもあるため、一般的にコストが高くなる。また、このインターポーザーと半導体チップとのワイヤボンディングは、ワンバイワンの接続であるため、一括処理をすることができないし、一般的な電解工法によるメッキバンプは一括処理をすることができるものの、特にバリアメタルを形成する工程では、ステッパ装置、レジスト塗布・現像・露光装置など高額な設備が必要となる。そのため、チップサイズパッケージは、小型、薄型、軽量化を実現することができるが、コスト高になるという問題がある。
【０００６】
本発明は、このような状況に鑑みてなされたもので、インターポーザーを用いないで、電極間隔を広げ、バリアメタルを無電解メッキ法により形成し、ハンダコア、ハンダバンプ、樹脂封止などの微細成型を簡単に行い、小型、薄型、軽量化を実現しながら、コストを低減することができる半導体装置の製造方法を提供することを目的とする。
【０００７】
【課題を解決するための手段】
本発明による半導体装置の製造方法は、ウェハ状態の半導体基板に電子回路を形成し、該電子回路の電極端子と接続してバンプ電極を形成する所望の場所まで延在する配線を形成した後、全面に被覆膜を形成し、バンプ電極形成場所の前記配線を露出させた再配置された電極パッドを形成し、該電極パッド上に、ニッケル及び金膜を無電解メッキし、熱処理を行い、バリアメタル層を形成し、該バリアメタル層より大きい開口部を有するマスクを用いて、該バリアメタル層上に、ハンダペーストを印刷し、熱処理をすることにより、ハンダコアを形成し、前記半導体基板の前記ハンダコアを形成した面側に、前記ハンダコアの高さより厚く、フィラー入りエポキシ樹脂を印刷し、脱泡して硬化させ、第１の樹脂層を形成し、該第１の樹脂層及び前記ハンダコアを、前記ハンダコアの高さの２／３から１／２となるまで研削して前記ハンダコアを露出させ、前記ハンダコアを露出した面と反対の裏面側の前記半導体基板を研磨して薄くし、該研磨した前記半導体基板の前記裏面側に、フィラー入りエポキシ樹脂を印刷し、脱泡して硬化させ、第２の樹脂層を形成した後、前記露出したハンダコア上に、露出する該ハンダコアより大きい開口部を有するマスクを用いて、ハンダペーストを印刷し、熱処理をすることにより、ハンダバンプを形成し、該ハンダバンプを形成した前記第１の樹脂層、前記半導体基板及び前記第２の樹脂層を切断し、個片化することを特徴とする。
【０００８】
この方法を用いることにより、半導体基板上で電極パッドの間隔を広げ、バリアメタル層を介在させているため、直接半導体基板上にハンダバンプをハンダペーストの印刷と加熱処理とにより形成することができる。しかも、バリア層の形成を無電解メッキにより形成しているため、バンプ電極を形成する必要な電極パッド部分のみにバリアメタル層を形成することができ、従来のように、全面にスパッタリングなどにより設けた金属膜にマスクを形成し、電解メッキを行い、その後、エッチングするというような煩雑な工程を経ることなく形成することができる。さらに、ハンダコアおよびハンダバンプを印刷と加熱処理により形成するため、製造工程が非常に簡略化される。
【０００９】
【発明の実施の形態】
つぎに、図面を参照しながら本発明の半導体装置の製造方法について説明をする。本発明による半導体装置の製造方法は、まず、図１〜３に示されるように、半導体基板１に電子回路を形成し、その電子回路の電極端子２を半導体基板１上で配線４を介して分散することにより再配置された電極パッド４ａを形成し、図４に示されるように、その電極パッド４ａ上に、無電解メッキによりバリアメタル層６を形成し、図５に示されるように、バリアメタル層６上に、ハンダペーストを印刷し熱処理をすることにより、ハンダコア７を形成し、図６に示されるように、半導体基板１のハンダコア７を形成した面側に樹脂を印刷することにより樹脂層８を形成し、図７に示されるように、樹脂層８を研削してハンダコア７を露出させ、図８に示されるように、半導体基板１の裏面側を研磨し、図９に示されるように、半導体基板１の裏面側に裏面樹脂層９を形成し、図１０に示されるように、露出したハンダコア７上に、さらにハンダペーストを印刷し熱処理をすることにより、ハンダバンプ１０を形成し、図１２に示されるように、電子回路の境界部でダイシングをして個片化することにより製造する。
【００１０】
この半導体装置の製造方法について、具体例を交えて、さらに詳細に説明する。まず、図１に示されるように、半導体基板（ウェハ）１にトランジスタやダイオードなどの回路素子（図示せず）を形成して電子回路を形成し、その表面に電子回路の電極端子２を形成すると共に、半導体基板１の表面に絶縁膜３を形成して回路素子を保護している。この状態は、通常の半導体チップにする前のウェハの状態である。なお、図１〜１０においては、１個の電極端子およびその電極端子に接続して設けるバンプ電極が１個の例で示されているが、多数ある電極端子全てについて同時に同様の方法でバンプ電極の形成が行われる。
【００１１】
つぎに、Ａｌ-Ｓｉ（Ｓｉが１ｗｔ％）などからなる電極材料をスパッタ法などにより１μｍ程度の厚さに成膜して、図示しないレジスト膜を設けてパターニングすることにより、図２に示されるように、電極端子２と接続してバンプ電極を形成する所望の場所まで延在する配線４を形成する。その後、図３に示されるように、ＣＶＤ法などによりＳｉＯ2またはＳｉ3Ｎ4などからなる被覆層５を全面に設け、前述の配線４の端部であるバンプ電極形成場所のみが露出するようにパターニングする。この際、バンプ電極形成場所として配線４を露出させた再配置の電極パッド４ａは、他の再配置の電極パッドとの間隔が０.５ｍｍピッチ程度となり、その大きさが１５０μｍφ程度となるように形成する。
【００１２】
つぎに、図４に示されるように、再配置した電極パッド４ａ上にバリアメタル層６を形成する。具体的にはつぎのように行った。まず、再配置した電極パッド４ａ表面の親水性改善のため、脱脂処理を行い、ついで、硫酸または硝酸により表面に付着した酸化膜を除去した。その後、その表面にＺｎ膜を置換メッキした。硝酸によりこのＺｎ膜を一旦除去した後、再度Ｚｎ膜を置換メッキし、電極パッド４ａ表面に均一なＺｎ膜を形成した。つぎに、還元反応により、Ｎｉを５〜９μｍ析出させた。さらに、Ｎｉ表面の酸化を防止するため、置換メッキ法によりＡｕ膜を０.０３μｍ形成することにより、バリアメタル層６を形成した。なお、このバリアメタル層６の直径は１６０μｍであった。ここで、電極パッド４ａは、１回目のＺｎを置換メッキで形成する際のエッチング量が大きい。具体的には、０.７μｍ程度エッチングされた。したがって、配線４の厚さを１μｍ程度以上設けることが必要である。１μｍ以下の場合は、２回目のＺｎを形成するまでに電極パッド４ａの材料が溶けて無くなる場合が生じ、Ｎｉメッキが成長しない場合が生じ、好ましくない。Ａｕ膜を形成後、これらの膜の結合を強めるため、２３０℃、１時間の熱処理を行った。
【００１３】
つぎに、図５に示されるように、バリアメタル層６の表面にハンダコア７を印刷法により形成する。この場合のマスクとして、（マスクの開口面積πｒ2）／（開口部におけるマスク壁面面積２πｒｔ）＝ｒ／２ｔの比率が１／２以上のハンダマスクを使用するのがよかった。これは、（マスクの開口面積）／（マスク壁面面積）が１／２より小さくなると、たとえばマスク開口の直径が３５０μｍφで、マスク厚ｔを２００μｍにした場合、マスク壁面との接着力の方が大きく、マスクにハンダペーストが残っており、転写の再現性が劣るためである。具体的には、直径が３５０μｍφの開口で、厚さｔが１００μｍのマスクを用い、Ｓｎ-Ｃｕ（Ｃｕが２ｗｔ％）のハンダペーストを使用して印刷した。そして、酸素濃度が１０００ｐｐｍ以下の不活性ガス雰囲気で、２６０℃、１０秒以上の熱処理をしてリフローした。ハンダマスクの開口の直径が３５０μｍのとき、マスク厚を変化させた結果、厚さｔが１７５μｍ（すなわちｒ／２ｔ=０.５）まではハンダが転写されることを確認できた。また、リフロー時の酸素濃度が１０００ｐｐｍ以上の場合、ハンダコア７の高さにバラツキが生じた。バリアメタル層の直径が１６０μｍφ、マスク開口の直径が３５０μｍφ、マスク厚ｔが１００μｍのとき、ハンダコア７の高さは１９０±２０μｍの範囲で得られた。
【００１４】
つぎに、図６に示されるように、半導体ウェハ上のアクティブ面（ハンダコア７を形成した面）側に、たとえばフィラー入りエポキシ樹脂を大気圧下で印刷法により塗布して、樹脂層８を形成する。この際、樹脂層８の厚さを規定するウェハ周囲を除いて開口孔を形成した樹脂印刷マスクをつけて行うが、この樹脂印刷マスクは、ハンダコアの高さと同じ厚さから、それより１５０μｍ大きい厚さまでの範囲の厚さとする。印刷後、真空雰囲気下に放置して印刷時に巻き込んだ気泡を脱泡する。その後、高温にして樹脂を硬化させる。具体的には、印刷に用いるマスク厚をハンダコア高さより大きい２５０μｍ厚のものを使用し、１００Ｐａ・ｓの５種対の粘度の樹脂を用いて、６６５Ｐａの減圧下で、２０分間放置して脱泡をした。その後、１００℃で１時間、１５０℃で２時間の熱処理をして樹脂を硬化させた。硬化後の樹脂層８の厚さは２７５±５０μｍであった。なお、使用する樹脂の粘度は、２５、２００、３００、６００Ｐａ・ｓでも使用できることが確認されている。
【００１５】
つぎに、図７に示されるように、半導体基板１のアクティブ面側（表面側）の樹脂層８を研削して、ハンダコア７を露出させる。樹脂の研削量は、樹脂層８の研削面がハンダコア７の高さの２／３〜１／２となるように設定した。具体的には、１９０μｍ高のハンダコア７の場合に、樹脂層の厚さ（研削後のハンダコア５の高さ）が９５〜１２５（１１０±１５）μｍとなるように研削を行った。このとき、露出したハンダコア７の直径は、２００±２０μｍφの範囲で得られた。
【００１６】
つぎに、図８に示されるように、半導体基板１の厚さが１５０〜３５０μｍになるように、半導体基板１の裏面を研磨する。具体的には、６３０μｍ厚の半導体基板１を研磨して、２００±１５μｍ厚にした。その後、図９に示されるように、半導体基板１の裏面側にたとえば、フィラー入りエポキシ樹脂を大気圧下で印刷により塗布して裏面樹脂層９を形成する。この印刷の際に用いるマスクは、裏面樹脂層９の厚さが１５０±１００μｍの厚さになるように選定する。その後、真空圧下に放置して印刷時に巻き込んだ気泡を脱泡した後に、１００℃で１時間、１５０℃で２時間の熱処理を行い、樹脂を硬化させることにより、裏面樹脂層９を形成する。具体例としては、ウェハ周囲以外を開口した１００μｍ厚のマスクを使用して、３０Ｐａ・ｓの粘度の樹脂を印刷により塗布し、６６５Ｐａ以下の真空圧下に２０分間放置して、脱泡を行い気泡を除去した。その後、１００℃で１時間、１５０℃で２時間の熱処理を行い、樹脂を硬化させた。硬化後の裏面樹脂層９の厚さは、１００±４０μｍの範囲で得られた。
【００１７】
つぎに、図１０に示されるように、ハンダコア７上にハンダバンプ１０を印刷法により形成する。ここで、前述のハンダコア７を形成する場合と同様に、ハンダペーストを印刷する際に用いるマスクは、（マスクの開口面積）／（開口部におけるマスク壁面面積）の比率が１／２以上のハンダマスクを使用するのがよかった。そして、酸素濃度が１０００ｐｐｍ以下の不活性ガス雰囲気で、２６０℃、１０秒間の熱処理をしてリフローをした。具体的には、マスクとして、直径が３５０μｍφの開口で、厚さｔが１００μｍのマスクを用い、Ｓｎ-Ｃｕ（Ｃｕが２ｗｔ％）のハンダペーストを使用して印刷した。ハンダマスクの開口の直径が３５０μｍのとき、マスク厚を変化させた結果、前述の場合と同様に、厚さｔが１７５μｍまではハンダが転写されることを確認できたが、２００μｍの厚さでは、マスクにハンダが残っており、転写の再現性に劣った。また、リフロー時の酸素濃度を１０００ｐｐｍ以上にした場合、ハンダバンプ１０の高さにバラツキが生じた。ハンダコア７の直径が２００±２０μｍφ、マスク開口の直径が３５０μｍφ、マスク厚ｔが１００μｍのとき、ハンダバンプ１０の高さは１５０±２０μｍの範囲で得られた。
【００１８】
つぎに、図１１に１２３で示されるように、ウェハの裏面、すなわち裏面樹脂層９の露出面に型名などのマーク１１を付する。このマーキングは、印刷またはレーザ刻印などの方法により行う。半導体基板１がシリコンであれば、印刷でも、レーザ刻印でも構わないが、半導体基板がＧａＡｓのように、レーザ刻印によりＡｓなどの毒物が飛散する恐れのある場合には、印刷法によりマーキングを行う。具体例では、半導体基板がＳｉであるため、レーザによりマーキングを付した。
【００１９】
つぎに、図１２に示されるように、ウェハに多数形成された同じ電子回路をそれぞれその境界部でダイシングをしてチップ化（個片化）する。具体的には、ウェハの裏面側をダイシングテープ１２に貼着し、ダイサー１３によりチップ間を切断する。切断した後も、ダイシングテープ１２に貼着したまま、次工程のテストを行うことができる。
【００２０】
その後、図１３に示されるように、ハンダバンプ１０にテスターのプローブ１４を接触させて、電気試験を行う。このように、梱包直前にテストを行なうことにより、ダイシング時の不良も検出することができ、不良品の流出を完全に防止することができ、信頼性を向上させることができる。また、このように、ダイシングテープ１２に貼着したままテストを行うことにより、各チップは電気的には分離されながら、ダイシングテープ１２上に整列しているため、図１３に示されるように、２個以上のチップを同時にテストすることができる。具体的には、４個のチップを同時にテストすることができた。このように同時に複数個のチップのテストを行うことができるため、テストインデックスを短くすることができ、コストダウンを図ることができた。もちろん、従来通りピックアンドプレスによる１個単位でのテストをすることもできる。
【００２１】
最後に、外観検査を行い、図１４に示されるように、チップごとに収納できる凹部が形成されたキャリアテープ１５の凹部に収納し、キャリアテープを梱包することにより、出荷できる状態になる。
【００２２】
本発明によれば、半導体チップの基板表面に設けられる電極端子を再配置して電極パッド間の間隔を広げ、無電解メッキによるバリアメタル層を形成し、その上にハンダコアおよびハンダバンプを印刷と加熱処理により形成しているため、従来のハンダバンプを電解メッキにより設ける方法に比べて、非常に簡単な製造工程でチップサイズ程度の小型で、直接マザーボードなどにマウントすることができる半導体装置を得ることができる。
【００２３】
なお、前述の具体例では、電極端子を再配置するための配線４として、Ａｌ-Ｓｉ（Ｓｉが１ｗｔ％）を用いる例であったが、配線４として、ＡｕまたはＣｕを用いる場合には、この膜を形成するのに、スパッタ法以外に真空蒸着で成膜してもよい。また、図４のバリアメタル層６の形成工程は以下のように行う。
【００２４】
まず、前述の例と同様に、再配置した電極パッド４ａ表面の親水性改善のため、脱脂処理を行い、ついで、硫酸または硝酸により表面に付着した酸化膜を除去する。その後、電極パッド４ａの表面に、Ｐｄを置換メッキにより成膜する。つぎに、還元反応により、Ｎｉを５〜９μｍ析出させる。さらに、置換メッキ法によりＡｕ膜を０.０３μｍ形成することにより、バリアメタル層６を形成する。なお、このバリアメタル層６の直径は１６０μｍであった。ここで、配線４は、半導体基板１表面の凹凸により断線が生じる場合があるので、１μｍ以上の厚さに形成することが必要である。
【００２５】
【発明の効果】
以上のように、本発明によれば、半導体基板表面にウェハのプロセスを用いて、電極端子の再配置を行って電極パッドの間隔を広げているため、インターポーザを用いることなく、直接マザーボードなどにマウントすることができるチップサイズの非常に小型の半導体装置を得ることができる。しかも、半導体基板表面にハンダコアやハンダバンプを形成する前にバリアメタル層を無電解メッキにより形成し、さらに、ハンダコアやハンダバンプの形成を、印刷と加熱処理とにより行っているため、非常に簡単な設備で、しかも一括処理により製造することができる。その結果、小型、薄型、軽量の半導体装置を非常に安価に得ることができる。
【図面の簡単な説明】
【図１】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図２】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図３】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図４】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図５】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図６】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図７】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図８】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図９】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図１０】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図１１】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図１２】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図１３】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図１４】本発明による製造方法の一実施形態の製造工程を示す説明図である。
【図１５】従来の半導体装置における構造の一例を示す説明図である。
【図１６】従来の半導体装置における構造の一例を示す説明図である。
【図１７】従来の半導体装置における構造の一例を示す説明図である。
【符号の説明】
１ 半導体基板
２ 電極端子
４ 配線
４ａ 電極パッド
６ バリアメタル層
７ ハンダコア
８ 樹脂層
９ 裏面樹脂層
１０ ハンダバンプ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device that can achieve small size, thinness, light weight, and low cost. More specifically, the present invention relates to a method for manufacturing a semiconductor device, which can inexpensively obtain a semiconductor device having a structure that can be directly mounted on a mother board without using a lead frame or an interposer while having fine electrode terminals.
[0002]
[Prior art]
As shown in FIG. 15, for example, a semiconductor device generally has a semiconductor chip 21 bonded to a die pad 22 of a lead frame, and an electrode pad 21a and a lead 23 of a lead frame are wire bonded by a gold wire 24. The package 25 is manufactured by molding with resin.
[0003]
Further, as means for realizing a small size, a thin shape, and a light weight, as shown in FIG. 16 or FIG. 17, the solder pads are formed by dispersing the electrode pads 21 a around the semiconductor chip 21 over the entire plane area of the semiconductor chip 21. Chip size packages are being considered. That is, in the example shown in FIG. 16, a wiring (not shown) is formed on one surface of an interposer 26 made of a ceramic substrate, an organic material substrate such as polyimide, a film tape, etc. Are connected by wire bonding using a gold wire 24 or the like, and connected to the wiring on the back surface of the interposer 26 to form an external electrode 27 made of a solder ball or the like, and the semiconductor chip 21 side is covered with a resin 25 Technology. In the example shown in FIG. 17, the solder pads 21b are formed on the electrode pads (not shown) without connecting the electrode pads 21a and the wirings of the semiconductor chip 21 by wire bonding, and the bumps 21b and the interposer are formed. The other wiring is the same as the example shown in FIG. A resin layer 28 fixes the semiconductor chip.
[0004]
By interposing such an interposer, the electrode pads provided at very narrow intervals around the semiconductor chip can be dispersed over the entire area of the semiconductor chip and directly connected to a circuit board or the like. That is, with the recent high integration and miniaturization of semiconductor chips, the electrode pads are provided around the semiconductor chip at intervals of about 100 to 200 μm. However, the wiring of the circuit board on which the semiconductor device is mounted has an interval of about 0.5 mm, and even if the bump electrode is formed on the electrode pad of the semiconductor chip, it cannot be mounted directly on the circuit board. By interposing the electrode, the electrode can be dispersed over the entire area of the semiconductor chip, so that it can be directly mounted on the circuit board.
[0005]
[Problems to be solved by the invention]
As described above, the chip size package can be reduced in size, but an interposer and a connection process for connecting to the interposer are required. This interposer is generally less expensive than a semiconductor device that uses a lead frame, because it has a small distribution amount, that is, a production amount, and some of them require fine molding. In addition, the wire bonding between the interposer and the semiconductor chip is a one-by-one connection, so batch processing cannot be performed, and plating bumps by a general electrolytic method can be batch processed. In the process of forming metal, expensive equipment such as a stepper device, a resist coating / developing / exposure device is required. For this reason, the chip size package can be reduced in size, thickness, and weight, but there is a problem that the cost increases.
[0006]
The present invention has been made in view of such a situation, and without using an interposer, the electrode interval is widened, a barrier metal is formed by an electroless plating method, and a fine molding such as a solder core, a solder bump, a resin seal, etc. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce the cost while realizing a small size, a thin shape, and a light weight.
[0007]
[Means for Solving the Problems]
In the method of manufacturing a semiconductor device according to the present invention, an electronic circuit is formed on a semiconductor substrate in a wafer state, connected to an electrode terminal of the electronic circuit, and a wiring extending to a desired location for forming a bump electrode is formed. the entire surface to form a coating film, to form a rearranged electrode pad is exposed the wiring of the bump electrode forming location, on the electrode pad, and an electroless plating of nickel and gold film, a heat treatment is performed forming a barrier metal layer, using a mask having an opening larger than the barrier metal layer, on the barrier metal layer, to print the solder paste, by heat treatment, to form a solder core, of the semiconductor substrate on the side formed with said solder core, thicker than the height of said solder core, the filler-containing epoxy resin was printed, and cured by defoaming to form a first resin layer, said first resin layer 及Said solder core, said grinding from 2/3 until 1/2 of the height of the solder core by exposing the solder core, thinned by polishing the semiconductor substrate on the back surface side opposite to the exposed surface of the solder core From the exposed solder core on the exposed solder core , the epoxy resin containing filler is printed on the back side of the polished semiconductor substrate , defoamed and cured to form a second resin layer. A solder bump is formed by printing a solder paste using a mask having a large opening and performing heat treatment , and the first resin layer, the semiconductor substrate, and the second resin layer on which the solder bump is formed are formed. It is characterized by cutting into pieces .
[0008]
By using this method, since the interval between the electrode pads is increased on the semiconductor substrate and the barrier metal layer is interposed, the solder bump can be directly formed on the semiconductor substrate by printing solder paste and heat treatment. Moreover, since the barrier layer is formed by electroless plating, the barrier metal layer can be formed only on the electrode pad portion where the bump electrode is necessary, and it is provided on the entire surface by sputtering or the like as in the prior art. The metal film can be formed without a complicated process of forming a mask, performing electrolytic plating, and then etching. Furthermore, since the solder core and the solder bump are formed by printing and heat treatment, the manufacturing process is greatly simplified.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Next, a method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings. In the method of manufacturing a semiconductor device according to the present invention, first, as shown in FIGS. 1 to 3, an electronic circuit is formed on a semiconductor substrate 1, and electrode terminals 2 of the electronic circuit are connected to the semiconductor substrate 1 via wiring 4. Dispersed electrode pads 4a are formed by dispersing, and as shown in FIG. 4, a barrier metal layer 6 is formed on the electrode pads 4a by electroless plating, as shown in FIG. A solder core 7 is formed on the barrier metal layer 6 by printing a solder paste and heat-treating, and a resin is printed on the surface of the semiconductor substrate 1 on which the solder core 7 is formed, as shown in FIG. The resin layer 8 is formed, and the resin layer 8 is ground to expose the solder core 7 as shown in FIG. 7, and the back side of the semiconductor substrate 1 is polished as shown in FIG. As the semiconductor substrate The backing layer 9 is formed on the back side of, as shown in FIG. 10, on the solder core 7 exposed by further printing was heat treated solder paste to form solder bumps 10, as shown in FIG. 12 Thus, it manufactures by dicing and dicing at the boundary part of an electronic circuit .
[0010]
This semiconductor device manufacturing method will be described in more detail with specific examples. First, as shown in FIG. 1, a circuit element (not shown) such as a transistor or a diode is formed on a semiconductor substrate (wafer) 1 to form an electronic circuit, and an electrode terminal 2 of the electronic circuit is formed on the surface thereof. At the same time, an insulating film 3 is formed on the surface of the semiconductor substrate 1 to protect the circuit elements. This state is the state of the wafer before it is made into a normal semiconductor chip. 1 to 10 show one electrode terminal and one bump electrode provided to be connected to the electrode terminal in one example. However, bump electrodes can be simultaneously formed in the same manner for all the electrode terminals. Is formed.
[0011]
Next, an electrode material made of Al—Si (Si is 1 wt%) or the like is formed to a thickness of about 1 μm by sputtering or the like, and a resist film (not shown) is provided and patterned, and the result is shown in FIG. As described above, the wiring 4 is formed so as to be connected to the electrode terminal 2 and extend to a desired place where the bump electrode is formed. Thereafter, as shown in FIG. 3, a coating layer 5 made of SiO 2 or Si 3 N 4 or the like is provided on the entire surface by CVD or the like so that only the bump electrode forming location which is the end portion of the wiring 4 is exposed. To pattern. At this time, the rearranged electrode pad 4a with the wiring 4 exposed as a bump electrode formation location is spaced about 0.5 mm from the other rearranged electrode pads, and the size is about 150 μmφ. Form.
[0012]
Next, as shown in FIG. 4, a barrier metal layer 6 is formed on the rearranged electrode pad 4a. Specifically, it was performed as follows. First, degreasing treatment was performed to improve the hydrophilicity of the rearranged electrode pad 4a surface, and then the oxide film adhered to the surface was removed with sulfuric acid or nitric acid. Thereafter, a Zn film was substitution plated on the surface. After removing this Zn film once with nitric acid, the Zn film was subjected to substitution plating again to form a uniform Zn film on the surface of the electrode pad 4a. Next, 5 to 9 μm of Ni was deposited by a reduction reaction. Furthermore, in order to prevent the Ni surface from being oxidized, the barrier metal layer 6 was formed by forming 0.03 μm of an Au film by a displacement plating method. The diameter of the barrier metal layer 6 was 160 μm. Here, the electrode pad 4a has a large etching amount when the first Zn is formed by substitution plating. Specifically, it was etched by about 0.7 μm. Therefore, it is necessary to provide the wiring 4 with a thickness of about 1 μm or more. When the thickness is 1 μm or less, the material of the electrode pad 4a may be melted and lost before forming the second Zn, and the Ni plating may not grow, which is not preferable. After forming the Au film, heat treatment was performed at 230 ° C. for 1 hour in order to strengthen the bond between these films.
[0013]
Next, as shown in FIG. 5, a solder core 7 is formed on the surface of the barrier metal layer 6 by a printing method. As a mask in this case, it is preferable to use a solder mask having a ratio of (mask opening area πr 2 ) / (mask wall surface area 2πrt at opening) = r / 2t of 1/2 or more. When (mask opening area) / (mask wall surface area) is smaller than 1/2, for example, when the mask opening diameter is 350 μmφ and the mask thickness t is 200 μm, the adhesive strength with the mask wall surface is greater. This is because the solder paste remains on the mask and transfer reproducibility is poor. Specifically, printing was performed using Sn—Cu (Cu is 2 wt%) solder paste using a mask having a diameter of 350 μmφ and a thickness t of 100 μm. And it reflowed by heat-processing for 10 second or more at 260 degreeC in the inert gas atmosphere whose oxygen concentration is 1000 ppm or less. As a result of changing the mask thickness when the diameter of the opening of the solder mask was 350 μm, it was confirmed that the solder was transferred until the thickness t was 175 μm (ie, r / 2t = 0.5). Further, when the oxygen concentration during reflow was 1000 ppm or more, the height of the solder core 7 varied. When the diameter of the barrier metal layer was 160 μmφ, the diameter of the mask opening was 350 μmφ, and the mask thickness t was 100 μm, the height of the solder core 7 was obtained in the range of 190 ± 20 μm.
[0014]
Next, as shown in FIG. 6, a resin layer 8 is formed on the active surface (surface on which the solder core 7 is formed) on the semiconductor wafer by applying, for example, an epoxy resin with filler under atmospheric pressure by a printing method. To do. At this time, a resin printing mask in which an opening hole is formed except for the periphery of the wafer that defines the thickness of the resin layer 8 is attached. This resin printing mask is 150 μm larger than the same thickness as the solder core. The thickness is in the range up to the thickness. After printing, it is left in a vacuum atmosphere to defoam air bubbles that are involved during printing. Thereafter, the resin is cured at a high temperature. Specifically, a mask having a thickness of 250 μm larger than the height of the solder core is used for printing, and the resin is removed by leaving it for 20 minutes under a reduced pressure of 665 Pa using five types of resins of 100 Pa · s. Foamed. Thereafter, the resin was cured by heat treatment at 100 ° C. for 1 hour and 150 ° C. for 2 hours. The thickness of the resin layer 8 after curing was 275 ± 50 μm. It has been confirmed that the resin used can be used at a viscosity of 25, 200, 300, 600 Pa · s.
[0015]
Next, as shown in FIG. 7, the resin layer 8 on the active surface side (surface side) of the semiconductor substrate 1 is ground to expose the solder core 7. The grinding amount of the resin was set so that the grinding surface of the resin layer 8 was 2/3 to 1/2 of the height of the solder core 7. Specifically, in the case of the solder core 7 having a height of 190 μm, grinding was performed such that the thickness of the resin layer (the height of the solder core 5 after grinding) was 95 to 125 (110 ± 15) μm. At this time, the diameter of the exposed solder core 7 was obtained in a range of 200 ± 20 μmφ.
[0016]
Next, as shown in FIG. 8, the back surface of the semiconductor substrate 1 is polished so that the thickness of the semiconductor substrate 1 becomes 150 to 350 μm. Specifically, the semiconductor substrate 1 having a thickness of 630 μm was polished to a thickness of 200 ± 15 μm. After that, as shown in FIG. 9, for example, a filler-filled epoxy resin is applied to the back surface side of the semiconductor substrate 1 by printing under atmospheric pressure to form the back surface resin layer 9. The mask used in this printing is selected so that the thickness of the back surface resin layer 9 is 150 ± 100 μm. Then, after leaving the air bubble under vacuum pressure to defoam bubbles, a heat treatment is performed at 100 ° C. for 1 hour and 150 ° C. for 2 hours to cure the resin, thereby forming the back resin layer 9. As a specific example, using a 100 μm-thick mask with openings other than the periphery of the wafer, a resin having a viscosity of 30 Pa · s is applied by printing, and left for 20 minutes under a vacuum pressure of 665 Pa or less to perform defoaming and air bubbles Was removed. Thereafter, heat treatment was performed at 100 ° C. for 1 hour and at 150 ° C. for 2 hours to cure the resin. The thickness of the back surface resin layer 9 after curing was obtained in the range of 100 ± 40 μm.
[0017]
Next, as shown in FIG. 10, solder bumps 10 are formed on the solder core 7 by a printing method. Here, as in the case of forming the solder core 7 described above, the mask used for printing the solder paste is a solder whose ratio of (mask opening area) / (mask wall surface area in the opening) is 1/2 or more. It was good to use a mask. Then, reflow was performed by heat treatment at 260 ° C. for 10 seconds in an inert gas atmosphere having an oxygen concentration of 1000 ppm or less. Specifically, a mask having a diameter of 350 μmφ and a thickness t of 100 μm was used as a mask, and printing was performed using a solder paste of Sn—Cu (Cu is 2 wt%). As a result of changing the mask thickness when the diameter of the solder mask opening was 350 μm, it was confirmed that the solder was transferred up to a thickness t of 175 μm as in the case described above. Solder remained on the mask, and transfer reproducibility was poor. In addition, when the oxygen concentration during reflow was set to 1000 ppm or more, the height of the solder bumps 10 varied. When the diameter of the solder core 7 was 200 ± 20 μmφ, the diameter of the mask opening was 350 μmφ, and the mask thickness t was 100 μm, the height of the solder bump 10 was obtained in the range of 150 ± 20 μm.
[0018]
Next, as shown by 123 in FIG. 11, a mark 11 such as a model name is attached to the back surface of the wafer, that is, the exposed surface of the back surface resin layer 9. This marking is performed by a method such as printing or laser marking. If the semiconductor substrate 1 is silicon, it may be printed or laser-engraved. However, if the semiconductor substrate is GaAs and the like, toxic substances such as As may be scattered by laser engraving, marking is performed by a printing method. . In the specific example, since the semiconductor substrate is Si, marking is performed by a laser.
[0019]
Next, as shown in FIG. 12, the same electronic circuit formed in large numbers on the wafer is diced at the boundary portions to form chips (individualized). Specifically, the back side of the wafer is attached to the dicing tape 12, and the chips are cut by the dicer 13. Even after cutting, the test of the next process can be performed while being stuck to the dicing tape 12.
[0020]
Thereafter, as shown in FIG. 13, a tester probe 14 is brought into contact with the solder bump 10 to perform an electrical test. In this way, by performing the test immediately before packing, it is possible to detect a defect during dicing, to completely prevent the outflow of defective products, and to improve reliability. Further, by performing the test while being adhered to the dicing tape 12 in this way, each chip is aligned on the dicing tape 12 while being electrically separated, so as shown in FIG. Two or more chips can be tested simultaneously. Specifically, four chips could be tested simultaneously. Since a plurality of chips can be tested simultaneously in this way, the test index can be shortened and the cost can be reduced. Of course, it is also possible to perform a test in a single unit by pick and press as usual.
[0021]
Finally, an appearance inspection is performed, and as shown in FIG. 14, the carrier tape 15 is housed in a recessed portion in which a recessed portion that can be housed for each chip is formed, and the carrier tape is packed to be ready for shipment.
[0022]
According to the present invention, the electrode terminals provided on the substrate surface of the semiconductor chip are rearranged to widen the space between the electrode pads, the barrier metal layer is formed by electroless plating, and the solder core and the solder bump are printed and heated thereon. Since it is formed by processing, it is possible to obtain a semiconductor device that can be directly mounted on a mother board or the like with a very small manufacturing process compared to the conventional method of providing solder bumps by electrolytic plating. it can.
[0023]
In the above specific example, Al—Si (Si is 1 wt%) is used as the wiring 4 for rearranging the electrode terminals. However, when Au or Cu is used as the wiring 4, In order to form this film, it may be formed by vacuum deposition in addition to the sputtering method. Moreover, the formation process of the barrier metal layer 6 of FIG. 4 is performed as follows.
[0024]
First, in the same manner as in the above-described example, a degreasing process is performed to improve the hydrophilicity of the surface of the rearranged electrode pad 4a, and then the oxide film attached to the surface is removed with sulfuric acid or nitric acid. Thereafter, Pd is deposited on the surface of the electrode pad 4a by displacement plating. Next, 5 to 9 μm of Ni is deposited by a reduction reaction. Further, the barrier metal layer 6 is formed by forming 0.03 μm of Au film by displacement plating. The diameter of the barrier metal layer 6 was 160 μm. Here, since the wire 4 may be disconnected due to unevenness on the surface of the semiconductor substrate 1, it is necessary to form the wire 4 with a thickness of 1 μm or more.
[0025]
【The invention's effect】
As described above, according to the present invention, since the electrode terminals are rearranged by using the wafer process on the surface of the semiconductor substrate and the distance between the electrode pads is widened, it is directly applied to the mother board or the like without using the interposer. A very small semiconductor device having a chip size that can be mounted can be obtained. In addition, the barrier metal layer is formed by electroless plating before forming the solder core or solder bump on the surface of the semiconductor substrate, and the solder core or solder bump is formed by printing and heat treatment. Moreover, it can be manufactured by batch processing. As a result, a small, thin, and lightweight semiconductor device can be obtained at a very low cost.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a manufacturing process of an embodiment of a manufacturing method according to the present invention.
FIG. 2 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
FIG. 3 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
FIG. 4 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
FIG. 5 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
FIG. 6 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
FIG. 7 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
FIG. 8 is an explanatory diagram showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
FIG. 9 is an explanatory diagram showing a manufacturing process of an embodiment of the manufacturing method according to the present invention.
FIG. 10 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
FIG. 11 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
FIG. 12 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
FIG. 13 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
FIG. 14 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention.
FIG. 15 is an explanatory diagram showing an example of a structure in a conventional semiconductor device.
FIG. 16 is an explanatory diagram showing an example of a structure in a conventional semiconductor device.
FIG. 17 is an explanatory diagram showing an example of a structure in a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Electrode terminal 4 Wiring 4a Electrode pad 6 Barrier metal layer 7 Solder core 8 Resin layer 9 Back surface resin layer 10 Solder bump

Claims (1)

ウェハ状態の半導体基板に電子回路を形成し、該電子回路の電極端子と接続してバンプ電極を形成する所望の場所まで延在する配線を形成した後、全面に被覆膜を形成し、バンプ電極形成場所の前記配線を露出させた再配置された電極パッドを形成し、
該電極パッド上に、ニッケル及び金膜を無電解メッキし、熱処理を行い、バリアメタル層を形成し、
該バリアメタル層より大きい開口部を有するマスクを用いて、該バリアメタル層上に、ハンダペーストを印刷し、熱処理をすることにより、ハンダコアを形成し、
前記半導体基板の前記ハンダコアを形成した面側に、前記ハンダコアの高さより厚く、フィラー入りエポキシ樹脂を印刷し、脱泡して硬化させ、第１の樹脂層を形成し、
該第１の樹脂層及び前記ハンダコアを、前記ハンダコアの高さの２／３から１／２となるまで研削して前記ハンダコアを露出させ、
前記ハンダコアを露出した面と反対の裏面側の前記半導体基板を研磨して薄くし、
該研磨した前記半導体基板の前記裏面側に、フィラー入りエポキシ樹脂を印刷し、脱泡して硬化させ、第２の樹脂層を形成した後、
前記露出したハンダコア上に、露出する該ハンダコアより大きい開口部を有するマスクを用いて、ハンダペーストを印刷し、熱処理をすることにより、ハンダバンプを形成し、
該ハンダバンプを形成した前記第１の樹脂層、前記半導体基板及び前記第２の樹脂層を切断し、個片化することを特徴とする半導体装置の製造方法。An electronic circuit is formed on a semiconductor substrate in a wafer state, a wiring extending to a desired location for forming a bump electrode by connecting with an electrode terminal of the electronic circuit is formed, a coating film is formed on the entire surface, and a bump is formed. Forming a rearranged electrode pad that exposes the wiring at the electrode formation location ;
Electroless plating of nickel and gold film on the electrode pad , heat treatment is performed, and a barrier metal layer is formed ,
Using a mask having an opening larger than the barrier metal layer, a solder paste is printed on the barrier metal layer , and heat treatment is performed, thereby forming a solder core .
On the side of the formation of the solder core of the semiconductor substrate, thicker than the height of said solder core, the filler-containing epoxy resin was printed, and cured by defoaming to form a first resin layer,
The first resin layer and the solder core, by grinding from 2/3 until 1/2 of the height of the solder core to expose the solder core,
Polishing and thinning the semiconductor substrate on the back side opposite to the exposed surface of the solder core ,
After the filler-filled epoxy resin is printed on the back side of the polished semiconductor substrate , defoamed and cured to form a second resin layer ,
A solder bump is formed on the exposed solder core by printing a solder paste using a mask having an opening larger than the exposed solder core, and performing heat treatment ,
A method of manufacturing a semiconductor device, wherein the first resin layer, the semiconductor substrate, and the second resin layer on which the solder bumps are formed are cut into individual pieces .
JP2002144124A 2002-05-20 2002-05-20 Manufacturing method of semiconductor device Expired - Fee Related JP3726115B2 (en)

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