JP2003338515A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JP2003338515A
JP2003338515A JP2002144124A JP2002144124A JP2003338515A JP 2003338515 A JP2003338515 A JP 2003338515A JP 2002144124 A JP2002144124 A JP 2002144124A JP 2002144124 A JP2002144124 A JP 2002144124A JP 2003338515 A JP2003338515 A JP 2003338515A
Authority
JP
Japan
Prior art keywords
solder
semiconductor substrate
forming
core
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002144124A
Other languages
Japanese (ja)
Other versions
JP3726115B2 (en
Inventor
Hiroyuki Kurata
博之 倉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2002144124A priority Critical patent/JP3726115B2/en
Publication of JP2003338515A publication Critical patent/JP2003338515A/en
Application granted granted Critical
Publication of JP3726115B2 publication Critical patent/JP3726115B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To expand a distance between electrodes without using an interposer to form a barrier metal by an electroless plating method, to facilitate the fine molding of a solder core, a solder bump, resin sealing or the like, and to reduce a size, thickness, and weight while reducing a cost. <P>SOLUTION: An electronic circuit is formed on a semiconductor substrate 1. An electrode terminal 2 of the electronic circuit is distributed on the semiconductor substrate 1 via wiring 4 to form a relocated electrode pad 4a. On the electrode pad 4a, a barrier metal layer 6 is formed by an electroless plating method. Solder paste is printed on the barrier metal layer 6 and is heat-treated to form the solder core 7. A resin layer 8 is formed on the side face of the semiconductor substrate 1 with a solder core 7 formed thereon. The resin layer 8 is ground to expose the solder core 7, and a rear face resin layer 9 is formed on the rear face of the semiconductor substrate 1. On an exposed solder core 7, solder paste is printed again and is heat-treated to form a solder bump 10. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】 【０００１】 【発明の属する技術分野】本発明は、小型、薄型、軽
量、低価格を達成し得る半導体装置の製造方法に関す
る。さらに詳しくは、微細な電極端子を有しながらリー
ドフレームやインターポーザなどを用いないで、直接マ
ザーボードなどにマウントすることができる構造の半導
体装置を安価に得る半導体装置の製造方法に関する。 【０００２】 【従来の技術】半導体装置は、一般的には、たとえば図
１５に示されるように、半導体チップ２１をリードフレ
ームのダイパッド２２にダイボンディングし、電極パッ
ド２１ａとリードフレームのリード２３とを金線２４に
よりワイヤボンディングして、樹脂でモールドすること
によりパッケージ２５を形成することにより製造されて
いる。 【０００３】また、小型、薄型、軽量化を実現させる手
段として、図１６または図１７に示されるように、半導
体チップ２１周囲の電極パッド２１ａを半導体チップ２
１の平面積全体に分散させてハンダボールを形成するチ
ップサイズパッケージが考えられている。すなわち、図
１６に示される例は、セラミック基板、ポリイミドなど
の有機材基板、フィルムテープなどからなるインターポ
ーザー２６の一面に配線（図示せず）を形成して半導体
チップの電極パッド２１ａとその配線とを金線２４など
を用いたワイヤボンディングにより接続し、そのインタ
ーポーザー２６の裏面にその配線とそれぞれ接続してハ
ンダボールなどからなる外部電極２７を形成し、半導体
チップ２１側を樹脂２５により被覆する技術である。な
お、図１７に示される例は、半導体チップ２１の電極パ
ッド２１ａと配線との接続をワイヤボンディングによら
ないで、電極パッド（図示せず）にハンダバンプ２１ｂ
を形成し、そのバンプ２１ｂとインターポーザーの配線
とを直接接合するもので、他の構成は図１６に示される
例と同じである。２８は半導体チップを固定する樹脂層
である。 【０００４】このようなインターポーザーを介在させる
ことにより、半導体チップの周囲に非常に狭い間隔で設
けられている電極パッドを半導体チップの面積全体に分
散させて回路基板などに直接接続することを可能として
いる。すなわち、近年の半導体チップの高集積化および
小型化に伴い、その電極パッドは半導体チップの周囲に
１００〜２００μｍ程度の間隔で設けられている。しか
し、半導体装置がマウントされる回路基板の配線は、
０.５ｍｍ程度の間隔があり、半導体チップの電極パッ
ドにバンプ電極を形成しても直接回路基板にマウントす
ることができないが、このインターポーザーを介在させ
ることにより、半導体チップの面積全体に電極を分散さ
せることができるため、直接回路基板にマウントするこ
とができる。 【０００５】 【発明が解決しようとする課題】前述のように、チップ
サイズパッケージは小型化が可能であるが、インターポ
ーザーとそれに接続する接続工程が必要となる。このイ
ンターポーザーは、リードフレームを使用する半導体装
置に比べて、流通量、すなわち生産量が少なく、また、
微細な成型が要求されるものもあるため、一般的にコス
トが高くなる。また、このインターポーザーと半導体チ
ップとのワイヤボンディングは、ワンバイワンの接続で
あるため、一括処理をすることができないし、一般的な
電解工法によるメッキバンプは一括処理をすることがで
きるものの、特にバリアメタルを形成する工程では、ス
テッパ装置、レジスト塗布・現像・露光装置など高額な
設備が必要となる。そのため、チップサイズパッケージ
は、小型、薄型、軽量化を実現することができるが、コ
スト高になるという問題がある。 【０００６】本発明は、このような状況に鑑みてなされ
たもので、インターポーザーを用いないで、電極間隔を
広げ、バリアメタルを無電解メッキ法により形成し、ハ
ンダコア、ハンダバンプ、樹脂封止などの微細成型を簡
単に行い、小型、薄型、軽量化を実現しながら、コスト
を低減することができる半導体装置の製造方法を提供す
ることを目的とする。 【０００７】 【課題を解決するための手段】本発明による半導体装置
の製造方法は、半導体基板に電子回路を形成し、該電子
回路の電極端子を前記半導体基板上で配線を介して分散
することにより再配置された電極パッドを形成する工程
と、該電極パッド上に、無電解メッキによりバリアメタ
ル層を形成する工程と、該バリアメタル層上に、ハンダ
ペーストを印刷し熱処理をすることにより、ハンダコア
を形成する工程と、前記半導体基板の該ハンダコアを形
成した面側に樹脂層を形成する工程と、該樹脂層を研削
して前記ハンダコアを露出させる工程と、前記半導体基
板の前記ハンダコアを露出した面と反対の裏面側に樹脂
層を形成する工程と、前記該露出したハンダコア上に、
さらにハンダペーストを印刷し熱処理をすることによ
り、ハンダバンプを形成する工程とを含むことを特徴と
する。 【０００８】この方法を用いることにより、半導体基板
上で電極パッドの間隔を広げ、バリアメタル層を介在さ
せているため、直接半導体基板上にハンダバンプをハン
ダペーストの印刷と加熱処理とにより形成することがで
きる。しかも、バリア層の形成を無電解メッキにより形
成しているため、バンプ電極を形成する必要な電極パッ
ド部分のみにバリアメタル層を形成することができ、従
来のように、全面にスパッタリングなどにより設けた金
属膜にマスクを形成し、電解メッキを行い、その後、エ
ッチングするというような煩雑な工程を経ることなく形
成することができる。さらに、ハンダコアおよびハンダ
バンプを印刷と加熱処理により形成するため、製造工程
が非常に簡略化される。 【０００９】 【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体装置の製造方法について説明をする。本発明
による半導体装置の製造方法は、まず、図１〜３に示さ
れるように、半導体基板１に電子回路を形成し、その電
子回路の電極端子２を半導体基板１上で配線４を介して
分散することにより再配置された電極パッド４ａを形成
し、図４に示されるように、その電極パッド４ａ上に、
無電解メッキによりバリアメタル層６を形成し、図５に
示されるように、バリアメタル層６上に、ハンダペース
トを印刷し熱処理をすることにより、ハンダコア７を形
成し、図６に示されるように、半導体基板１のハンダコ
ア７を形成した面側に樹脂を印刷することにより樹脂層
８を形成し、図７に示されるように、樹脂層８を研削し
てハンダコア７を露出させ、図９に示されるように、半
導体基板１の裏面側に裏面樹脂層９を形成し、図１０に
示されるように、露出したハンダコア７上に、さらにハ
ンダペーストを印刷し熱処理をすることにより、ハンダ
バンプ１０を形成することにより製造する。 【００１０】この半導体装置の製造方法について、具体
例を交えて、さらに詳細に説明する。まず、図１に示さ
れるように、半導体基板（ウェハ）１にトランジスタや
ダイオードなどの回路素子（図示せず）を形成して電子
回路を形成し、その表面に電子回路の電極端子２を形成
すると共に、半導体基板１の表面に絶縁膜３を形成して
回路素子を保護している。この状態は、通常の半導体チ
ップにする前のウェハの状態である。なお、図１〜１０
においては、１個の電極端子およびその電極端子に接続
して設けるバンプ電極が１個の例で示されているが、多
数ある電極端子全てについて同時に同様の方法でバンプ
電極の形成が行われる。 【００１１】つぎに、Ａｌ-Ｓｉ（Ｓｉが１ｗｔ％）な
どからなる電極材料をスパッタ法などにより１μｍ程度
の厚さに成膜して、図示しないレジスト膜を設けてパタ
ーニングすることにより、図２に示されるように、電極
端子２と接続してバンプ電極を形成する所望の場所まで
延在する配線４を形成する。その後、図３に示されるよ
うに、ＣＶＤ法などによりＳｉＯ2またはＳｉ3Ｎ4など
からなる被覆層５を全面に設け、前述の配線４の端部で
あるバンプ電極形成場所のみが露出するようにパターニ
ングする。この際、バンプ電極形成場所として配線４を
露出させた再配置の電極パッド４ａは、他の再配置の電
極パッドとの間隔が０.５ｍｍピッチ程度となり、その
大きさが１５０μｍφ程度となるように形成する。 【００１２】つぎに、図４に示されるように、再配置し
た電極パッド４ａ上にバリアメタル層６を形成する。具
体的にはつぎのように行った。まず、再配置した電極パ
ッド４ａ表面の親水性改善のため、脱脂処理を行い、つ
いで、硫酸または硝酸により表面に付着した酸化膜を除
去した。その後、その表面にＺｎ膜を置換メッキした。
硝酸によりこのＺｎ膜を一旦除去した後、再度Ｚｎ膜を
置換メッキし、電極パッド４ａ表面に均一なＺｎ膜を形
成した。つぎに、還元反応により、Ｎｉを５〜９μｍ析
出させた。さらに、Ｎｉ表面の酸化を防止するため、置
換メッキ法によりＡｕ膜を０.０３μｍ形成することに
より、バリアメタル層６を形成した。なお、このバリア
メタル層６の直径は１６０μｍであった。ここで、電極
パッド４ａは、１回目のＺｎを置換メッキで形成する際
のエッチング量が大きい。具体的には、０.７μｍ程度
エッチングされた。したがって、配線４の厚さを１μｍ
程度以上設けることが必要である。１μｍ以下の場合
は、２回目のＺｎを形成するまでに電極パッド４ａの材
料が溶けて無くなる場合が生じ、Ｎｉメッキが成長しな
い場合が生じ、好ましくない。Ａｕ膜を形成後、これら
の膜の結合を強めるため、２３０℃、１時間の熱処理を
行った。 【００１３】つぎに、図５に示されるように、バリアメ
タル層６の表面にハンダコア７を印刷法により形成す
る。この場合のマスクとして、（マスクの開口面積πｒ
2）／（開口部におけるマスク壁面面積２πｒｔ）＝ｒ
／２ｔの比率が１／２以上のハンダマスクを使用するの
がよかった。これは、（マスクの開口面積）／（マスク
壁面面積）が１／２より小さくなると、たとえばマスク
開口の直径が３５０μｍφで、マスク厚ｔを２００μｍ
にした場合、マスク壁面との接着力の方が大きく、マス
クにハンダペーストが残っており、転写の再現性が劣る
ためである。具体的には、直径が３５０μｍφの開口
で、厚さｔが１００μｍのマスクを用い、Ｓｎ-Ｃｕ
（Ｃｕが２ｗｔ％）のハンダペーストを使用して印刷し
た。そして、酸素濃度が１０００ｐｐｍ以下の不活性ガ
ス雰囲気で、２６０℃、１０秒以上の熱処理をしてリフ
ローした。ハンダマスクの開口の直径が３５０μｍのと
き、マスク厚を変化させた結果、厚さｔが１７５μｍ
（すなわちｒ／２ｔ=０.５）まではハンダが転写される
ことを確認できた。また、リフロー時の酸素濃度が１０
００ｐｐｍ以上の場合、ハンダコア７の高さにバラツキ
が生じた。バリアメタル層の直径が１６０μｍφ、マス
ク開口の直径が３５０μｍφ、マスク厚ｔが１００μｍ
のとき、ハンダコア７の高さは１９０±２０μｍの範囲
で得られた。 【００１４】つぎに、図６に示されるように、半導体ウ
ェハ上のアクティブ面（ハンダコア７を形成した面）側
に、たとえばフィラー入りエポキシ樹脂を大気圧下で印
刷法により塗布して、樹脂層８を形成する。この際、樹
脂層８の厚さを規定するウェハ周囲を除いて開口孔を形
成した樹脂印刷マスクをつけて行うが、この樹脂印刷マ
スクは、ハンダコアの高さと同じ厚さから、それより１
５０μｍ大きい厚さまでの範囲の厚さとする。印刷後、
真空雰囲気下に放置して印刷時に巻き込んだ気泡を脱泡
する。その後、高温にして樹脂を硬化させる。具体的に
は、印刷に用いるマスク厚をハンダコア高さより大きい
２５０μｍ厚のものを使用し、１００Ｐａ・ｓの５種対
の粘度の樹脂を用いて、６６５Ｐａの減圧下で、２０分
間放置して脱泡をした。その後、１００℃で１時間、１
５０℃で２時間の熱処理をして樹脂を硬化させた。硬化
後の樹脂層８の厚さは２７５±５０μｍであった。な
お、使用する樹脂の粘度は、２５、２００、３００、６
００Ｐａ・ｓでも使用できることが確認されている。 【００１５】つぎに、図７に示されるように、半導体基
板１のアクティブ面側（表面側）の樹脂層８を研削し
て、ハンダコア７を露出させる。樹脂の研削量は、樹脂
層８の研削面がハンダコア７の高さの２／３〜１／２と
なるように設定した。具体的には、１９０μｍ高のハン
ダコア７の場合に、樹脂層の厚さ（研削後のハンダコア
５の高さ）が９５〜１２５（１１０±１５）μｍとなる
ように研削を行った。このとき、露出したハンダコア７
の直径は、２００±２０μｍφの範囲で得られた。 【００１６】つぎに、図８に示されるように、半導体基
板１の厚さが１５０〜３５０μｍになるように、半導体
基板１の裏面を研磨する。具体的には、６３０μｍ厚の
半導体基板１を研磨して、２００±１５μｍ厚にした。
その後、図９に示されるように、半導体基板１の裏面側
にたとえば、フィラー入りエポキシ樹脂を大気圧下で印
刷により塗布して裏面樹脂層９を形成する。この印刷の
際に用いるマスクは、裏面樹脂層９の厚さが１５０±１
００μｍの厚さになるように選定する。その後、真空圧
下に放置して印刷時に巻き込んだ気泡を脱泡した後に、
１００℃で１時間、１５０℃で２時間の熱処理を行い、
樹脂を硬化させることにより、裏面樹脂層９を形成す
る。具体例としては、ウェハ周囲以外を開口した１００
μｍ厚のマスクを使用して、３０Ｐａ・ｓの粘度の樹脂
を印刷により塗布し、６６５Ｐａ以下の真空圧下に２０
分間放置して、脱泡を行い気泡を除去した。その後、１
００℃で１時間、１５０℃で２時間の熱処理を行い、樹
脂を硬化させた。硬化後の裏面樹脂層９の厚さは、１０
０±４０μｍの範囲で得られた。 【００１７】つぎに、図１０に示されるように、ハンダ
コア７上にハンダバンプ１０を印刷法により形成する。
ここで、前述のハンダコア７を形成する場合と同様に、
ハンダペーストを印刷する際に用いるマスクは、（マス
クの開口面積）／（開口部におけるマスク壁面面積）の
比率が１／２以上のハンダマスクを使用するのがよかっ
た。そして、酸素濃度が１０００ｐｐｍ以下の不活性ガ
ス雰囲気で、２６０℃、１０秒間の熱処理をしてリフロ
ーをした。具体的には、マスクとして、直径が３５０μ
ｍφの開口で、厚さｔが１００μｍのマスクを用い、Ｓ
ｎ-Ｃｕ（Ｃｕが２ｗｔ％）のハンダペーストを使用し
て印刷した。ハンダマスクの開口の直径が３５０μｍの
とき、マスク厚を変化させた結果、前述の場合と同様
に、厚さｔが１７５μｍまではハンダが転写されること
を確認できたが、２００μｍの厚さでは、マスクにハン
ダが残っており、転写の再現性に劣った。また、リフロ
ー時の酸素濃度を１０００ｐｐｍ以上にした場合、ハン
ダバンプ１０の高さにバラツキが生じた。ハンダコア７
の直径が２００±２０μｍφ、マスク開口の直径が３５
０μｍφ、マスク厚ｔが１００μｍのとき、ハンダバン
プ１０の高さは１５０±２０μｍの範囲で得られた。 【００１８】つぎに、図１１に１２３で示されるよう
に、ウェハの裏面、すなわち裏面樹脂層９の露出面に型
名などのマーク１１を付する。このマーキングは、印刷
またはレーザ刻印などの方法により行う。半導体基板１
がシリコンであれば、印刷でも、レーザ刻印でも構わな
いが、半導体基板がＧａＡｓのように、レーザ刻印によ
りＡｓなどの毒物が飛散する恐れのある場合には、印刷
法によりマーキングを行う。具体例では、半導体基板が
Ｓｉであるため、レーザによりマーキングを付した。 【００１９】つぎに、図１２に示されるように、ウェハ
に多数形成された同じ電子回路をそれぞれその境界部で
ダイシングをしてチップ化（個片化）する。具体的に
は、ウェハの裏面側をダイシングテープ１２に貼着し、
ダイサー１３によりチップ間を切断する。切断した後
も、ダイシングテープ１２に貼着したまま、次工程のテ
ストを行うことができる。 【００２０】その後、図１３に示されるように、ハンダ
バンプ１０にテスターのプローブ１４を接触させて、電
気試験を行う。このように、梱包直前にテストを行なう
ことにより、ダイシング時の不良も検出することがで
き、不良品の流出を完全に防止することができ、信頼性
を向上させることができる。また、このように、ダイシ
ングテープ１２に貼着したままテストを行うことによ
り、各チップは電気的には分離されながら、ダイシング
テープ１２上に整列しているため、図１３に示されるよ
うに、２個以上のチップを同時にテストすることができ
る。具体的には、４個のチップを同時にテストすること
ができた。このように同時に複数個のチップのテストを
行うことができるため、テストインデックスを短くする
ことができ、コストダウンを図ることができた。もちろ
ん、従来通りピックアンドプレスによる１個単位でのテ
ストをすることもできる。 【００２１】最後に、外観検査を行い、図１４に示され
るように、チップごとに収納できる凹部が形成されたキ
ャリアテープ１５の凹部に収納し、キャリアテープを梱
包することにより、出荷できる状態になる。 【００２２】本発明によれば、半導体チップの基板表面
に設けられる電極端子を再配置して電極パッド間の間隔
を広げ、無電解メッキによるバリアメタル層を形成し、
その上にハンダコアおよびハンダバンプを印刷と加熱処
理により形成しているため、従来のハンダバンプを電解
メッキにより設ける方法に比べて、非常に簡単な製造工
程でチップサイズ程度の小型で、直接マザーボードなど
にマウントすることができる半導体装置を得ることがで
きる。 【００２３】なお、前述の具体例では、電極端子を再配
置するための配線４として、Ａｌ-Ｓｉ（Ｓｉが１ｗｔ
％）を用いる例であったが、配線４として、Ａｕまたは
Ｃｕを用いる場合には、この膜を形成するのに、スパッ
タ法以外に真空蒸着で成膜してもよい。また、図４のバ
リアメタル層６の形成工程は以下のように行う。 【００２４】まず、前述の例と同様に、再配置した電極
パッド４ａ表面の親水性改善のため、脱脂処理を行い、
ついで、硫酸または硝酸により表面に付着した酸化膜を
除去する。その後、電極パッド４ａの表面に、Ｐｄを置
換メッキにより成膜する。つぎに、還元反応により、Ｎ
ｉを５〜９μｍ析出させる。さらに、置換メッキ法によ
りＡｕ膜を０.０３μｍ形成することにより、バリアメ
タル層６を形成する。なお、このバリアメタル層６の直
径は１６０μｍであった。ここで、配線４は、半導体基
板１表面の凹凸により断線が生じる場合があるので、１
μｍ以上の厚さに形成することが必要である。 【００２５】 【発明の効果】以上のように、本発明によれば、半導体
基板表面にウェハのプロセスを用いて、電極端子の再配
置を行って電極パッドの間隔を広げているため、インタ
ーポーザを用いることなく、直接マザーボードなどにマ
ウントすることができるチップサイズの非常に小型の半
導体装置を得ることができる。しかも、半導体基板表面
にハンダコアやハンダバンプを形成する前にバリアメタ
ル層を無電解メッキにより形成し、さらに、ハンダコア
やハンダバンプの形成を、印刷と加熱処理とにより行っ
ているため、非常に簡単な設備で、しかも一括処理によ
り製造することができる。その結果、小型、薄型、軽量
の半導体装置を非常に安価に得ることができる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device that can achieve a small size, a thin shape, a light weight, and a low price. More specifically, the present invention relates to a method for manufacturing a semiconductor device, which can inexpensively obtain a semiconductor device having a structure that can be directly mounted on a mother board without using a lead frame or an interposer while having fine electrode terminals. 2. Description of the Related Art Generally, in a semiconductor device, as shown in FIG. 15, for example, a semiconductor chip 21 is die-bonded to a die pad 22 of a lead frame, and an electrode pad 21a, a lead 23 of a lead frame, These are manufactured by forming a package 25 by wire bonding with a gold wire 24 and molding with resin. Further, as means for realizing small size, thinness, and weight reduction, as shown in FIG. 16 or FIG.
A chip size package is considered in which solder balls are formed by being dispersed over the entire area of one plane. That is, in the example shown in FIG. 16, a wiring (not shown) is formed on one surface of an interposer 26 made of a ceramic substrate, an organic material substrate such as polyimide, a film tape, etc. Are connected by wire bonding using a gold wire 24 or the like, and connected to the wiring on the back surface of the interposer 26 to form an external electrode 27 made of a solder ball or the like, and the semiconductor chip 21 side is covered with a resin 25 Technology. In the example shown in FIG. 17, the connection between the electrode pad 21a of the semiconductor chip 21 and the wiring is not performed by wire bonding, and the solder bump 21b is applied to the electrode pad (not shown).
The bumps 21b and the interposer wiring are directly joined, and the other configuration is the same as the example shown in FIG. A resin layer 28 fixes the semiconductor chip. By interposing such an interposer, it is possible to disperse the electrode pads provided at very small intervals around the semiconductor chip over the entire area of the semiconductor chip and directly connect it to a circuit board or the like. It is said. That is, with the recent high integration and miniaturization of semiconductor chips, the electrode pads are provided around the semiconductor chip at intervals of about 100 to 200 μm. However, the wiring of the circuit board on which the semiconductor device is mounted is
Even if bump electrodes are formed on the electrode pads of the semiconductor chip, they cannot be directly mounted on the circuit board. However, by interposing this interposer, the electrodes are formed over the entire area of the semiconductor chip. Since it can be dispersed, it can be mounted directly on a circuit board. As described above, the chip size package can be reduced in size, but requires an interposer and a connecting step for connecting to it. This interposer has less circulation, that is, less production than semiconductor devices that use lead frames.
Since there are some that require fine molding, the cost is generally high. In addition, the wire bonding between the interposer and the semiconductor chip is a one-by-one connection, so batch processing cannot be performed, and plating bumps by a general electrolytic method can be batch processed. In the process of forming metal, expensive equipment such as a stepper device, a resist coating / developing / exposure device is required. For this reason, the chip size package can be reduced in size, thickness, and weight, but there is a problem that the cost increases. The present invention has been made in view of such a situation, and without using an interposer, the electrode interval is widened, a barrier metal is formed by an electroless plating method, solder core, solder bump, resin sealing, etc. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can reduce the cost while realizing a small size, a thin shape, and a light weight by simply performing micro-molding. A method of manufacturing a semiconductor device according to the present invention includes forming an electronic circuit on a semiconductor substrate and dispersing electrode terminals of the electronic circuit on the semiconductor substrate via wiring. Forming a rearranged electrode pad, forming a barrier metal layer on the electrode pad by electroless plating, printing a solder paste on the barrier metal layer, and performing heat treatment, Forming a solder core; forming a resin layer on the surface of the semiconductor substrate on which the solder core is formed; grinding the resin layer to expose the solder core; and exposing the solder core of the semiconductor substrate. Forming a resin layer on the back side opposite to the finished surface, and on the exposed solder core,
And a step of forming solder bumps by printing solder paste and performing heat treatment. By using this method, the interval between the electrode pads is increased on the semiconductor substrate and the barrier metal layer is interposed, so that solder bumps are directly formed on the semiconductor substrate by printing solder paste and heat treatment. Can do. Moreover, since the barrier layer is formed by electroless plating, the barrier metal layer can be formed only on the electrode pad portion where the bump electrode is necessary, and it is provided on the entire surface by sputtering or the like as in the prior art. The metal film can be formed without a complicated process of forming a mask, performing electrolytic plating, and then etching. Furthermore, since the solder core and the solder bump are formed by printing and heat treatment, the manufacturing process is greatly simplified. DETAILED DESCRIPTION OF THE INVENTION Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. In the method of manufacturing a semiconductor device according to the present invention, first, as shown in FIGS. 1 to 3, an electronic circuit is formed on a semiconductor substrate 1, and electrode terminals 2 of the electronic circuit are connected to the semiconductor substrate 1 via wiring 4. The electrode pad 4a rearranged is formed by dispersing, and as shown in FIG. 4, on the electrode pad 4a,
A barrier metal layer 6 is formed by electroless plating, and as shown in FIG. 5, a solder core 7 is formed on the barrier metal layer 6 by printing solder paste and heat treatment, as shown in FIG. Further, a resin layer 8 is formed by printing a resin on the surface of the semiconductor substrate 1 on which the solder core 7 is formed, and the resin layer 8 is ground to expose the solder core 7 as shown in FIG. As shown in FIG. 10, a back resin layer 9 is formed on the back side of the semiconductor substrate 1 and, as shown in FIG. 10, a solder paste is further printed on the exposed solder core 7 and subjected to heat treatment, whereby solder bumps 10 are formed. It is manufactured by forming. The semiconductor device manufacturing method will be described in more detail with specific examples. First, as shown in FIG. 1, a circuit element (not shown) such as a transistor or a diode is formed on a semiconductor substrate (wafer) 1 to form an electronic circuit, and an electrode terminal 2 of the electronic circuit is formed on the surface thereof. At the same time, an insulating film 3 is formed on the surface of the semiconductor substrate 1 to protect the circuit elements. This state is the state of the wafer before it is made into a normal semiconductor chip. 1 to 10
In FIG. 1, one electrode terminal and a bump electrode provided to be connected to the electrode terminal are shown as one example. However, bump electrodes are formed simultaneously in the same manner for all the electrode terminals. Next, an electrode material made of Al—Si (Si is 1 wt%) or the like is formed to a thickness of about 1 μm by sputtering or the like, and a resist film (not shown) is provided for patterning, thereby FIG. As shown in FIG. 2, the wiring 4 is formed so as to be connected to the electrode terminal 2 and extend to a desired place where the bump electrode is formed. Thereafter, as shown in FIG. 3, a coating layer 5 made of SiO 2 or Si 3 N 4 or the like is provided on the entire surface by CVD or the like so that only the bump electrode forming location which is the end portion of the wiring 4 is exposed. To pattern. At this time, the rearranged electrode pad 4a with the wiring 4 exposed as a bump electrode formation location is spaced about 0.5 mm from the other rearranged electrode pads, and the size is about 150 μmφ. Form. Next, as shown in FIG. 4, a barrier metal layer 6 is formed on the rearranged electrode pad 4a. Specifically, it was performed as follows. First, degreasing treatment was performed to improve the hydrophilicity of the rearranged electrode pad 4a surface, and then the oxide film adhered to the surface was removed with sulfuric acid or nitric acid. Thereafter, a Zn film was substitution plated on the surface.
After removing this Zn film once with nitric acid, the Zn film was subjected to substitution plating again to form a uniform Zn film on the surface of the electrode pad 4a. Next, 5 to 9 μm of Ni was deposited by a reduction reaction. Furthermore, in order to prevent the Ni surface from being oxidized, the barrier metal layer 6 was formed by forming 0.03 μm of an Au film by a displacement plating method. The diameter of the barrier metal layer 6 was 160 μm. Here, the electrode pad 4a has a large etching amount when the first Zn is formed by substitution plating. Specifically, it was etched by about 0.7 μm. Therefore, the thickness of the wiring 4 is 1 μm.
It is necessary to provide more than about. When the thickness is 1 μm or less, the material of the electrode pad 4a may be melted and lost before forming the second Zn, and the Ni plating may not grow, which is not preferable. After forming the Au film, heat treatment was performed at 230 ° C. for 1 hour in order to strengthen the bond between these films. Next, as shown in FIG. 5, a solder core 7 is formed on the surface of the barrier metal layer 6 by a printing method. As a mask in this case, (mask opening area πr
2 ) / (mask wall surface area at opening 2πrt) = r
It was good to use a solder mask with a ratio of / 2t of 1/2 or more. If (mask opening area) / (mask wall surface area) is smaller than 1/2, for example, the mask opening diameter is 350 μmφ and the mask thickness t is 200 μm.
In this case, the adhesive strength to the mask wall surface is larger, and the solder paste remains on the mask, and transfer reproducibility is poor. Specifically, using a mask having a diameter of 350 μmφ and a thickness t of 100 μm, Sn—Cu
Printing was performed using a solder paste (Cu is 2 wt%). And it reflowed by heat-processing for 10 second or more at 260 degreeC in the inert gas atmosphere whose oxygen concentration is 1000 ppm or less. When the diameter of the opening of the solder mask is 350 μm, the thickness t is 175 μm as a result of changing the mask thickness.
It was confirmed that the solder was transferred up to (that is, r / 2t = 0.5). Also, the oxygen concentration during reflow is 10
In the case of 00 ppm or more, the height of the solder core 7 varied. The diameter of the barrier metal layer is 160 μmφ, the diameter of the mask opening is 350 μmφ, and the mask thickness t is 100 μm.
The height of the solder core 7 was obtained in the range of 190 ± 20 μm. Next, as shown in FIG. 6, for example, a filler-filled epoxy resin is applied to the active surface (surface on which the solder core 7 is formed) on the semiconductor wafer by a printing method under atmospheric pressure, and a resin layer is formed. 8 is formed. At this time, a resin printing mask in which an opening hole is formed except for the periphery of the wafer that defines the thickness of the resin layer 8 is attached. This resin printing mask has a thickness equal to the height of the solder core, and 1
The thickness is in the range up to 50 μm thick. After printing
Leave in a vacuum atmosphere to defoam air bubbles that are caught during printing. Thereafter, the resin is cured at a high temperature. Specifically, a mask having a thickness of 250 μm larger than the height of the solder core is used for printing, and the resin is removed by leaving it for 20 minutes under a reduced pressure of 665 Pa using five types of resins of 100 Pa · s. Foamed. Then, 1 hour at 100 ° C,
The resin was cured by heat treatment at 50 ° C. for 2 hours. The thickness of the resin layer 8 after curing was 275 ± 50 μm. The viscosity of the resin used is 25, 200, 300, 6
It has been confirmed that it can be used even at 00 Pa · s. Next, as shown in FIG. 7, the active layer side (surface side) resin layer 8 of the semiconductor substrate 1 is ground to expose the solder core 7. The grinding amount of the resin was set so that the grinding surface of the resin layer 8 was 2/3 to 1/2 of the height of the solder core 7. Specifically, in the case of the solder core 7 having a height of 190 μm, grinding was performed such that the thickness of the resin layer (the height of the solder core 5 after grinding) was 95 to 125 (110 ± 15) μm. At this time, the exposed solder core 7
The diameter of was obtained in the range of 200 ± 20 μmφ. Next, as shown in FIG. 8, the back surface of the semiconductor substrate 1 is polished so that the thickness of the semiconductor substrate 1 becomes 150 to 350 μm. Specifically, the semiconductor substrate 1 having a thickness of 630 μm was polished to a thickness of 200 ± 15 μm.
After that, as shown in FIG. 9, for example, a filler-filled epoxy resin is applied to the back surface side of the semiconductor substrate 1 by printing under atmospheric pressure to form the back surface resin layer 9. In the mask used for this printing, the thickness of the back surface resin layer 9 is 150 ± 1.
The thickness is selected to be 00 μm. After leaving it under vacuum pressure to defoam bubbles that were caught during printing,
Heat treatment at 100 ° C. for 1 hour and 150 ° C. for 2 hours,
The back surface resin layer 9 is formed by curing the resin. As a specific example, 100 is opened except for the periphery of the wafer.
Using a μm-thick mask, a resin having a viscosity of 30 Pa · s was applied by printing, and the pressure was reduced to 20 under a vacuum pressure of 665 Pa or less.
The mixture was left for a minute and defoamed to remove bubbles. Then 1
Heat treatment was performed at 00 ° C. for 1 hour and 150 ° C. for 2 hours to cure the resin. The thickness of the back surface resin layer 9 after curing is 10
Obtained in the range of 0 ± 40 μm. Next, as shown in FIG. 10, solder bumps 10 are formed on the solder core 7 by a printing method.
Here, as in the case of forming the solder core 7 described above,
As a mask used for printing the solder paste, a solder mask having a ratio of (mask opening area) / (mask wall surface area in the opening) of 1/2 or more should be used. Then, reflow was performed by heat treatment at 260 ° C. for 10 seconds in an inert gas atmosphere having an oxygen concentration of 1000 ppm or less. Specifically, the mask has a diameter of 350 μm.
Using a mask with an opening of mφ and a thickness t of 100 μm, S
Printing was performed using a solder paste of n-Cu (Cu is 2 wt%). As a result of changing the mask thickness when the diameter of the solder mask opening was 350 μm, it was confirmed that the solder was transferred up to a thickness t of 175 μm as in the case described above. Solder remained on the mask, and transfer reproducibility was poor. In addition, when the oxygen concentration during reflow was set to 1000 ppm or more, the height of the solder bumps 10 varied. Solder core 7
Has a diameter of 200 ± 20 μmφ and a mask opening diameter of 35
When the thickness was 0 μmφ and the mask thickness t was 100 μm, the height of the solder bump 10 was obtained in the range of 150 ± 20 μm. Next, as shown by 123 in FIG. 11, a mark 11 such as a model name is attached to the back surface of the wafer, that is, the exposed surface of the back surface resin layer 9. This marking is performed by a method such as printing or laser marking. Semiconductor substrate 1
If the semiconductor substrate is silicon, printing or laser marking may be used. However, if the semiconductor substrate is GaAs and laser or other toxic substances may be scattered, marking is performed by a printing method. In the specific example, since the semiconductor substrate is Si, marking is performed by a laser. Next, as shown in FIG. 12, the same electronic circuits formed in large numbers on the wafer are diced at their boundaries to form chips (divided into individual pieces). Specifically, the back side of the wafer is attached to the dicing tape 12,
Chips are cut by the dicer 13. Even after cutting, the test of the next process can be performed while being stuck to the dicing tape 12. Thereafter, as shown in FIG. 13, a tester probe 14 is brought into contact with the solder bump 10 to conduct an electrical test. In this way, by performing the test immediately before packing, it is possible to detect a defect during dicing, to completely prevent the outflow of defective products, and to improve reliability. Further, by performing the test while being adhered to the dicing tape 12 in this way, each chip is aligned on the dicing tape 12 while being electrically separated, so as shown in FIG. Two or more chips can be tested simultaneously. Specifically, four chips could be tested simultaneously. Since a plurality of chips can be tested simultaneously in this way, the test index can be shortened and the cost can be reduced. Of course, it is also possible to perform a test in a single unit by pick and press as usual. Finally, an appearance inspection is performed and, as shown in FIG. 14, the product is stored in a recess of the carrier tape 15 formed with a recess that can be stored for each chip, and the carrier tape is packed so that it can be shipped. Become. According to the present invention, electrode terminals provided on the substrate surface of the semiconductor chip are rearranged to increase the distance between the electrode pads, and a barrier metal layer is formed by electroless plating.
Since the solder core and solder bumps are formed by printing and heat treatment, it is mounted on a mother board directly with a very small manufacturing process compared to the conventional method of providing solder bumps by electrolytic plating. A semiconductor device that can be obtained can be obtained. In the above-mentioned specific example, as the wiring 4 for rearranging the electrode terminals, Al—Si (Si is 1 wt.
However, when Au or Cu is used for the wiring 4, this film may be formed by vacuum deposition in addition to the sputtering method. Moreover, the formation process of the barrier metal layer 6 of FIG. 4 is performed as follows. First, in the same manner as in the above example, degreasing treatment is performed to improve the hydrophilicity of the surface of the rearranged electrode pad 4a.
Next, the oxide film adhering to the surface is removed by sulfuric acid or nitric acid. Thereafter, Pd is deposited on the surface of the electrode pad 4a by displacement plating. Next, N is reduced by a reduction reaction.
i is deposited 5-9 μm. Further, the barrier metal layer 6 is formed by forming 0.03 μm of Au film by displacement plating. The diameter of the barrier metal layer 6 was 160 μm. Here, since the wiring 4 may be disconnected due to unevenness on the surface of the semiconductor substrate 1, 1
It is necessary to form a thickness of μm or more. As described above, according to the present invention, the interposer is provided because the electrode terminals are rearranged by using the wafer process on the surface of the semiconductor substrate to rearrange the electrode pads. A very small semiconductor device having a chip size that can be directly mounted on a mother board or the like without being used can be obtained. In addition, the barrier metal layer is formed by electroless plating before forming the solder core or solder bump on the surface of the semiconductor substrate, and the solder core or solder bump is formed by printing and heat treatment. Moreover, it can be manufactured by batch processing. As a result, a small, thin, and lightweight semiconductor device can be obtained at a very low cost.

【図面の簡単な説明】 【図１】本発明による製造方法の一実施形態の製造工程
を示す説明図である。 【図２】本発明による製造方法の一実施形態の製造工程
を示す説明図である。 【図３】本発明による製造方法の一実施形態の製造工程
を示す説明図である。 【図４】本発明による製造方法の一実施形態の製造工程
を示す説明図である。 【図５】本発明による製造方法の一実施形態の製造工程
を示す説明図である。 【図６】本発明による製造方法の一実施形態の製造工程
を示す説明図である。 【図７】本発明による製造方法の一実施形態の製造工程
を示す説明図である。 【図８】本発明による製造方法の一実施形態の製造工程
を示す説明図である。 【図９】本発明による製造方法の一実施形態の製造工程
を示す説明図である。 【図１０】本発明による製造方法の一実施形態の製造工
程を示す説明図である。 【図１１】本発明による製造方法の一実施形態の製造工
程を示す説明図である。 【図１２】本発明による製造方法の一実施形態の製造工
程を示す説明図である。 【図１３】本発明による製造方法の一実施形態の製造工
程を示す説明図である。 【図１４】本発明による製造方法の一実施形態の製造工
程を示す説明図である。 【図１５】従来の半導体装置における構造の一例を示す
説明図である。 【図１６】従来の半導体装置における構造の一例を示す
説明図である。 【図１７】従来の半導体装置における構造の一例を示す
説明図である。 【符号の説明】 １ 半導体基板 ２ 電極端子 ４ 配線 ４ａ 電極パッド ６ バリアメタル層 ７ ハンダコア ８ 樹脂層 ９ 裏面樹脂層 １０ ハンダバンプBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view showing a manufacturing process of an embodiment of a manufacturing method according to the present invention. FIG. 2 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention. FIG. 3 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention. FIG. 4 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention. FIG. 5 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention. FIG. 6 is an explanatory view showing a manufacturing process of an embodiment of the manufacturing method according to the present invention. FIG. 7 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention. FIG. 8 is an explanatory diagram showing a manufacturing process of an embodiment of the manufacturing method according to the present invention. FIG. 9 is an explanatory diagram showing a manufacturing process of an embodiment of the manufacturing method according to the present invention. FIG. 10 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention. FIG. 11 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention. FIG. 12 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention. FIG. 13 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention. FIG. 14 is an explanatory diagram showing manufacturing steps of an embodiment of the manufacturing method according to the present invention. FIG. 15 is an explanatory diagram showing an example of a structure in a conventional semiconductor device. FIG. 16 is an explanatory diagram showing an example of a structure in a conventional semiconductor device. FIG. 17 is an explanatory diagram showing an example of a structure in a conventional semiconductor device. [Description of Symbols] 1 Semiconductor substrate 2 Electrode terminal 4 Wiring 4a Electrode pad 6 Barrier metal layer 7 Solder core 8 Resin layer 9 Back surface resin layer 10 Solder bump

Claims (1)

【特許請求の範囲】 【請求項１】 半導体基板に電子回路を形成し、該電子
回路の電極端子を前記半導体基板上で配線を介して分散
することにより再配置された電極パッドを形成する工程
と、該電極パッド上に、無電解メッキによりバリアメタ
ル層を形成する工程と、該バリアメタル層上に、ハンダ
ペーストを印刷し熱処理をすることにより、ハンダコア
を形成する工程と、前記半導体基板の該ハンダコアを形
成した面側に樹脂層を形成する工程と、該樹脂層を研削
して前記ハンダコアを露出させる工程と、前記半導体基
板の前記ハンダコアを露出した面と反対の裏面側に樹脂
層を形成する工程と、前記該露出したハンダコア上に、
さらにハンダペーストを印刷し熱処理をすることによ
り、ハンダバンプを形成する工程とを含むことを特徴と
する半導体装置の製造方法。1. A process of forming an electronic circuit on a semiconductor substrate and forming a rearranged electrode pad by dispersing electrode terminals of the electronic circuit on the semiconductor substrate via wiring. A step of forming a barrier metal layer on the electrode pad by electroless plating, a step of forming a solder core by printing a solder paste on the barrier metal layer and performing heat treatment, and a step of forming the semiconductor substrate. A step of forming a resin layer on the surface side on which the solder core is formed; a step of grinding the resin layer to expose the solder core; and a resin layer on the back surface side of the semiconductor substrate opposite to the surface on which the solder core is exposed. Forming and on the exposed solder core,
And a step of forming a solder bump by printing a solder paste and performing a heat treatment.
JP2002144124A 2002-05-20 2002-05-20 Manufacturing method of semiconductor device Expired - Fee Related JP3726115B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041401A (en) * 2004-07-29 2006-02-09 Sharp Corp Semiconductor device and manufacturing method thereof
WO2006077630A1 (en) * 2005-01-19 2006-07-27 New Japan Radio Co., Ltd. Semiconductor device manufacturing method
WO2008050582A1 (en) * 2006-10-26 2008-05-02 Sharp Kabushiki Kaisha Semiconductor device, display device and electronic device
JP2009266853A (en) * 2008-04-22 2009-11-12 New Japan Radio Co Ltd Semiconductor device, and method of manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041401A (en) * 2004-07-29 2006-02-09 Sharp Corp Semiconductor device and manufacturing method thereof
WO2006077630A1 (en) * 2005-01-19 2006-07-27 New Japan Radio Co., Ltd. Semiconductor device manufacturing method
US7326638B2 (en) 2005-01-19 2008-02-05 New Japan Radio Co., Ltd. Method for manufacturing semiconductor device
JPWO2006077630A1 (en) * 2005-01-19 2008-06-12 新日本無線株式会社 Manufacturing method of semiconductor device
JP4739198B2 (en) * 2005-01-19 2011-08-03 新日本無線株式会社 Manufacturing method of semiconductor device
WO2008050582A1 (en) * 2006-10-26 2008-05-02 Sharp Kabushiki Kaisha Semiconductor device, display device and electronic device
JP2009266853A (en) * 2008-04-22 2009-11-12 New Japan Radio Co Ltd Semiconductor device, and method of manufacturing the same

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