JP2558961B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is used for manufacturing a non-volatile semiconductor memory, particularly for forming a floating gate type memory cell.

[0002]

2. Description of the Related Art In recent years, storage capacity of non-volatile memory has been increased.
As the capacity increases, memory cells shrink and
The challenge is to shorten the writing time of data. this
To address these problems, the approach from the memory cell structure
DSA (Diffusion Self-Aligned) structure is proposed as
Has been done. FIG. 12 is a schematic diagram for explaining the DSA structure.
11 shows a volatile memory cell, 11 is a P-type silicon base
Plate, 12 is an isolation oxide film, 13a is a source region (N⁺ Typeless
13b is a drain region (N⁺ Type impurity region
Area), 14 is a floating gate, 15 is a control gate, and 16 is P
Type impurity region, 17 is a channel region, 18 is gate insulation
A film, 19 is a polysilicon interlayer insulating film. That is, DS
As shown in FIG. 12, the A structure has an N channel type Celt, in particular.
A channel region is formed around the drain region 13b of the transistor.
A P-type impurity region 16 (P
-Drain during writing, forming a pocket)
Increase the electric field strength in the nearby channel region, which
It is intended to increase the gate injection current. Especially
For the punch-through resistance of the transistor,
There is a problem peculiar to the gate cell transistor. It floats
If a free-gate field effect transistor is used in the cell,
Voltage is applied to the drain, the floating gate and
The potential of the floating gate floats due to capacitive coupling with the rain.
Therefore, the cell transistor is a single-gate type transistor.
Punch-through is easier than with This trend is
As the gate length of the transistor becomes shorter, it becomes more noticeable.
When trying to reduce the transistor size,
This is a problem that needs to be solved. P-pocket 16
By forming the
The punch-through withstand voltage of the transistor is improved and the cell size is reduced.
This is advantageous.

From the above, when the DSA structure is used for the floating gate type memory cell transistor, there are advantages that the writing speed is improved and the punch-through breakdown voltage is strengthened, which is an essential technique for a large capacity nonvolatile memory. Can be.

[0004]

In order to form the DSA structure in the N-channel type cell transistor and to fully exert its intended function, the P-pocket region particularly near the drain end of the floating gate is formed. The impurity concentration profile of is important. In order to improve the punch-through breakdown voltage of the cell transistor and the writing speed,
It is necessary to make the impurity concentration of the P-pocket region near the edge of the drain sufficiently higher than that of the channel region. However, P-
The formation of the pocket region is performed by ion-implanting P-type impurities after forming the stacked gate electrode, so that the following problems occur. Since the edge of the drain is covered by the stacked gate, in order to prevent channeling (to prevent ions from being deeply implanted through the path through which ions easily pass), the conventional ion implantation method does not use the substrate normal line for ion implantation. Is as small as 7 degrees at the maximum, and it is impossible to directly inject P-type impurities sufficiently into the vicinity of the drain end portion under the floating gate. Therefore, as an actual method, ion implantation for forming a P-pocket region is performed, and a thermal process such as annealing is performed to diffuse the P-type impurity further toward the channel side from the region which becomes the drain end, and then the source / drain region is formed. The method of performing ion implantation to form is adopted. For this reason, if the P-pocket of the DSA structure is introduced, the number of heating steps increases once, and the two ion implantations cannot be performed at the same time due to this heating step, and the number of patterning steps using a mask also increases once. There are drawbacks. When the P-pocket region is formed by such diffusion, the controllability of the impurity concentration profile is not sufficient, and it is difficult to obtain a sufficiently high P-type impurity concentration near the drain end. Further, there is a drawback that the channel impurity concentration profile is greatly affected by the thermal process for forming the P-pocket region. Further, if the P-type impurity is sufficiently thermally diffused in the lateral direction to form the P-pocket region and the concentration of the P-type impurity in the diffused portion is to be kept high, the dose of ion implantation is considerably increased. However, this causes problems such as increase in junction capacitance and deterioration in junction breakdown voltage. The junction breakdown voltage is overlapped with the channel stopper region under the element isolation region in the P-pocket region, and the P-type impurity concentration is further increased, and the source / drain N ^{+ is formed.} Since a pn junction breakdown voltage can be formed between the junction region and the region, the junction breakdown voltage is greatly affected by the impurity concentration distribution in the vicinity.

Therefore, an object of the present invention is to provide a semiconductor capable of improving the controllability of the P-type impurity concentration profile and improving the performance in the peripheral region on the channel side of the drain or source region in the stacked gate nonvolatile memory cell. It is to provide a method of manufacturing a device.

[0006]

Means and Actions for Solving the Problems

(1) A step of providing a floating gate electrode on a first conductivity type channel formation planned region via an insulating film and forming a control gate electrode on the gate electrode, and each of the stacked gate electrodes. After the formation, impurities of the first conductivity type are ion-implanted at an angle of 8 degrees or more with respect to the normal line of the semiconductor substrate surface, and the second conductivity type diffusion layer serving as the drain of the transistor having the stacked gate electrode is formed. And a step of forming a region having a high first-conductivity-type impurity concentration in the vicinity of the boundary. Further, the present invention is (2) the method of manufacturing a semiconductor device according to (1), wherein the ion implantation is performed at 60 degrees or less with respect to a normal line of the semiconductor substrate.

That is, in order to achieve the above-mentioned object, the present invention appropriately rotates the substrate for impurity ion implantation for forming the P-pocket region, and specifically, the stacked gate with respect to the substrate normal. At least 8 degrees to the side of the, 6
Ion implantation is performed at an angle of 0 degrees or less to increase the impurity concentration in the pocket region near the drain end portion under the floating gate. By changing the implantation angle, the impurity concentration profile in this region is controlled, and the writing characteristics are improved and the short channel effect is suppressed at the same time.

The reason why the ion implantation direction is set to 8 degrees or more and 60 degrees or less is that if the conventional method is 7 degrees or less, the effect of increasing the impurity concentration in the pocket region near the drain end portion under the floating gate is extremely small. However, it is because the starting point is improved in the vicinity of 8 degrees compared to the conventional one, and the reason why it is set to 60 degrees or less is
This is because if the angle is larger than this angle, the angle becomes too large and it becomes difficult to satisfactorily implant ions into the substrate. In the present invention, since the ion implantation is performed at an angle of 8 degrees or more, the channeling problem occurs, but the deep ion implantation does not cause the problem.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing an EPROM cell transistor which is an embodiment of the present invention will be described with reference to FIGS.

For example, the field isolation film 22 and the channel stopper region 23 are formed on the surface of the P-type silicon substrate 21 by a well-known technique to perform element isolation. Next, a gate insulating film 24 of, eg, about 20 nm is formed on the surface of the silicon substrate 21 by a thermal oxidation method. The normal process is
After forming the gate insulating film 24, ion implantation of P-type impurities is performed in the channel region in order to adjust the threshold value of the cell transistor. According to the present invention, the threshold value of the cell transistor is set to P pocket ion implantation conditions. Since it can be controlled by (implantation angle, dose amount, accelerating voltage), in this embodiment, the P-type impurity for increasing the concentration is formed by forming the channel region only with the P-type impurity in the P-type silicon substrate 21. Ion implantation is not performed. Next, a phosphorus-doped polycrystalline silicon layer 25 which is a material for the floating gate is formed. Then, a thermal oxide film 26 of, eg, about 20 nm is formed on the polycrystalline silicon layer 25 by thermal oxidation. Then, a second phosphorus-doped polycrystalline silicon layer 27, which is a material for the control gate electrode, is formed on the oxide film 26 (see FIG. 1).

Next, the second phosphorus-doped polycrystalline silicon layer 27, the thermal oxide film 26, and the first phosphorus-doped polycrystalline silicon layer 25 are sequentially patterned, and the control gate electrode 2 is formed.
7. A laminated gate electrode including the second gate insulating film 26 and the floating gate electrode 25 is formed. Then, thermal oxidation is performed to form a post oxide film 31 on the stacked gate and the substrate surface (see FIG. 2).

Next, ion implantation of P-type impurities is performed in a self-aligned manner by using the above-mentioned laminated gate as a mask.
A P-type ion implantation layer 32 is formed in the vicinity of the portion where the drain region is to be formed.
a and 32b are formed. In this ion implantation, for example, the silicon substrate 21 is rotated once or more per minute, and boron is ion-implanted at an angle of 10 ° ≦ θ ≦ 45 ° with respect to the substrate normal line 33 and a dose amount of 5 × 10 ¹² cm ⁻² or more. (Figure 3, Figure 4
reference). In this case, the ion implantation impurities may be implanted at a concentration higher than the central portion of the channel region of the cell transistor and lower than the impurity concentration of the drain region of the cell transistor. This ion implantation may be performed by a method for manufacturing a semiconductor device, which is performed under the condition given by the following formula. X _p · tan θ ≧ X _jl

Here, X _p is the distance from the substrate surface of the average range of the first conductivity type impurities ion-implanted by the ion implantation, and θ is the angle of the ion implantation with respect to the normal to the semiconductor substrate surface. , X _jl is the distance that the end of the drain or source extends by diffusion in the channel direction under the stacked gate from the ion implantation to the final step (FIG. 7).
reference). That is, the product of the distance X _p and the tan θ from the substrate surface of the average range of the P-type impurities implanted by the ion implantation,
That is, in the present embodiment, P which enters under the floating gate
If the distance in the channel direction of the type impurities is larger than the distance X _jl at which the drain end is diffused and entered under the floating gate, the P-pocket concentration at the drain end can be sufficiently increased, and P- The effect of pockets can be demonstrated. Further, the ion implantation depth X _p at this time is approximately the same as the junction depth X _j of the drain diffusion layer (as a width X _j /
If 2 ≦ X _p ≦ 2X _j ), the P-type impurity in the portion having the largest curvature at the drain end, which is the most prominent for punch-through of the cell transistor, can be effectively increased, and the short channel effect The suppression effect becomes large. If the implantation is too shallow, the P-type impurities will be sucked into the oxide film in the upper portion due to a subsequent thermal process such as oxidation, which is not effective.

[0015] X _j = 0.20μm, X _jl in Fig. 11 shows a schematic 0.16 [mu] m, the implantation angle θ dependence of the punch-through characteristic at X _p = 0.30 .mu.m. In this case, according to the above equation, it is expected that the P pocket becomes effective when θ> 28 ° or more. What can be seen from FIG. 11 is that θ =
When 0 °, θ = 15 °, that is, less than 28 °, the punch-through withstand voltage sharply drops when the floating gate length L = 0.6 μm or less, but when θ = 30 °, that is, 28 ° or more, the punch-through withstand voltage improving effect is large. Appearing, a sufficient value is obtained up to L = 0.5 μm. However, in the present invention, it can be put to practical use at θ = 8 ° or more and can be put to practical use at θ = 60 ° or less, as described above.

3 and 4, 34 and 36 are P-type impurity ion beams, 35 is P-type impurity ions entering from the side wall of the stacked gate, 36a and 36b are P-type impurity ions entering from the field edge end, and 21 is rotating. Represents a silicon substrate.

Next, N-type impurity ions are implanted in a self-aligned manner using the laminated gate as a mask to form N-type ion implantation layers 39a and 39b. This ion implantation is
Parallel to the side surface of the stacked gate (7 to the normal to the substrate surface)
Ion implantation is performed. For example, arsenic 5
Ion implantation is performed under the condition of × 10 ¹⁵ cm ^-2 (see FIG. 5).
In FIG. 5, numeral 38 indicates an N-type impurity ion beam.

Next, a thermal process, for example, annealing at 900 ° C. is performed to activate the ion-implanted impurities and recover the damage to the oxide films 24 and 31 received by the two ion implantations. At this time, the P-type ion implantation layer 32a,
32b forms P-pocket regions 40a and 40b,
The N-type ion implantation layers 39a and 39b form source / drain regions 41a and 41b. After this, the normal M
The interlayer insulating film 42 is formed according to the method of manufacturing the OS integrated circuit. Next, a part of the interlayer insulating film 42 on the source / drain regions 41a and 41b is opened, a contact hole 43 is formed, and then an Al electrode 44 is formed.
The cell is completed (see FIG. 6). In FIG. 6, 45 is P
A portion where the pocket region and the channel stopper region overlap, and 46 represents a channel region.

According to the method of manufacturing the EPROM cell transistor described above, the P-type impurity concentration in the P-pocket region near the end of the drain region, which is important in the DSA structure, can be increased, and as a result, the writing efficiency of the cell can be increased. Is improved,
It is easy to miniaturize and highly integrate the cells.

FIG. 7 shows a cross section near the drain end of the cell formed in the above embodiment. The P-pocket region shown by the dotted line in FIG. 7 is the case where the conventional ion implantation method is used in the formation of the P-pocket region in the above-mentioned embodiment. In FIG. 7, X _j is the junction depth of the drain 41b, and X _j is
_jl is a distance that the drain end extends by diffusion in the channel direction below the floating gate 25 from the ion implantation to the final step. FIG. 8 shows a specific impurity concentration distribution in the AA ′ cross section of FIG. 7. The boron concentration shown by the dotted line is the case where the conventional ion implantation method is used in forming the P-pocket region in the above-mentioned embodiment.

(B) According to this method, the P-pocket region 40b near the floating gate 25 can be made to have a sufficiently higher concentration than the channel region 46, the electric field strength near the drain region 41b is increased, and the amount of hot electrons generated is increased. And the writing efficiency of the memory cell is improved.

(B) According to (a) above, the pn junction between the source or drain region and the P-pocket region can be formed with a high impurity concentration, and the extension of the depletion region can be suppressed.
It is possible to sufficiently secure the effective channel length of the cell transistor and suppress the short channel effect.

(C) Due to the above (a) and (b), it becomes possible to control the threshold voltage of the cell transistor only in the P-pocket region,
The ion implantation used for forming the channel of the cell transistor can be omitted.

(D) According to this method, in the P-type impurity concentration profile of the P-pocket region, the portion that affects the writing efficiency of the memory cell, that is, the vicinity of the drain side end under the gate 25 and the portion that affects the short channel effect, that is, Since the vicinity of the drain lower end under the gate 25 can be independently controlled (for example, by two times of ion implantation with different accelerating voltage and angle), it is possible to flexibly cope with a change in cell structure or a change in thermal process after forming a cell transistor. It becomes possible. (E) With this method, it is possible to omit the heat step required for forming the P-pocket region by the conventional ion implantation method.

(F) By the above (e), the ion implantation for forming the P-pocket region of the cell transistor and the ion implantation for forming the source / drain regions can be carried out at the same time. The number of steps can be reduced. (G) By this method, a portion 45 where the channel stopper region 23 below the element isolation region 22 and the P-pocket region overlap each other.
Then, in the portion 45 where the P-pocket region overlaps, the P-type impurity ions forming the P-pocket have a slow profile from the substrate surface to the depth due to transmission and scattering at the field edge. When the wafer is rotated to perform oblique ion implantation of the P-pocket, the number of P-type impurity ions implanted below the field edge is
For example, in the P-pocket region of the layer 32b, the maximum is in the direction of P-direction impurity ions 36b penetrating below the field edge, but there is almost no implantation in the direction of 180a opposite to 36a.
The P-type impurity concentration in the portion 45 where 6b and the channel stopper 22 overlap is reduced. (See FIG. 3) Due to these effects, in the pn junction formed in the above-mentioned portion, compared with the pn junction in which the P-pocket is formed by the conventional ion implantation method, the effect and the concentration of the P-type impurity concentration near the junction are reduced. Due to the effect of relaxing the gradient, the breakdown voltage of the pn junction can be improved.

The present invention is not limited to the embodiment, but various applications are possible. For example, in the above-described embodiment, the P-pocket region is formed so as to cover the source / drain region (see FIG. 6). However, for example, by using a mask process, the substrate 21 is kept stationary or intermittently rotated. 9,
It is obvious that the P-pocket region as shown in FIG. 10 may be partially formed near the drain. Further, in the above embodiment, the case where the P-pocket layers are formed on both sides of the drain and the source has been described, but it is clear that the P-pocket layers may be provided only on the drain side by using a mask process. Although the N-channel type cell has been described, the same applies to the P-channel type cell.

[0027]

【The invention's effect】

(1) According to the present invention, the P-pocket region near the floating gate can be made to have a sufficiently higher concentration than the channel region, the electric field strength in the vicinity of the drain region is increased, the generation amount of hot electrons is increased, and the writing of the memory cell is performed. Efficiency is improved.

(2) The source or drain region and P-
Since the pn junction with the pocket region can be formed with a high impurity concentration and the extension of the depletion region can be suppressed, the effective channel length of the cell transistor can be sufficiently secured and the short channel effect can be suppressed.

(3) Due to the above (1) and (2), the cell transistor can operate only in the P-pocket region, and the ion implantation used for forming the channel of the cell transistor can be omitted.

(4) According to the present invention, in the P-type impurity concentration profile of the P-pocket region, the part that affects the writing efficiency of the memory cell and the part that affects the short channel effect can be independently controlled. It is possible to flexibly cope with a change in temperature and a change in a thermal process after forming the cell transistor. (5) According to the present invention, it is possible to omit the heat step required for forming the P-pocket region by the conventional ion implantation method.

(6) According to the above (5), the ion implantation for forming the P-pocket region of the cell transistor and the ion implantation for forming the source / drain regions can be performed at the same time. The number of steps can be reduced.

(7) According to the present invention, in the portion where the channel stopper region under the element isolation region and the P-pocket region overlap, the P-type impurity ions forming the P-pocket are transmitted or scattered at the field edge, so that the substrate surface You will have a slow profile from to deep inside. Rotate the wafer to P
-The number of P-type impurity ions implanted in the lower portion of the field edge when oblique pocket ion implantation is performed is reduced. Therefore, the pn junction formed in the above portion has the effect of reducing the P-type impurity concentration in the vicinity of the junction and the effect of easing the concentration gradient, as compared with the pn junction in which the P-pocket is formed by conventional ion implantation. The breakdown voltage of the pn junction can be improved.

[Brief description of drawings]

FIG. 1 is a process drawing of an embodiment of the present invention.

FIG. 2 is a process drawing of the example.

FIG. 3 is a process diagram of the example.

FIG. 4 is a process drawing of the example.

FIG. 5 is a process drawing of the example.

FIG. 6 is a process drawing of the same example.

FIG. 7 is a cross-sectional view near the drain.

8 is a diagram showing an impurity concentration profile in FIG.

FIG. 9 is a cross-sectional view of essential parts of a different embodiment of the present invention.

FIG. 10 is a cross-sectional view of the essential parts of a different embodiment of the present invention.

FIG. 11 is a punch through breakdown voltage characteristic diagram of a cell transistor.

FIG. 12 is a cross-sectional view of a conventional nonvolatile memory cell.

[Explanation of symbols]

21 ... P-type substrate, 22 ... Field insulating film, 23 ... Channel stopper, 24, 29 ... Gate insulating film, 25 ... Floating gate electrode (polysilicon), 26 ... Oxide film, 27 ... Control gate electrode (Polysilicon), 31 ... Post oxide film, 32
a, 32b ... P-type ion implantation layer, 39a, 39b ... N-type ion implantation layer, 40a, 40b ... P-pocket region, 4
1a, 41b ... Source / drain, 42 ... Interlayer insulating film,
43 ... Contact hole, 44 ... Al electrode, 45 ... P region overlapping part, 46 ... Channel region.

Claims (6)

(57) [Claims] 1. A step of providing a floating gate electrode on a first conductivity type channel formation planned region via an insulating film and laminating a control gate electrode on the gate electrode via an insulating film. After each gate electrode is formed, the first conductivity type impurities are ion-implanted at an angle of 8 degrees or more and 60 degrees or less with respect to the normal line of the semiconductor substrate surface to form the stacked gate electrodes. Forming a region having a high impurity concentration of the first conductivity type in the vicinity of the boundary of the second conductivity type diffusion layer, which serves as the drain of the transistor, and the ion implantation at an angle of 8 degrees or more and 60 degrees or less is performed by Xp. tan θ ≧ Xjl and Xj / 2 ≦ Xp
≦ 2Xj (where Xp is the distance of the average range of the first conductivity type impurities ion-implanted by the ion implantation from the substrate surface, θ is the angle of the ion implantation with respect to the normal to the semiconductor substrate surface, Xjl is the distance that the end of the drain extends by diffusion in the channel direction under the stacked gate from the ion implantation to the final step, and Xj is the junction depth of the drain diffusion layer). A method of manufacturing a semiconductor device, characterized in that the method is performed. 2. The semiconductor device according to claim 1, wherein not only the drain of the transistor but also a region having a high impurity concentration of the first conductivity type is formed in the vicinity of the boundary of the second conductivity type diffusion layer serving as the source. Manufacturing method. 3. The method according to claim 1, further comprising a step of implanting the impurity at a concentration higher than that of a central portion of a channel region of the transistor and lower than that of a drain region of the transistor. Manufacturing method of semiconductor device. 4. The ion implantation is performed by continuously rotating the substrate.
A method of manufacturing a semiconductor device according to item 1. 5. The ion implantation is performed by intermittently rotating the substrate.
A method of manufacturing a semiconductor device according to item 1. 6. The semiconductor according to claim 1, wherein the ion implantation with an angle of 8 degrees or more and 60 degrees or less is performed simultaneously with the ion implantation for forming the source and drain of the transistor. Device manufacturing method.