JPS63300567A - Floating gate type insulated gate field effect transistor - Google Patents

Abstract

PURPOSE:To improve a writing speed by setting the substrate concentration profile of a channel to the depth of the vicinity of the bottom of source, drain regions at the peak of concentration. CONSTITUTION:Source and drain regions 5, 4 made of selectively formed N-type impurity regions are formed on a P-type semiconductor substrate 1. A first channel region 13 made of part of the substrate 1 is formed directly under a floating gate insulating film 9. A high concentration second channel region 12 in contact with the bottom of the region 4 and the vicinity is formed under the region 13. Further, a higher concentration P-type buried region 11a than the region 12 is formed thereunder. In this case, since there are buried regions under the regions 12 and 4, a depleted layer is scarcely extended downward. Accordingly, a punch-through scarcely occurs, and the depthwise component of a drain electric field is weakened, and its channel component is strengthened. Thus, channel hot electrons are easily generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a floating gate type insulated gate field effect transistor used in a nonvolatile MO8 semiconductor memory device.

[Conventional technology]

As shown in FIG. 5, a conventional EFROMK uses a floating gate type insulated gate field effect transistor as a memory element, and the mainstream programming method is CHE (channel hot electron) injection. In this method, in order to control the characteristics (threshold voltage and write characteristics) of the JEFROM, a structure is usually used in which a semiconductor substrate is doped with impurities to form a well (2).

[Problem that the invention seeks to solve]

In the EPROM using the conventional floating gate type insulated gate field effect transistor described above, the impurity concentration of the well is appropriately controlled in order to obtain a predetermined writing speed, so the threshold voltage during erasing is adjusted accordingly. determined by necessity. In the case of the conventional example, the threshold voltage is usually 2. Since the reading power supply voltage Vcc is set around 5.0V. In the case of Ov, this is not a problem.

However, when lowering Vcc, the threshold voltage must be lowered accordingly. Normally, it is considered to lower the well concentration as a process control, but instead, the electric field strength becomes weaker, resulting in a case where the writing speed becomes slow9 or does not meet the predetermined specifications.

Means for Solving Problems] The floating gate field effect transistor of the present invention has a source region and a drain region made up of impurity regions of a second conductivity type selectively formed in a semiconductor substrate of a first conductivity type, and a gate insulating region. A first conductive type semiconductor substrate comprising a portion of the first conductivity type semiconductor substrate immediately below the film.
a channel region, a highly doped second channel region provided below the first channel region and in contact with the bottom of the drain region and its vicinity; a second channel region provided below the drain region and the second channel region; The first conductivity type buried region has a higher concentration than the channel region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip mainly showing the main parts of a first embodiment of the present invention.

This embodiment consists of an N-type impurity region selectively formed in a P-type semiconductor substrate 1, a source region 5 and a drain region 4, and a part of the P-type semiconductor substrate 1 directly under a floating gate insulating film 9. a highly doped second channel region 12 provided below the first channel region 13 and in contact with the bottom of the drain region 4 and its vicinity; It includes a second channel region 12 and a high concentration P-type buried region 11a.

Next, the manufacturing method of this example will be explained.

FIGS. 2(1) to 2(e) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of the first embodiment.

First, as shown in FIG. 2(a), in a P-type semiconductor substrate I made of silicon, a P-well 2 is formed by implanting boron ions into a transistor forming region defined by a side insulating film 14 and performing forced diffusion. Form.

Next, as shown in FIG. 2(b), the field insulating film 3
A first gate isolation film (
Poron is applied to a predetermined depth through the floating gate insulating film 9).
A first ion-implanted layer]0 is formed by on-implantation.

Furthermore, in the same manner as before, as shown in Fig. 2 CC),
A first N-type doped polycrystalline silicon layer (7) is formed on the first gate insulating film (9), and when this polycrystalline silicon layer (7) is thermally oxidized, a second insulating film (control gate insulating film) formed from tζ is formed. 8) Further, a second Nq-doped polycrystalline silicon layer (6) is formed thereon and shaped into a predetermined shape.

Then, by a thermal oxidation method, an insulating film 14 is formed on the side surface of the first 2 ON type polycrystalline silicon layer.
Channel region 12. Floating gate electrode7. Control gate insulating film 8. Control game)? lt pole 6 is formed.

Next, as shown in FIG. 2(d)tc, poron ions are implanted into the second channel region 1 in a self-aligned manner with respect to the gate electrode.
Second ion implantation layers 11'a and 11'b having a higher concentration than the first ion implantation layer 11'a and 11'b are formed below the first ion implantation layer 11'a and 11'b.

Next, as shown in FIG. 2(e)K, ions of arsenic or phosphorus are implanted and heat treatment is performed to form the drain region 4.
A source region 5 is formed. Second ion implantation layer 11'a
, ll'b are P-type buried regions 11a, respectively.

11b.

Next, as shown in FIG. 1, an interlayer insulating film 15 is formed and contact holes are provided, and
16b.

FIG. 6 shows the depth Xj in the channel section of this embodiment.
) and impurity concentration Na; FIG.

In this embodiment, the threshold voltage during erasing is determined by the impurity concentration of the first channel region. Even if this threshold voltage is lowered, it is unlikely that the writing speed will be impaired as in the conventional example. In other words, the channel hot electrons (hereinafter referred to as CHE) injected into the floating gate jaL pole have the following mechanism:
It is accelerated by the channel direction component of the drain electric field and gains energy. When the obtained energy exceeds the barrier height of 3.2 eV at the silicon-silicon oxide film interface, injection into the floating gate electrode becomes possible. Therefore, the injection efficiency increases as the electric field component in the channel direction increases. Although the electric field in the channel direction can be increased by increasing the drain voltage, the upper limit is given by the punch-through voltage between the source and drain. Then,
The depletion layer extension that causes punch-through tends to occur near the bottom of the drain region. In this embodiment, the highly doped second channel region is provided exactly at that portion, and there is also a buried region below the drain region, making it difficult for the depletion layer to extend downward from the drain region.

Therefore, not only is punch-through difficult to occur, but also the depth-direction component of the drain electric field is weakened and the channel-direction component is strong, so it can be said that the structure is advantageous for the generation of CHE.

FIG. 3 is a sectional view of a semiconductor chip showing the main parts of a second embodiment of the present invention.

This embodiment is the same as the first embodiment except that the first channel region and the second channel region are comprised of a second epitaxial layer 18 and a first epitaxial layer 17, respectively.

Next, the manufacturing method of this example will be explained.

FIGS. 4(a) to 4(d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of the second embodiment.

First, as shown in FIG. 4(a), a P-type semiconductor base plate 1
A first epitaxial layer 17, which is also P-type and has a higher concentration than the base plate, is provided on the substrate. After that, KEPROM
A P-type second epitaxial layer 18 is formed which determines the threshold voltage during erasing. At this time, the second epitaxial layer 18
The film thickness is at most the same as the depth of the source/drain diffusion region, and its concentration is lower than the concentration of the first epitaxial layer 17. Next, as shown in FIG. 4(b), the device region is divided with a field insulating film 3, and then a two-layer N-type polycrystalline silicon layer (7) is formed as shown in FIG. 4(C).
.

(6) is formed by a conventional method and shaped into a predetermined shape, and then, as shown in FIG. A second ion-implanted layer 3 is formed by implanting boron ions into the source/drain diffusion region to a predetermined depth in a self-aligned manner with respect to the gate electrode.
1' is formed.

Thereafter, as in the conventional case, as shown in FIG. 3, arsenic or phosphorus is ion-implanted to form a 5° source region and a drain region 4. Then, an interlayer insulating film 15 is formed by the CVD method [7. After patterning the contact hole, an aluminum layer and a keyaki layer are provided.

Since this embodiment uses an epitaxial layer, it has the advantage of requiring fewer ion implantation steps and being more suitable for mass production.

〔Effect of the invention〕

Based on the above explanation, the present invention provides a channel-direction component of the drain electric field by setting the concentration peak at a depth near the bottom of the source/drain region in the substrate concentration profile of the channel portion of the transistor as described above. is stronger, the occurrence rate of CHE becomes higher than before, and the writing speed becomes faster. This means that even if you lower the erase threshold voltage of a memory cell using this transistor, you can still obtain the same level of write speed as before.
This is effective when lowering the read voltage.

Furthermore, compared to the conventional type, even if the surface concentration of the first channel region is lowered, the concentration of the second channel region is sufficiently high, so that the extension of the depletion layer from the drain is suppressed, making punch-through less likely to occur. Therefore, it can be used in a region where the channel length is shorter than that of the conventional method, and has the effect of working more advantageously in terms of writing speed.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor chip showing the main parts of the first embodiment of the present invention, and FIGS. 2(a) to 2(e) are diagrams for explaining the manufacturing method of the first embodiment. 3 is a sectional view of a semiconductor chip arranged in the order of steps; FIG. 3 is a sectional view of a semiconductor chip showing main parts of a second embodiment of the present invention; FIGS.
Figure (d) is a cross-sectional view of a semiconductor chip arranged in the order of steps to explain the manufacturing method of the second embodiment, Figure 5 is a cross-sectional view of a semiconductor chip showing the main parts of a conventional example, and Figure 6 is a cross-sectional view of a semiconductor chip arranged in the order of steps to explain the manufacturing method of the second embodiment. FIG. 1 is an impurity concentration profile diagram of a channel portion in Example 1; 1... P-type semiconductor substrate, 1'... P-type semiconductor base plate, 2... P-well, 3...
・Field insulating film, 4...Drain region, 5
. . . Source region, 6 . . . Control gate electrode, 7 . . . Floating gate electrode, 8 . ...Floating gate insulating film, 1
0...--first ion implantation layer, lla, llb.
...P type embedded area% ll'a, ll'b...
...Second ion implantation layer, 12...Second
Channel region, 13...First channel region, 1
4... Insulating film, 15... Interlayer insulating film,
16a, 16b... Aluminum electrode, 17
・・・・・・First epitaxial eyebrow, 18・・・・・・
Second epitaxial layer. Agent Patent Attorney Susumu Uchihara Umasa Gate Zetsu Figure 2 Figure 3 Figure 4 Figure 4

Claims (1)

[Claims] a source region and a drain region made of a second conductivity type impurity region selectively formed in a first conductivity type semiconductor substrate;
A first channel region formed of a part of the first conductivity type semiconductor substrate directly under the gate insulating film, and a highly doped second channel region provided below the first channel region and in contact with the bottom of the drain region and its vicinity. and a buried region of a first conductivity type provided below the drain region and the second channel region and having a higher concentration than the second channel region.