JP2975213B2 - MOS memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS memory device for writing information by injecting carriers into a floating gate by inter-band tunneling.

[0002]

2. Description of the Related Art MO having a floating gate structure
S memory devices have been put to practical use. In this conventional MOS memory device, a hot electric carrier is generated when writing or erasing information, so that a strong electric field strength is required, and therefore a high power supply voltage has to be used. As a solution to this drawback, there has been proposed a MOS memory device in which carriers are injected into a floating gate using inter-band tunneling. In this MOS memory device, a transition region having the same conductivity type as the substrate and having a uniform impurity concentration of about 10 ¹⁸ cm ⁻³ higher than the impurity concentration of the substrate is formed immediately below the floating gate. Then, by applying a gate voltage, a large band bend is generated in the transition region, and this band bend causes band-to-band tunneling, and the generated carrier is directly or further multiplied by impact ionization and injected into the floating gate. Information is written.

[0003] An MO utilizing this inter-band tunneling
The S memory device has a great advantage that information can be written with higher efficiency than the conventional memory device using FN injection.

[0004]

FIG. 4 is an energy diagram of a conventional MOS memory device using band-to-band tunneling. In the conventional MOS memory device, since the impurity concentration distribution in the transition region for generating carriers is formed uniformly along the depth direction of the substrate, the band bending becomes maximum near the interface with the gate insulating film, As a result, the part having the highest tunneling probability is located near the interface. As a result, as shown in FIG. 4, there is a problem that the carrier injection energy into the floating gate is low because the potential energy of the carrier generated by the inter-band tunneling is lower than the height of the potential barrier of the insulating film.

Accordingly, an object of the present invention is to provide a MOS memory device which eliminates the above-mentioned drawbacks, further improves the efficiency of carrier injection into the floating gate, and has excellent write performance.

[0006]

SUMMARY OF THE INVENTION A MOS memory device according to the present invention comprises a semiconductor substrate of one conductivity type, source and drain regions of opposite conductivity type formed on the semiconductor substrate, and a semiconductor substrate formed on the semiconductor substrate. A first gate insulating film, a floating gate electrode formed on the first gate insulating film, a control gate electrode formed on the floating gate electrode via a second gate insulating film, and the first gate A transition region of one conductivity type formed so as to face the floating gate electrode with an insulating film interposed therebetween, and generating band-to-band tunneling; and an opposite conductivity type on a side of the transition region in contact with the first gate insulating film. Having a shallow impurity concentration layer, and having a PN junction between a far side and a near side of the transition region from the first gate insulating film, or A shallow impurity concentration layer in which the impurity concentration is thinner or zero than the substrate side, or a shallow impurity concentration layer containing an impurity of the opposite conductivity type and partially or entirely carrier-compensated on a side in contact with one gate insulating film. Wherein the effective carrier concentration of the transition region on the side closer to the first gate insulating film is smaller than the effective carrier concentration on the side farther from the first gate insulating film. By doing so, the following effects can be obtained. That is, at the time of writing (or erasing) of the memory, the position where the band bending gradient occurs and the inter-band tunneling probability becomes maximum is located at a position away from the interface with the gate insulating film and at a higher potential energy. Can be. As a result, carriers generated by band-to-band tunneling have high potential energy, and when they reach the interface with the gate insulating film, they are injected into the insulating film with high energy, so that the injection efficiency is dramatically increased. Can be done.

[0007]

FIG. 1 is a sectional view showing the structure of an example of a MOS memory device according to the present invention. In this example, N channels M
The OS memory device will be described. Field oxide films 2a and 2b for element isolation are formed on a P-type substrate 1. This MO
The S memory device has an n ⁺ source region 3 and a drain region 4 formed by an ion implantation method, and a gate portion is formed between the source region and the drain region. This gate portion is formed on the surface of the substrate 1 and has a first gate insulating film 5 made of SiO _{2, a} floating gate 6 made of polysilicon doped with impurities, a second insulating film 7 and a control made of polysilicon. Gate electrode 8. A transition region 9 for generating carriers by band-to-band tunneling is formed between the source region 3 and the drain region 4 of the substrate 1. The transition region 9 is formed in a substrate surface region adjacent to the first gate insulating
A first transition region 9a having an impurity concentration higher about 10 ¹⁸ cm ^-3 than the impurity concentration of the substrate in the same conductivity type as the first transition region
It has a second transition region 9b formed at a position deeper than the substrate 9a and having the same conductivity type as that of the substrate and having an impurity concentration of about 10 ¹⁹ cm ^-3 . This transition region can be formed as follows. Before the gate portion is formed, boron, which is an impurity having the same conductivity type as that of the substrate, is ion-implanted from the surface side of the substrate with a high energy of 100 KeV or more. This ion implantation is performed so as to be implanted to a depth of about 0.1 μm or more from the surface. Next, arsenic, an impurity of the opposite conductivity type to the substrate,
Ion implantation is performed using an oxide film with a thickness of 300 mm or more with an energy of 50 KeV or less. The arsenic is implanted so as to be implanted to a depth near the surface of the substrate, for example, 500 ° or less. Thereafter, an SiO ₂ layer for forming the first gate insulating film 1 is deposited on the substrate surface by, for example, thermal oxidation by a rapid thermal process or a CVD method. As a result, as shown in FIG. 1, the substrate 1 is located immediately below the first gate insulating film 5.
A first transition region 9a of the opposite conductivity type and a second (a) transition region 9b of the same conductivity type as the substrate 1 and having an impurity concentration higher than that of the first transition region 9a are formed adjacent to each other. .
FIG. 2 diagrammatically shows the impurity concentration distribution in this transition region.
Further, an interlayer insulating film 9 is formed on the semiconductor substrate, and a contact hole is formed.
A source electrode and a drain electrode are formed.

Next, writing of information will be described. At the time of writing, a drain voltage of about 8 V is applied between the source and the drain, and a gate control voltage of 8 V is applied to the control gate electrode 8. FIG. 3 shows the energy state in the transition region 9 at this time. As shown in FIG. 3, a band curve having a steep slope is formed in the second transition region 9b having a high impurity concentration. Since the potential energy at the portion where the steep band bending is formed is located at an energy position higher than the top of the potential barrier of the first gate insulating film 5, the carriers generated by the inter-band transition are not applied to the first gate insulating film. The probability of exceeding the potential barrier is further increased.

The present invention is not limited to the above-described embodiment, and various changes and modifications are possible. For example, in the above-described embodiment, an N-channel MOS memory device has been described. However, it is needless to say that the present invention can be applied to a P-channel MOS memory device. Further, as shown in FIG. 2B, the impurity concentration of the first transition region adjacent to the gate insulating film is made lower than the impurity concentration of the second transition region and the substrate, and the effective carrier concentration is made second. It is also possible to lower the effective carrier density in the transition region.

[0010]

As described above, according to the present invention, a shallow impurity concentration layer having a conductivity type opposite to a deep portion of a transition region is provided on a side of a transition region where band-to-band tunneling occurs in contact with a gate insulating film. A PN junction is formed between the side in contact with the gate insulating film in the region and the substrate side away from the gate insulating film, or the effective carrier concentration on the side in contact with the gate insulating film in the transition region is set to So that it is lower than the side. As a result, the position where the gradient of band bending at the time of writing (or erasing) of the memory is large and the tunneling probability between bands is the maximum is located at a position away from the interface with the gate insulating film and at a higher potential energy. be able to. As a result, the carriers generated by band-to-band tunneling have high potential energy, and when they reach the interface with the gate insulating film, they have high energy. Therefore, the probability of injection into the gate insulating film is high, and the injection efficiency is dramatically increased. Can be increased. Therefore, the information writing time can be shortened, the speed can be increased, and moreover, the gate voltage at the time of writing the information can be reduced, and the durability and reliability of the device can be further improved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a configuration of an example of a MOS memory device according to the present invention.

FIG. 2 is a diagram showing a concentration distribution in a depth direction of a transition region.

FIG. 3 is an energy diagram showing an energy state when a gate voltage is applied.

FIG. 4 is an energy diagram showing an energy state when a gate voltage of a conventional MOS memory device is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2a, 2b Field oxide film 3 Source region 4 Drain region 5 First gate insulating film 6 Floating gate electrode 7 Second gate insulating film 8 Control gate electrode 9 Transition region

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-101272 (JP, A) JP-A-3-262158 (JP, A) JP-A-63-205964 (JP, A) JP-A-63-205 196078 (JP, A) JP-A-3-54869 (JP, A) JP-A-63-40377 (JP, A) JP-A-4-93086 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/8247 H01L 27/115 H01L 29/78 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A semiconductor substrate of one conductivity type, source and drain regions of opposite conductivity type formed on the semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, and a first gate insulating film A floating gate electrode formed on the film, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and facing the floating gate electrode with the first gate insulating film interposed therebetween. And a transition region of one conductivity type that generates band-to-band tunneling. A band voltage is applied to the control gate electrode to generate band-to-band tunneling in the transition region, and the generated carrier is transferred to the floating gate. In a MOS memory device for writing information by injecting into the first region, the first gate of the transition region On the side in contact with the Enmaku has a shallow impurity concentration layer of opposite conductivity type, MOS memory device characterized by having a PN junction between the far side and near side from the first gate insulating film of said transition region. 2. The MOS memory device according to claim 1, wherein an impurity concentration on the side of the transition region in contact with the first gate insulating film is lower than that on the substrate side of the transition region or zero. It has a shallow impurity concentration layer, or has a shallow impurity concentration layer partially or wholly carrier-compensated containing an impurity of the opposite conductivity type, and has an effective carrier concentration near the first gate insulating film in the transition region. Is smaller than the effective carrier concentration on the far side.