JP2557833B2 - Semiconductor integrated circuit device having test circuit and test method thereof - Google Patents

Description

DETAILED DESCRIPTION [Outline] In a gate array type large-scale integrated circuit device having a test circuit, an arbitrary basic gate cell can be selected and tested regardless of the operation of a logic circuit. is there.

[Industrial applications]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a gate array type large scale semiconductor integrated circuit device having a test circuit (hereinafter referred to as a gate array type LSI) and a test method thereof.

[Prior Art] In recent years, the demand for gate array type LSI, which is a typical form of semi-custom LSI, is increasing due to the high degree of freedom based on the logic design on the user side. Along with this, the scale of operation is increasing and the integration is increasing, and the operation of the internal gate is also becoming complicated. In order to test the performance of such a gate array type LSI before handing it to the user side, some kind of test circuit is built in and tested in addition to the normal logic circuit.

A commonly used test method is a so-called scan path method, in which a switch circuit and a combinational circuit are installed separately from a logic circuit and an attempt is made to judge from an output obtained by a predetermined input. As a more specific method
LSSD (Level Sensitive Scan Design) has been proposed. Since these methods are already well known, detailed description thereof will be omitted.

[Problems to be solved by the invention]

As described above, due to the increase in the scale of the gate array type LSI, the width of the capacity distribution generated by the circuit layout is expanded, resulting in a decrease in the logical operation speed. In addition, it is becoming more and more difficult to observe the operating state of the internal gate due to high integration. With respect to such problems, in the former case, a method of dividing the inside of a chip by layout,
A method of reducing the load dependency by using a bipolar MOS circuit has been proposed, and for the latter, an attempt has been made to incorporate a test circuit by the scan path method represented by the LSSD method described above.

However, the latter method requires an extra circuit for testing as described above in addition to the normal logic circuit. As a result, the layout becomes complicated, and the expansion of the layout capacity distribution width lowers the operation speed and hinders high integration. Further, as the logic circuit becomes larger in scale, the test circuit also becomes larger in scale, resulting in a longer test pattern and an increase in test time.

[Means and Actions for Solving Problems]

The present invention is to provide a gate array type LSI having a test circuit which solves the above problems and a test method thereof, and FIG. 1 shows a basic configuration diagram of the present invention. In FIG. 1, Gi is a basic gate cell composed of either one of a NAND gate and a NOR gate, and a plurality of basic gate cells are connected in accordance with user specifications to obtain a predetermined logic operation. A1i is an access means composed of, for example, an AND gate, and in the embodiment, the emitter of the multi-emitter transistor forming the basic gate Gi is used. Also, Sc
i is a plurality of row selection lines, which are selected by the row selection means SC during the test, and Sli is a plurality of example selection lines, which are selected by the column selection means SL during the test. Further, Mi is a plurality of read lines (monitor lines), which are connected to the output of the basic gate Gi through the diode means DI. The data of these monitor lines are monitored by the monitor means M. As described above, the gate array type LSI according to the present invention has a plurality of access means A1.
It has a test circuit composed of i, row selection line Sci, column selection line Sli, monitor line Mi, row selection means SC, column selection means SL, monitor means M and diode means DI.

As described above, the test circuit has a test circuit completely separate from the user-specified logic circuit configured by connecting the respective basic gates Gi, and access to each of the basic gates Gi is different from the logic circuit in the test circuit. It has a possible selective access means Ai. The input from this access means makes it possible to force the output of each elementary gate independently of the other elementary gates to at least one logic state, namely a high (H) level or a low (L) level. The test is then performed by monitoring the output of the accessed basic gate.

〔Example〕

FIG. 2 is a block diagram of an embodiment of a gate array type LSI having a test circuit according to the present invention. In FIG. 2, reference numeral 1 is a gate array type LSI chip, 2 is a plurality of basic gate cells arranged in a matrix on the chip, and in the present embodiment, it is constituted by either one of a NAND gate and a NOR gate. To be done. The wiring between these basic gates is connected to the output of any of the basic gates and the input of any of the other basic gates, for example, as shown by the dotted line, based on the logical operation desired by the user. Further, the input of each basic gate 2 is provided with test input terminals T ₁ and T ₂ , respectively, and connected to a row selection line and a column selection line which will be described later. Reference numeral 3 is a row selection line provided in the row direction of the gate array, and reference numeral 4 is a column selection line provided in the column direction of the gate array. The row select lines S _c1 , S _c2 ... S _cn are connected to the test terminal T ₁ of each basic gate, and the column select lines Sl ₁ , Sl ₂ ... Sl _n are connected to the test terminal T ₂ of each basic gate. . Reference numeral 5 denotes a plurality of monitor lines, which are connected to each basic gate through, for example, a diode 6 as a diode means and output the output state of the basic gate to a monitor means described later. _Reference numeral 7 is a row selection means for selecting any of the row selection lines S _{c1 to} S _cn , 8
Is a column selecting means for selecting any _one of the column selecting lines Sl _{1 to} Sl _n , and 9 is a monitoring means for monitoring the output state of each basic gate via the monitor line 5.

In such a configuration, when the gate array type LSI is tested, the failure of all the basic gates can be detected by the fixed test pattern regardless of the logic operation of the logic circuit. That is, there are basically four types of failure patterns, which are an output S0 failure, an output S1 failure, an input S0 failure, and an input S1 failure. The S0 fault is a fault that is fixed at the L (low) level, and the S1 fault is a fault that is fixed at the H (high) level. The "output S0 fault" is all row selection lines and This is a failure detected when the column selection line is set to L level. As is apparent from the circuit configuration of the basic gate shown in FIG. 5, the output of the basic gate should be at the H level when the L level is input to the input. That is, the expected output value of the basic gate is at the H level. However, if any of the basic gates has some kind of failure and the output is at the L level, the output of the basic gate is connected to the monitor line through the diode means, and therefore the monitoring means can determine that the failure has occurred. . That is, the "output S0 failure" is a failure in which the L level appears in any one of the basic gates when the expected output value of the basic gate is the H level.

The "output S1 failure" is a detected failure with any of the row selection lines Sci and column selection lines Sli at the H level.
In this case, the input of the selected basic gate is H level because the other basic gates output H level, and the basic gate is released from the compulsory state at the time of the test. It is enabled, and its expected output value becomes L level. If the output of the basic gate is L level, it is detected by the monitoring means through the monitor line connected to it, but if the output is H level due to some failure, it is H level like other basic gate outputs. Therefore, it can be determined that the basic gate has a failure.

The "input S0 failure" of is related to the "output S1 failure" of, and as described above, when "output S1 failure", the expected output value of the basic gate is L level. At this time, if any of the input terminals of the basic gate is originally at the H level but is at the L level, its output becomes the H level. That is, since the outputs of all the basic gates other than the basic gate are at the H level, the H level should be input to all the inputs of the basic gate. However, due to some failure, the input is L
When it is at the level, its output becomes the H level,
In this case, it is determined that one of the inputs is out of order.

The "input S1 failure" is a failure in which one of the inputs of the basic gate is at the H level even though the input is originally at the L level. Detecting by providing a set of selective access means.

If all the basic gates are implemented using the above-mentioned failure patterns, the output S0 failure, the output S1 failure, and the input S0 failure can be easily detected. As described above, such a test circuit can test each basic gate independently of the logic circuit operation.

In the above description, the output S0 failure, the output S1 failure, the input S0 failure, and the input S1 failure are divided into four types, but the failure of the gate cell input terminal, the failure of the gate cell output terminal, and the wiring between them. It doesn't mention until the failure is specified. That is, for example, in the output S0 failure and the input S0 failure, it is not known whether the gate cell output terminal has a failure, the input terminal in the next stage has a failure, or the wiring between them has a failure (short-circuited to 0 potential).

However, this is because, in the present invention, a failure in the vicinity thereof is regarded as an “equivalent failure” and a countermeasure is taken.
As a result, the "quick circuit test" that is the problem to be solved by the present invention
Is achievable. In the above description of each failure, "some kind of failure" means that it is not specified whether there is a disconnection, a short circuit, an input terminal failure, or an output terminal failure.

FIG. 3 is a basic configuration diagram of another embodiment of a gate array type LSI having a test circuit according to the present invention. In this example,
In addition to the selective access means A1i shown in FIG. 1, an independent second access means A2i is provided for each basic gate. Therefore, another row selection line Sci ′ and a column selection line Sli ′ are added. By providing the second access means A2i, the above-mentioned "input S1 failure" can be easily detected. That is, using this basic configuration, it is possible to easily detect all the failure patterns of “output S0 failure”, “output S1 failure”, “input S0 failure” and “input S1 failure”.

FIG. 4 is a block diagram of an embodiment of the basic configuration shown in FIG. In FIG. 4, the row selection line Sci and the column selection line Sli
Is set to H level, the basic gate Gin is enabled by the first access means A1i. Basic gate G at this time
The expected output value of in is L level. On the other hand, if the output of the gate G ₁₁ is connected to one of the inputs of the gate Gin, the expected output value of the gate G ₁₁ is at the H level because it is the state of the expected output value at the time of the test. This H level is input to the gate Gin.

The output of gate G ₁₁ In this case selects the second access means A2 ₁ gate G ₁₁ varies forced to L level.
Since this L level is taken in by the input of the gate Gin, the output of the gate Gin changes from the L level to the H level. This change is determined via the monitor line. That is, if L changes to H, it is judged that at least the relationship between the output and the input between the gate G ₁₁ and the gate Gin is normal. However, if there is some failure between the output of gate G _{11 and} the input of gate Gin and the output of gate G ₁₁ is forced to the L level, the input of gate Gin will still be at the H level. In this case, since the output of the gate Gin does not change, the monitor means determines that there is a failure. That is, in this case, since the input side is still in the H level state, it is judged as "input S1 failure".

In this way, for all gates connected to the inputs of the gate Gin, the second access means are sequentially selected, and the output state is forcibly changed so that the gate Gi
By monitoring the state of the output of n, the connection state between them can be tested and "input S1 failure" can be detected.

As is clear from the block diagram of FIG. 4, when the above-mentioned four failure patterns are detected, the first
Of the selective access means A1 _{1 to} A1 _n of the row selection line S
with _c1 to S _cn and column select lines Sl ₁ to SL _n, 3 one fault pattern described in FIGS. 1 and 2, i.e., "output S0 failure", "outputs S1 failure" and "inputs S0 Perform "fault" detection. After these tests are completed, the other row selection lines S _c1 ′ to S _cn ′ and the column selection lines Sl ₁ ′ to S ₁ shown in FIG.
l _n ′ and the second selective access means A2 ₁ provided therein
By sequentially selecting ~ A2 _n , the "input S
"1 failure" can be detected.

FIG. 5 shows a concrete circuit example incorporating a basic gate and first and second access means. In Figure 5, Gi
Is a basic gate circuit with 2-input NAND. A1i is an emitter input terminal (T ₁ ,
T _2), A2i is are transistors of the second access means. As can be seen, the multi-emitter input terminal T ₁
And T ₂ correspond to the test terminals T ₁ and T ₂ of the NAND gate of the embodiment shown in FIG. Two emitter input terminals
IN ₁ and IN ₂ are each connected to the output of another basic gate (see the dotted line connecting the gates in Fig. 2) and output
OUT is connected to the input of another basic gate. Since the operation row selection line Sci or Sli of this circuit is a multi-emitter transistor Tr ₁ if L level pulls the base potential of the Tr ₂ to ON, Tr ₂ is OFF, as an output (OUT) level,
If both the row selection lines Sci or Sli are at H level, the other inputs are at H level, so the multi-emitter transistor Tr ₁
Turns off and Tr ₂ recovers and turns on, so the output (OUT) becomes L level.

In such a state, when the base of the multi-collector transistor Tr ₃ of the second access means A2i is selected at the H level and the emitter is selected at the L level, the transistor Tr ₃ is turned on, which causes the output (OUT). H level changes to L level. In this way, the row selection line Sci ′
Can be changed to the L level and the column selection line Sli 'to the H level to change the output (OUT) of the basic gate. In this case, the second of the multi-transistor Tr ₃
The collector of is connected to an appropriate biasing means, so that the transistor T connecting the output (OUT) and the monitor line
Since the base of r ₄ becomes L level, the transistor Tr ₄ is cut off, and the L level switched by the second access means is prevented from being detected by the monitor means.

〔The invention's effect〕

According to the present invention, each basic gate and its input / output connection can be tested separately from the logic circuit, and the test can be performed in a predetermined pattern to detect a failure, which enables a quick test. Yes, all test pattern creation is automated and easy.

[Brief description of drawings]

 FIG. 1 is a block diagram showing the basic constitution of the present invention, FIG. 2 is a block diagram showing an embodiment of the basic constitution of FIG. 1, FIG. 3 is a block diagram showing another basic constitution of the present invention, and FIG. FIG. 4 is a block diagram of the embodiment, and FIG. 5 is a concrete circuit diagram of FIG. (Description of symbols) 1 ... Gate array type LSI chip 2 ... NAND gate 3 ... Row selection line 4 ... Column selection line 5 ... Monitor line 6 ... Diode means 7 ... Row selection means 8 ... Column Selection means 9 ... Monitoring means

Claims (11)

(57) [Claims] 1. A NAND gate or a NOR gate 1
A semiconductor integrated circuit device in which gate cells of different types and having first and second output logic states are arranged in a matrix, and wiring is provided between the plurality of gate cells to perform a predetermined logic circuit operation. Row selection line for testing and row selection means for selecting the row selection line, column selection line for testing and column selection means for selecting the column selection line in the column direction of the gate cell array, arrangement of gate cell array Direction monitoring line and monitor means for monitoring the data of the read line, switch means for connecting the read line and the output of the gate cell, and the row selecting means and column provided in each of the plurality of gate cells. Selective access means for controlling the output state of the corresponding gate cell selected by the selection means to the first logic state irrespective of the logic circuit operation. The semiconductor integrated circuit device having a test circuit, characterized and. 2. A device according to claim 1, wherein said switch means comprises a diode or a transistor, and the output state of the corresponding gate cell turns on in the second logic state. 3. A device according to claim 1, wherein the selective access means or the first selective access means are at least two emitters of an input transistor of a NAND or NOR gate. 4. A plurality of gate cells made of at least one of a NAND gate and a NOR gate and having a first and a second logic state are arranged in a matrix, and the plurality of gate cells perform a predetermined logic circuit operation. In a semiconductor integrated circuit device in which wiring is provided between the first and second row selection lines for testing in the row direction of the gate cell array, row selection means for selecting the row selection line, and first in the column direction of the gate cell array. Column selection lines for the first and second tests, column selection means for selecting the column selection lines, read lines for monitoring in the array direction of the gate cell array and monitor means for monitoring the data on the read lines, and the read lines. Switch means for connecting to the output of the gate cell; provided in each of the plurality of gate cells; selected by the first row selecting means and the first column selecting means; First selective access means for controlling a state to a first logic state irrespective of the logic circuit operation, and second row selection means and second column selection means provided in each of the plurality of gate cells. And a second selective access means for controlling the output state of the corresponding gate cell to the second logic state independently of the logic circuit operation of the gate cell. Semiconductor integrated circuit device. 5. An apparatus according to claim 4, wherein said switch means comprises a diode or a transistor, and the output state of the corresponding gate cell turns on in the second logic state. 6. A device according to claim 4, wherein said selective access means or said first selective access means are at least two emitters of a NAND or NOR gate input transistor. 7. The switch means comprises a diode or a transistor and the output state of the corresponding gate cell turns on in a second logic state, the second selective access means changing the state of the switch means. An apparatus as claimed in claim 4, wherein the output state of the gate cell is controlled without control. 8. The gate cell comprises a NAND gate, and the switch means connected to the gate cell comprises a transistor having a collector connected to the read line and an emitter connected to the output of the gate cell. The selective access means of comprises a multi-collector transistor, the first collector of the multi-collector transistor being commonly connected to a power supply for driving the transistor,
The second collector of the multi-collector transistor is connected to the output of the gate cell, and the base and emitter of the multi-collector transistor are connected to the second row selection line and column selection line, respectively. The device according to paragraph. 9. One of a NAND gate and a NOR gate.
In a method for testing a semiconductor integrated circuit device, the gate cells having different types of first and second output logic states are arranged in a matrix and wiring is provided between the plurality of gate cells to perform a predetermined logic circuit operation. In the semiconductor integrated circuit device, a row selection line for testing and row selection means for selecting the row selection line in the row direction of the gate cell array, and a column selection line for testing and the column selection line in the column direction of the gate cell array. A column selecting means for selecting, a read-out line for monitoring in the array direction of the gate cell array, a monitor means for monitoring the data on the read-out line, a switch means for connecting the read-out line and the output of the gate cell, Selected by the row selecting means and the column selecting means provided in each of the gate cells,
A first selective access means for controlling the output state of the corresponding gate cell to a first logic state irrespective of the logic circuit operation, and a test row connected to the first selective access means. A signal of a predetermined level is given to the selecting means and the column selecting means, and the output state of an arbitrary gate cell is controlled by the selective access means so as to be the first logic state irrespective of the operation of the logic circuit. Is detected by the switch means to determine whether the output state of the arbitrary gate cell is in the first logic state or not. 10. A gate cell, which comprises one of a NAND gate and a NOR gate and has first and second output logic states, is arranged in a matrix, and between the plurality of gate cells so as to perform a predetermined logic circuit operation. In a method of testing a semiconductor integrated circuit device having wirings in the gate array, the semiconductor integrated circuit device includes a row selection line for testing in a row direction of the gate cell array, a row selection means for selecting the row selection line, and a gate cell array. A column selecting line for testing and a column selecting means for selecting the column selecting line in the column direction, a read line for monitoring in the array direction of the gate cell array, a monitor means for monitoring data of the read line, and the read line. Switch means for connecting the output of the gate cell, and selected by the row selecting means and column selecting means provided in each of the plurality of gate cells,
A first selective access means for controlling the output state of the corresponding gate cell to a first logic state irrespective of the logic circuit operation, and a test row connected to the first selective access means. A signal of a predetermined level is given to the selection means and the column selection means, and the output state of all the gate cells in the preceding stage which outputs a signal to the input terminal of an arbitrary gate cell is operated by the respective first selective access means in the logic circuit. The output state of the arbitrary gate cell is controlled to be the second logic state by controlling the first logic state to be the second logic state irrespective of A method for testing a semiconductor integrated circuit device, comprising determining whether or not the output state of the gate cell is in the second logic state. 11. A plurality of gate cells made of at least one of a NAND gate and a NOR gate, and having a plurality of gate cells having a first and a second logic state are arranged in a matrix so as to perform a predetermined logic circuit operation. In a method of testing a semiconductor integrated circuit device having wiring between the first and second test row selection lines and a row selecting line for selecting the row selection line in a row direction of a gate cell array. Selection means, column selection lines for the first and second tests in the column direction of the gate cell array, column selection means for selecting the column selection line, and read lines for monitoring and the read lines in the array direction of the gate cell array. Means for monitoring the data of the above, a switch means for connecting the read line and the output of the gate cell, and a plurality of the gate cells provided in each of the first row selection means and the first column selection means. Means for controlling the output state of the corresponding gate cell to a first logic state regardless of the operation of the logic circuit; and a second selective access means provided in each of the plurality of gate cells. Second selective access means for controlling the output state of the corresponding gate cell selected by the row selecting means and the second column selecting means to the second logic state irrespective of the logic circuit operation of the gate cell. A row selection means and a column selection means for testing, which are connected to the first selective access means or the second selective access means, are provided with a signal of a predetermined level, and a signal is applied to an input terminal of an arbitrary gate cell. The output states of all the preceding-stage gate cells to be output are at least the first selective access means or the second
Controlling the output state of the arbitrary gate cell to the second logic state by controlling the first logic state regardless of the logic circuit operation of the preceding gate cell by the selective access means After that, a signal of a predetermined level is given to the row selecting means and the column selecting means for testing connected to the second selective access means, and the output state of the predetermined gate cell in the preceding stage gate cell is changed to the corresponding first The second selective access means controls the second logic state to be independent of the logic circuit operation of the predetermined gate cell, the output state of the arbitrary gate cell is detected by the switch means, and the arbitrary gate cell is detected. A method of testing a semiconductor integrated circuit device, comprising determining whether or not the output state of a gate cell is in a first logic state.