JPH08262111A - Method for indicating position of multiplex fault and semiconductor integrated circuit device using the method - Google Patents

Abstract

PURPOSE: To provide a method for indicating position of multiplex fault by which the indicating accuracy of a logically multiplex faults which has not been narrowed down can be indicated as single faults by indicating faulty positions to be retrieved at every output pin or output flip flop referring to a dictionary on faults and, at the same time, the fault analyzing time can be shortened. CONSTITUTION: A logic circuit in which a fault at one physical point is logically viewed as a multiplex fault has such a two-input OR/NOR output constitution that is provided with an OR logic function and NOR logic function, respectively inputs two input signals from input pins A and B, and respectively outputs OR logic output signals and NOR logic output signals from output pins C and D. The fault at one physical position in the logic circuit which is common to points 1 and 2 is discriminated by narrowing down the fault at the point 1 from the output pin C and the fault at the point 2 from the output pin D and ANDing the faults.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault location indicating technique for multiple faults, and more particularly to LSI (Large Scale Integration).
In the above highly integrated semiconductor integrated circuit device, the diagnostic data is created by the diagnostic simulation system which adopts the ternary logic (0/1 / X), and the diagnostic data is used for the test. And a technique effective when applied to a semiconductor integrated circuit device using the same, which is capable of pointing out a fault position of a functional defective product.

[0002]

2. Description of the Related Art For example, although not publicly known, as a technique studied by the inventor, nonstandard specifications and defects built in at the time of designing and manufacturing are left unremoved by a test, and the environment and time elapse. The failure caused by the occurrence of a defect due to the stress caused by does not affect the operation of the system when it is present, and the effect only appears when it is manifested as an error.

This fault is classified into a fixed fault and an intermittent fault according to the length of time it continues, and when the number of faults that can occur at one time in the target circuit is one, a single fault or a plurality of faults is generated. In case of individual faults, they can be classified as multiple faults, and it is considered that such fault location is indicated by the following flow.

(1). Using diagnostic data (LTF) and logic wiring information (LDF) by fault simulation, a "fault point that can be detected by that test" and an "output pin that can detect that fault" are set for each test. Create a "fault dictionary" in the form of a table.

(2). A test is performed using LTF, and from the results of the "test pattern number" which has become defective and "the output pin through which the fault in the test pattern has propagated",
Search the "fault dictionary" created in (1) and narrow down the fault location.

Regarding such a fault location technique, for example, on November 30, 1984, "LSI Handbook" edited by The Institute of Electronics, Communication and Information Engineers, P685-P68.
9 and the like.

[0007]

However, in the fault position pointing technique as described above, in the fault simulation, a fixed defect (single fault: always signal level "0" or (Fixed to "1")
Is assumed, while the "fault dictionary" search is
Since the system uses the "fault dictionary" as a key to search, in the case of "multiple faults" where multiple faults exist, even if it is possible to detect the presence of a fault, it is not possible to narrow down the fault location. .

That is, in the conventional fault location indicating method,
For example, even if there is a physical failure at one location such as a failure in the power supply system, it is difficult to logically narrow down the failures at a plurality of locations because the “failure dictionary” is not searched for each output pin.

Therefore, an object of the present invention is to find out what could not be logically narrowed down by multiple faults by pointing out the fault position by searching the "fault dictionary" for each output pin or output flip-flop through which the fault has propagated. It is an object of the present invention to provide a fault location method for multiple faults, which can improve the accuracy of indication as a single fault and shorten the failure analysis time, and a semiconductor integrated circuit device using the same.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the fault location method for multiple faults according to the present invention is applied to the fault location method for a logic circuit in the case where a single physical fault causes a logical multiple fault. A fault simulation of a logic circuit is performed using the diagnostic information and the logic arrangement information, and a fault dictionary is created in which a fault point that can be detected for each test is associated with an output pin or an output flip-flop of this fault. Test the logic circuit using, and search the fault dictionary using the output information that propagates the fault in the defective test pattern, and point out the fault location for each output information that propagates the fault in the logic circuit. Then, the physical failure position is narrowed down by taking the logical product of the respective results.

Specifically, when the fault position is pointed out, from the result of the test pattern number that has become defective in the logic circuit test and the output pin or output flip-flop to which the fault in this test pattern has propagated, Using the output pin or the output flip-flop as a key, the fault dictionary is searched to point out the fault position, and as the diagnostic data for pointing out the fault position, the data created by the diagnostic simulation system that uses the ternary logic is used. It was designed to be tested.

Further, the semiconductor integrated circuit device of the present invention uses the above-mentioned method for indicating a fault position of multiple faults to make the logic circuit LS.
The integrated circuit constitutes a semiconductor integrated circuit device having a high degree of integration of I or higher.

[0015]

According to the fault location method of multiple faults and the semiconductor integrated circuit device using the same, a logical multiple fault occurs logically due to a fault at one physical location (power source fault) in a logic circuit. If it appears (faults at two or more points), the fault position is indicated for each output pin or output flip-flop to which the fault propagates, and the logical product of each result is taken to narrow down the physical fault position. be able to.

That is, a fault dictionary is searched with the output pin or the output flip-flop as a key from the result of the defective test pattern number and the result of the output pin or the output flip-flop through which the fault in the test pattern propagates, and the logic is obtained. A fault that could not be narrowed down due to multiple faults (fault at one physical location) can be pointed out by improving the fault position pointing method.

As a result, diagnostic data is created by a diagnostic simulation system that employs three-valued logic, and the diagnostic data is used for testing. When pointing out the failure position of a non-defective product, the multiple failures can be logically pointed out as a single failure. Therefore, the hit rate of pointing out the failure position can be improved and the failure analysis time can be shortened.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a functional logic diagram showing a logic circuit of a semiconductor integrated circuit device to which a fault location method for multiple faults according to an embodiment of the present invention is applied, and FIG. 2 specifically shows this logic circuit. 3 is a circuit diagram, FIG. 3 is a chip configuration diagram showing a semiconductor integrated circuit device, and FIG. 4 is a flow chart showing a processing procedure of a fault location indicating method of multiple faults in the present embodiment.

First, a logic circuit of a semiconductor integrated circuit device to which the fault location method for multiple faults according to the present embodiment is applied will be described with reference to FIG.

The logic circuit of the semiconductor integrated circuit device according to the present embodiment is a logic circuit in the case where, for example, physically one failure causes a logically multiple failure, and has an OR logic function and a NOR logic function. Two input signals are input from input pins A and B respectively, and O is output from output pin C.
It has a 2-input OR / NOR output configuration in which an R logic output signal and a NOR logic output signal are output from the output pin D.

The logic circuit of this 2-input OR / NOR output configuration is, for example, an ECL (Emitter Coupling) as shown in FIG.
led logic) circuit, which is composed of five transistors Q1 to Q5 and resistors R1 to R6, and is a current switching logic circuit based on a differential amplifier circuit in which the emitters of the transistors Q1 to Q3 are commonly connected. The transistors Q1 and Q2 are connected in parallel to one of the differential amplifier circuits to form an OR gate, and the reference voltage VB is applied to the base of the other transistor Q3.

Regarding the operation of this ECL circuit, for example, when both the input voltages of the input pins A and B are lower than the reference voltage VB, the transistor Q3 turns on and the transistors Q1 and Q2 turn off. Q4
No base current is supplied to the transistor Q4 and the transistor Q4 is turned off (output “L”), but the base current of the transistor Q5 is supplied through the resistor R1.
5 is turned on (output “H”).

On the other hand, when one of the input voltages of the input pins A and B is higher than the reference voltage VB, the transistor Q1 or the transistor Q2 is turned on and the transistor Q3 is turned off. Contrary to the above, the base current is passed through the resistor R2. Is supplied, the transistor Q4 is turned on and the output is "H", and the transistor Q5 is turned off and the output is "L". Therefore, the transistors Q4 and Q5 have mutually opposite outputs, and the truth table of the output signal with respect to this input signal is as shown in Table 1.

[0025]

[Table 1]

Incidentally, such an ECL circuit is used as a basic circuit of an LSI developed for a large-sized computer which requires high speed performance as an ECL gate array.
As shown in FIG. 3, for example, the semiconductor chip of I has an array of 10 rows × 10 columns as one basic cell with four basic circuits, and the I / O cells are arranged on the outer periphery of this array. ing.

Next, with respect to the operation of the present embodiment, the processing procedure of the fault location indicating method will be described with reference to the flowchart of FIG.

For example, in FIG. 1, assuming a case where one physical failure occurs due to a failure of the power supply of the logic circuit and the like appears as a logical point-to-point failure,
A point failure will propagate to output pin C and a point failure will propagate to output pin D.

In this case, in the prior art, the output pin C
Since there is only one logical failure position that propagates to / D, there is no corresponding point, that is, a single degeneracy detected to search the failure dictionary for all output pins that propagate all failures. Since there is no failure, it is not possible to narrow down.

However, in this embodiment, by narrowing down the failure position for each of the output pins C / D, the point failure from the output pin C and the point failure from the output pin D can be narrowed down. In this case, it is determined that one physical point of the logic circuit having common points has a failure.

That is, as shown in FIG. 4, first, a fault simulation of a logic circuit is performed using diagnostic data and logic placement data, and a fault point that can be detected by this test for each test and an output pin that can detect this fault. A failure dictionary is created in a table format (steps 401, 40).
2). In addition, as this diagnostic data, three-valued logic (0 /
The data created by the diagnostic simulation system adopting 1 / X) is used.

Furthermore, the logic circuit is tested using the diagnostic data, and the result of the defective test pattern number and the output pin to which the fault in this test pattern has propagated is used to determine the fault dictionary using this output pin as a key. Search (steps 403, 404).

Then, the fault position is indicated for each output pin to which the fault of the logic circuit propagates, and the logical product of the respective results is taken to narrow down the physical fault position of the logic circuit (steps 405, 406).

Therefore, in the prior art, what could not be narrowed down logically due to multiple failures (physically at one location) is logically identified in the present embodiment by pointing out the failure position for each output pin. Multiple faults can be pointed out as a single fault.

Therefore, according to the fault location method for multiple faults according to the present embodiment, the fault dictionary is searched for each output pin through which the fault has propagated, and when logically it appears as multiple faults, it is physically set to 1. In a logic circuit that can be narrowed down to a failure at a location and is being tested using diagnostic data in a diagnostic simulation system that employs three-valued logic, the accuracy of pointing out the failure position of this logic circuit is improved. The failure analysis time of can be shortened.

Particularly, in pointing out a failure position of a functional defective product of a semiconductor integrated circuit device having a higher integration degree than LSI, a great effect can be obtained in terms of defect analysis efficiency and quality.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the fault location method of multiple faults of the present embodiment, the case where the fault location is pointed out for each output pin through which the fault propagates has been described, but the present invention is not limited to the above-mentioned embodiments. However, the present invention is also applicable to the case where the fault position is pointed out for each output flip-flop to which the fault propagates.

[0039]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, the failure simulation of the logic circuit is performed using the diagnostic information and the logic arrangement information, and the correspondence between the failure information that can be detected by this test and the output information that can detect this failure is tabulated for each test. Create a fault dictionary and test the logic circuit using the diagnostic information,
Output information that propagates the fault in the defective test pattern, for example, the fault dictionary is searched for each output pin or output flip-flop, the fault position is pointed out, and the logical product of the respective results is taken to determine the physical fault. By narrowing down the positions, multiple failures can be pointed out as a single failure when the failure at one location logically looks like multiple failures.

As a result, it is possible to improve the accuracy of pointing out the failure position of the logic circuit under test using the diagnostic data employing the three-valued logic, and shorten the failure analysis time. In identifying the failure position of the function defective product of the semiconductor integrated circuit device having the high integration degree as described above, it is possible to improve the efficiency and quality of failure analysis.

[Brief description of drawings]

FIG. 1 is a functional logic diagram showing a logic circuit of a semiconductor integrated circuit device to which a fault location method for multiple faults according to an embodiment of the present invention is applied.

FIG. 2 is a circuit diagram specifically showing a logic circuit in this embodiment.

FIG. 3 is a chip configuration diagram showing a semiconductor integrated circuit device in the present embodiment.

FIG. 4 is a flowchart showing a processing procedure of a fault location indicating method of multiple faults in the present embodiment.

[Explanation of symbols]

 Q1 to Q5 Transistors R1 to R6 Resistors A, B Input pins C, D Output pins

Claims (4)

[Claims] 1. A method for indicating a fault position of a logic circuit in the case where a fault physically occurs at one place and logically looks like a multiple fault, wherein a fault simulation of the logic circuit is performed by using diagnostic information and logic placement information. For each test, create a fault dictionary in the form of a table showing the correspondence between the fault information that can be detected by this test and the output information that can detect this fault, and then test the logic circuit using the diagnostic information. , A fault dictionary is searched using output information in which a fault in a defective test pattern propagates, and a fault position is pointed out for each output information in which a fault in the logic circuit propagates, and a logic of each result A fault location method for multiple faults, which is characterized by narrowing down physical fault locations by taking a product. 2. The fault location method for multiple faults according to claim 1, wherein when the fault location is identified, the test pattern number that has become defective in the test of the logic circuit and the fault in this test pattern are A fault position pointing method for multiple faults, wherein the fault position is pointed out by searching the fault dictionary with the output terminal or the output flip-flop that has been propagated as a key and using the output terminal or the output flip-flop as a key. 3. The method for indicating a fault position of multiple faults according to claim 1 or 2, wherein data created by a diagnostic simulation system that employs ternary logic is used as diagnostic information for indicating the fault position. A fault location method for multiple faults characterized by performing a test. 4. A semiconductor integrated circuit device using the fault location method for multiple faults according to claim 1, 2 or 3, wherein the logic circuit constitutes a semiconductor integrated circuit device having a higher degree of integration than an LSI. A semiconductor integrated circuit device comprising: