JPS62119953A - Semiconductor integrated circuit device provided with testing circuit - Google Patents

Abstract

PURPOSE:To ensure a speedy testing by a method wherein the test of a given basic gate cell in a gate array LSI may be accomplished irrespective of the behavior of a logic circuit. CONSTITUTION:A basic gate cell Gi is constituted of a NAND or NOR gate and connection is made to customers' specifications for the realization of a prescribed logical behavior. An access means Ali is constituted of an AND gate and an emitter of a multi-emitter transistor is used. A plurality of row-selecting lines Sci is selected by a selecting means SC for a test and a plurality of column-selecting lines Sli is selected by a selecting means SL for a test. A read line Mi is connected to the output of a basic gate Gi with the intermediary of a diode DI for monitor by a monitoring means M. In this way, a basic gate Gi is incorporated into a test circuit that is totally different from a logic circuit built to customer's specifications. Access to each basic gate Gi is selectively gained by using an access means Ai irrespective of customers' logic circuits, a signal from an access means forces the output of each basic gate into a certain logical status without affecting the other basic gates for the monitor and test of the output of the gate made access to. With a device designed as such, a prescribed pattern may apply to testing, ensuring a speedy testing.

Description

[Detailed Description of the Invention] [Summary] In a gate array type large-scale integrated circuit device having a test circuit, any basic gate cell can be selected and tested regardless of the operation of the logic circuit. It is.

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and more particularly to a gate array type large-scale semiconductor integrated circuit device (hereinafter referred to as gate array type LSI) having a test circuit.

[Conventional technology]

In recent years, the demand for gate array type LSIs, which are a typical form of semi-custom LSIs, has been increasing because of their high degree of freedom based on the user's logic design. Along with this, devices are becoming larger and more highly integrated, and the operation of internal gates is also becoming more complex. In order to test the performance of such a gate array type LSI before handing it over to the user, some kind of test circuit is usually installed in addition to the logic circuit to perform the test.

A commonly used test method is the so-called scan bus method, in which switch circuits and combinational circuits are installed separately from logic circuits, and judgments are made from the outputs obtained from predetermined inputs.

A more specific method is LSSD (LevelSe
nsitive 5can Design) has been proposed.

Since these methods are already well known, detailed explanation will be omitted.

[Problem that the invention seeks to solve]

As mentioned above, as the scale of gate array type LSI increases, the width of the capacitance distribution caused by the circuit layout increases, resulting in a decrease in the logical operation speed. Furthermore, with the increase in integration, it has become increasingly difficult to observe the operational status of internal gates. To address these problems, conventional methods have been proposed for the former, such as dividing the inside of the chip in terms of layout, and using bipolar MO3 circuits to reduce load dependence. L.S.S.D.
Attempts have been made to incorporate test circuits using the scan bus method, which is typified by the Japanese method.

However, the latter method requires an extra circuit for testing as described above in addition to the normal logic circuit. As a result, the layout becomes more complex, and the expansion of the layout capacitance distribution width causes a decrease in calculation speed and becomes an obstacle to higher integration.Furthermore, as logic circuits become larger, test circuits also become larger, resulting in test patterns. The test time has become longer and longer, resulting in an increase in test time.

[Means and operations for solving the problems] The object of the present invention is to provide a gate array type LSI having a test circuit that solves the above-mentioned problems, and FIG. 1 shows a basic configuration diagram of the present invention. In FIG. 1, Gi is a basic gate cell composed of either a NAND gate or a NOR gate, and a plurality of basic gate cells are connected according to the user's specifications to obtain a predetermined logical operation. Ali
is an access means consisting of, for example, an AND gate, and in the embodiment, the emitter of a multi-emitter transistor constituting the basic gate Gi is used.

Further, Sci is a plurality of row selection lines, which are selected during testing by the row selection means SC, and S1i is a plurality of column selection lines, which are selected during testing by the column selection means SL. Furthermore, M
i are a plurality of readout lines (monitor lines), which are connected to the output of the basic gate Gi via diode means DI. The data on these monitor lines are monitored by monitor means M.

As described above, the gate array type LSI according to the present invention has a plurality of access means Alt, row selection lines Sci, and column selection lines Sft.
, monitor line Mi, row selection means SC1 column selection means SL,
It has a test circuit constituted by monitor means M and diode means DI.

In this way, the test circuit has a test circuit that is completely separate from the user-specified logic circuit configured by connecting each basic gate Gi, and the test circuit has a test circuit that allows access to each basic gate Gi separately from the logic connection. It has a selective access means Ai capable of. The input from this access means allows the output of each basic gate to be forced to at least one logic state, ie, high (H) level or low (L) level, independently of other basic gates. The test is then performed by monitoring the output of the accessed basic gate.

〔Example〕

FIG. 2 is a block diagram of an embodiment of a gate array type LSI having a test circuit according to the present invention. In Figure 2,
Reference numeral 1 denotes a gate array type LSI chip, and 2 a plurality of basic gate cells arranged in a matrix pattern on the chip. In this embodiment, the gate cells are composed of either a NAND gate or a NOR gate. The wiring between these basic gates is such that the output of one of the basic gates is connected to the input of another basic gate, as shown by the dotted line, for example, based on the logic operation desired by the user. Furthermore, test input terminals T1 and T are provided at the inputs of each basic gate 2, respectively, and are connected to row selection lines and column selection lines, which will be described later. Reference numeral 3 denotes a row selection line which is provided in plural numbers in the row direction of the gate array, and 0 row selection line S C1+ St!, which is a plurality of column selection lines provided in the row direction 4, is provided in the column direction of the gate array.
'-' Stn is connected to the test terminal T of each basic gate, and column selection line 5IIn SRt-・Sl is connected to the test terminal T! of each basic gate. connected to. A plurality of monitor lines 5 are connected to each basic gate via a diode 6, for example, as a diode means, and output the state of the output of the basic gate to a monitor means to be described later.

7 is a row selection means for selecting one of the row selection lines S c I "' S c a; 8 is a column selection line St'+-5
I! , and 9 is a monitor means for monitoring the state of the output of each basic gate via the monitor line 5.

With such a configuration, when testing a gate array type LSI, failures in all basic gates can be detected using a fixed test pattern, regardless of the logic operation of the logic circuit. That is, there are basically four types of failure patterns, and these are: (1) Output SO failure, (2) Output S1 failure, (2) Input SO failure, and (2) Input S1 failure.

The "output SO failure" (2) is a failure that is detected when all row selection lines and column selection lines are set to L level. As is clear from the circuit configuration of the basic gate shown in FIG. 5, when an L level is input to the input, the output of the basic gate should be H level. That is, the expected output value of the basic gate is H level. However, if there is some sort of failure in one of the basic gates and the output is at the L level, the output of the basic gate is connected to the monitor line via the diode means, so the failure can be determined by the monitor means. . That is, an "output SO failure" is a failure in which an L level appears in one of the basic gates when the expected output value of the basic gate is H level -.

``Output si failure'' means that any row selection line Sci
This is a failure that is detected by setting column selection line 5jli to H level. In this case, the inputs of the selected basic gate are all at H level because the other basic gates are outputting H level, and the forced state during the test in ■ is released. The output IU1 wait value becomes L level. If the output of the basic gate concerned is at L level, it will be detected by the monitor means through the monitor line connected to it, but if the output is at H level due to some kind of failure, it will be 1 level like other basic gate outputs. , it can be determined that the basic gate is out of order.

The "input SO failure" in ■ is related to the "output S1 failure" in , at this time, one of the input terminals of the basic gate is
Even though it is originally at H level, if it is at L level, its output becomes H level. That is, since the outputs of all the basic gates other than the basic gate are at H level, all the inputs of the basic gate should be at H level. However, if the input is at the L level due to some kind of failure, the output will be at the H level, so in this case it is determined that one of the inputs is at fault.

``Input SL failure'' is a failure in which the input of one of the basic gates becomes 1 level even though it is originally at the L level.This will be explained later, but basically it applies to each basic gate. Detection is further provided by providing a set of selective access means.

If the above-described failure pattern is used for all basic gates, output SO failures, output S1 failures, and input SO failures can be easily detected. As mentioned above, such a test circuit allows each elementary gate to be tested independently of logic circuit operation.

FIG. 3 is a basic configuration diagram of another embodiment of a gate array type LSI having a test circuit according to the present invention.

In this example, in addition to the selective access means Ali shown in FIG. 1, an independent second access means A2i is provided for each basic gate. Therefore, other row selection lines S
c Bi and column selection line Sj! i' is added. This second
By providing the access means A2i, the above-mentioned "input s1 failure" can be easily detected. That is, if this basic configuration is used, "output SO failure", "output S1 failure", "input SO failure", and "input si failure"
All failure patterns can be easily detected.

FIG. 4 is a block diagram of an embodiment of the basic configuration shown in FIG. 3. In FIG. 4, row selection line Sci and column selection line 5
When Ili is set to H level, the basic gate Gin is enabled by the first access means Alt. Output of basic gate Gin at this time! The 111 wait value is at L level. On the other hand, gate G1 is connected to either input of gate Gin.
Assuming that the output of 1 is connected, the gate G + 1
At this time, the expected output value is at the H level because it is in the state of the expected output value at the time of the test in (2), and this H level is input to the gate Gin.

At this time, the second access means A 2 + of the gate Gl+
When , the output of gate G is forcibly changed to L level. Since this L level is taken into the input of the gate Gin, the change in the output of the gate Gin from the L level to the H level is determined via the monitor line. That is, if it changes from L to H, it is determined that at least the relationship between the output and input between gate C++ and gate Gin is normal. However, even if there is some failure between the output of gate G+I and the input of gate Gin and the output of gate G11 is forced to the L level, the input of the gate Gin will still remain at the H level. In this case, since the output of the gate Gin does not change, the monitoring means determines that there is a failure. That is, in this case, since the input side is still in the H level state, it is determined that "input 31 has failed."

In this way, by sequentially selecting the second access means for all the gates connected to the input of the gate Gin and forcibly changing the state of the output, the gate G
By monitoring the state of the output of in, the connection state between them can be tested, and an "input S1 failure" can be detected.

As is clear from the block diagram of FIG. 4, when detecting the above four failure patterns ■ to ■, first use the first selective access means All -AI S cn and column selection line Sj! +=Sj!
, % are used to detect the three failure patterns explained in FIGS. 1 and 2, namely, "output SO failure,""output Sl failure," and "input SO failure." After these tests are completed, the other row selection lines SCI shown in FIG.
'~Scゎ' and column selection lines sIl, '~SN,' and second selective access means A2+~ provided therein.
A2. .

By sequentially selecting , it is possible to detect the "input S1 failure" as described above.

FIG. 5 shows a specific example of a circuit incorporating a basic gate and first and second access means. In Figure 5, Gi
is a basic gate circuit using 2-input NAND. Also, A
lt is an emitter input terminal as a first access means;
A2i is a transistor serving as a second access means. As is clear, the input terminals T1 and T2 of the multi-emitter correspond to the test terminals T1 and Tt of the NAND gate of the embodiment shown in FIG. The two input terminals I N + and INg are each connected to the output of the other basic gate, and the output OUT is connected to the input of the other basic gate. The operation of this circuit is based on the row selection line Sci or Sli.
If is at L level, multi-emitter transistor Tr,
is ON, but Tr is OFF, so the output is at H level, and when the input is at H level, Trt is ON, so the output is at L level.

In such a state, when the base of the multi-collector transistor Tr of the second access means A2i is selected to be at H level and the emitter is selected to be at L level, the transistor Try is turned on, and the output becomes H level. Change to L level.

In this way, the row selection line Sci' is set to L level and the column selection line SR
By selecting 1' to be at H level, the output of the basic gate can be changed. In this case, since the second collector of the multi-transistor Tr+ is connected to an appropriate bias means, the base of the transistor Tr4, which connects the output and the monitor line, becomes L level, so the transistor Tra is cut off, and the second collector This prevents the L level switched by the access means from being detected by the monitor means.

〔Effect of the invention〕

According to the present invention, each basic gate and its input/output connections can be tested separately from the logic circuit, and the test can be performed in a predetermined pattern to detect failures.
Rapid testing is possible, and all test pattern creation is automated and easy.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block diagram of an embodiment of the basic configuration shown in FIG. 1, FIG. 3 is a block diagram showing another basic configuration of the present invention, and FIG. FIG. 4 is a block diagram of an embodiment, and FIG. 5 is a specific circuit diagram of FIG. 3. (Explanation of symbols) 1... Gate array type LSI chip 2... NAND gate 3... Row selection line 4... Column selection line 5... Monitor line 6... Diode means 7... Row selection means 8...column selection means 9...monitoring means Another basic configuration diagram of the present invention

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device in which a plurality of gate cells are arranged in a matrix, a row selection line for testing and row selection means for selecting the row selection line in the row direction of a gate cell array;
A column selection line for testing in the column direction of the gate cell array, a column selection means for selecting the column selection line, a readout line for monitoring in the row direction of the gate cell array, a monitor means for monitoring data on the readout line, and the readout line. and selective access means for connecting the gate cell and the row selection line and the column selection line, the selective access means independently of logic circuit operation. 1. A semiconductor integrated circuit device having a test circuit, characterized in that the logic circuit is tested by forcibly controlling the output of a gate cell to at least one logic state. 2. The device according to claim 1, wherein the gate cell is constituted by a NAND gate or a NOR gate. 3. A device according to claims 1 and 2, wherein said selective access means are at least two emitters of input transistors of said NAND gate or NOR gate. 4. In a semiconductor integrated circuit device in which a plurality of gate cells are arranged in a matrix, first and second test row selection lines in the row direction of the gate cell array, a row selection means for selecting the row selection lines, and a row selection means for selecting the row selection lines; Column selection means for selecting first and second test column selection lines and the column selection lines in the column direction; readout lines for monitoring in the row direction of the gate cell array; and monitoring means for monitoring data on the readout lines; switch means for connecting the readout line and the output of the gate cell; and first and second switch means for connecting the gate cell and the first and second row selection lines and the first and second column selection lines. selective access means, the first selective access means forcibly controlling the output of the gate cell to at least one logic state regardless of logic circuit operation; and the second selective access means: 1. A semiconductor integrated circuit device having a test circuit, characterized in that the logic circuit is tested by setting the output of a gate cell in a previous stage. 5. The device according to claim 4, wherein said second selective access means is constituted by a multi-collector transistor. 6. The device according to claim 4, wherein said switching means comprises a diode.