JP2555724Y2 - Digital relay - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital relay having a clock circuit.

[0002]

2. Description of the Related Art Conventionally, digital relays used as protection relays have been used to check the health of a protection system.
Alternatively, an automatic monitoring function for automatically performing a characteristic check is provided, and an automatic inspection is periodically performed, for example, once a day to several days. A digital relay having such an automatic inspection function is provided with a clock circuit for performing a constant process at a relatively long cycle. The cycle for performing the automatic inspection can be arbitrarily set within a certain range from the outside, and the CPU in the control unit of the digital relay performs a predetermined automatic inspection process at the set cycle using a clock circuit.

[0003]

However, in a conventional digital relay having such a clock circuit,
Since the start timing of the automatic inspection is based only on the clocking content of the built-in clock circuit, if the clock circuit becomes defective for some reason and stops, the automatic inspection will not be started even if the set cycle is exceeded . In addition, if the accuracy of the watch decreases for some reason, the start timing of the automatic inspection will be shifted. Moreover, the conventional constant monitoring cannot detect whether the automatic inspection is performed correctly and regularly, and cannot detect abnormal operation of the clock circuit. Even if a clerk regularly checks, a delay or advance of about several minutes a day cannot be easily confirmed. For this reason, a malfunction that would otherwise be found by the automatic inspection is not found, and there is a possibility that the reliability is reduced.

An object of the present invention is to provide a digital relay capable of detecting an abnormal operation state of a clock circuit and thereby determining, for example, whether or not an automatic check is correctly started at regular intervals. .

[0005]

SUMMARY OF THE INVENTION The present invention provides a digital relay having a clock circuit for measuring time or time, and having a processing function in accordance with the clock content of the clock circuit. a timer for <br/> meter monitoring time that counts in, means for storing temporarily read out clocking time of the clock circuit, the clock circuit by mismatch detection with counting contents of storage contents and the clock circuit of the storage unit Detects changes in the contents of timekeeping and monitors the change cycle.
Means for counting by a viewing timer;
Determines whether the count value is less than the lower limit specified in advance
And the count value of the clock monitoring timer is
Means for determining whether or not the change has occurred before reaching a count value corresponding to a predetermined upper limit value of the change cycle is provided.

[0006]

In the digital relay of the present invention, the clock monitoring timer is activated at a fixed period independently of the clock circuit, and the clock content of the clock circuit is read out and temporarily stored. by mismatch detection of the content with changes in clocking time of the clock circuit is detected, the variable
The clock cycle is counted by a clock monitoring timer. this
It is determined whether or not the count value is smaller than a predetermined lower limit value ( a lower limit value of the time required for changing the clock content of the clock circuit ) . Therefore, if the advance of the clock circuit is
If the speed increases, the count value of the watch monitoring timer
Does the clock circuit of the clock circuit change before reaching the value?
Thus, the abnormality can be detected. In addition, this invention
The digital relay of
Value corresponds to a predetermined upper limit of the change period.
By the time the count value is reached, it is determined whether the change has occurred.
Is determined. Therefore, if the advance of the clock circuit is
If the clock circuit slows down or stops, the clock circuit changes.
By the time, the count value of the watch monitoring timer
Above the value, the abnormality can be detected.
You. Reading and determination of these timekeeping contents can be one of constant monitoring item, upon detecting an abnormal operation of the clock circuit, by performing a corresponding output, it is possible to immediately notify the fault condition.

[0007]

FIG. 1 is a block diagram showing the configuration of a digital relay according to an embodiment of the present invention. In FIG.
U1 causes the entire device to function as a digital relay by executing a program written in ROM4. The clock generation circuit 2 supplies a clock signal to the CPU 1 and the timing control circuit 3. The timing control circuit 3 divides the clock signal,
An interrupt signal is given to PU1 at a fixed cycle, and a timing signal is given to each unit. The RAM 5 is used as a temporary storage for sampling data, a working area for relay operation, and a storage area for various variables to be described later. DI / O6 inputs the relay contact state of the auxiliary relay, and CPU 1 reads the contact state of the auxiliary relay via DI / O6. The DI / O7 is connected to various auxiliary relays such as an auxiliary relay that indicates that a failure has been detected during continuous monitoring, and the CPU 1 controls the auxiliary relay via the DI / O7 when detecting a stop failure state of the clock circuit. I do.
The key switch 9 is used for setting various values and modes, and the key control circuit 8 performs key input control. The display 11 displays the operation state of the entire digital relay unit including the abnormal operation state of the clock circuit. The display control circuit 10 controls the display of the display 11. The insulation converters 12 and 13 convert the signal under measurement into a voltage signal of a predetermined level in an insulated state, the filters 14 and 15 pass only a low band in order to prevent aliasing errors, and the sample and hold circuits 16 and 17 operate at every sampling period. Holds the input signal. The multiplexer 18 supplies one of the hold signals selected by the selection signal to the A / D converter 19.

The A / D converter 19 converts this into digital data. The nonvolatile memory 20 stores the set value. The clock circuit 21 includes a clock generator, a frequency dividing circuit, a clock counter, and a circuit that interfaces with a CPU bus line. The CPU 1 sets the time for the clock counter in the clock circuit 21 or reads the clock counter at a necessary time.

Next, FIG. 3 shows a partial configuration of the RAM 5 shown in FIG. In FIG. 3, C is a counter constituting a clock monitoring timer (hereinafter simply referred to as a clock monitoring timer), and C1 and C2 correspond to the time required for the count value of the clock monitoring timer C to change the clock content of the clock circuit. This is data indicating a range when determining whether or not the count value has reached the count value. If the value of the clock monitoring timer C is within the range of C1 to C2 when the clock content of the clock circuit changes,
The clock circuit is considered normal. In FIG. 3, M
Is a memory for reading and temporarily storing the clock content of the clock circuit. For example, of the contents of the time measured by the clock circuit, only the ones of "second" is read out and temporarily stored.

FIG. 4 is a diagram showing the contents of a clock counter in the clock circuit. In FIG. 4, Y1 to Y4 are four-digit data representing the year, MO2 and MO1 are two-digit data representing the month, D2 and D1 are two-digit data representing the day, H
2, H1 are two-digit data representing "hour", M2, M1 are two-digit data representing "minute", and S2, S1 are two-digit data representing "second".

FIG. 2 shows a timing chart of a program executed by the CPU shown in FIG. In FIG. 2, t is the cycle of an interrupt given from the timing control circuit 3 shown in FIG. 1, and the CPU executes the relay program for a certain time by this interrupt, and returns to the main program after the end of the relay program. If an interrupt occurs during the execution of the main program, the relay program is executed again. As described above, the relay program and the main program are alternately executed in the cycle of t. As described below,
In the relay program, the counter C provided in the RAM is incremented, and in the main program, the clock circuit is checked based on the relationship between the value of the counter C and the clock content of the clock circuit.

FIG. 5 shows the relationship between the change in the clock content of the clock circuit and the allowable error range of the count value of the clock monitoring timer.
In FIG. 5, C0 is the count value of the watch monitoring timer,
C1 and C2 are a lower limit value and an upper limit value indicating a permissible error range of the count value with C0 as a center, which is a center value that is counted during a time required for the clock content of the clock circuit to change.

Next, FIGS. 6 and 7 show the processing procedure of the CPU as a flowchart.

FIG. 6 shows a processing procedure of the relay program. When an interrupt is issued from the timing control circuit 3,
Execute this relay program. First, the counter C
Is incremented (n1). Subsequently, the measurement data is read, and a predetermined relay operation is performed (n2 → n
3). The result of the relay operation is compared with a predetermined set value (n4). As a result, if the condition for operating the relay is satisfied, contact output is performed (n4 → n5). In other cases, the contact output is not performed (n4 → RETURN).

FIG. 7 shows the processing procedure of the main program. First, the clock contents of the clock circuit are temporarily stored in the memory (n10). Specifically, the value of the ones digit S1 of the "second" of the time measured by the clock circuit shown in FIG. 4 is written to the memory M in the RAM shown in FIG. Subsequently, the clock monitoring timer C is cleared (n11). Thereafter, it is determined whether or not the clock content of the clock circuit matches the memory (n12). More specifically, a comparison is made between the ones of "seconds" of the clock content of the clock circuit and the memory M. If they match, it is determined whether or not the monitoring timer C is equal to or less than the upper limit value C2 (see FIG. 5) of the count value of the monitoring timer (n13). If C ≦ C2, other constant monitoring (A / D conversion accuracy check, settling value check, watchdog timer reset, DI / O check, trip circuit monitoring, power supply monitoring, etc.) is performed (n14). Thereafter, the processing from step n12 onward is sequentially repeated (n14 → n12...). As the time elapses thereafter, the content of the clock of the clock circuit is sequentially updated, and the value of the clock monitoring timer C is sequentially incremented by the interrupt processing of the relay program shown in FIG. If the clock content of the clock circuit is different from the memory content, that is, if the clock content of the clock circuit changes, it is determined whether the clock monitoring timer C is equal to or more than the lower limit value C1 of the count value. Is performed (n15). C
If ≧ C1, that is, if the count value of the watch monitoring timer C is within the allowable error range, the watch monitoring timer C
Is cleared, and the one's place of the clock content “second” of the clock circuit is written into the memory again (n16 → n17). If the count value C of the clock monitoring timer exceeds the upper limit value C2 and no change in the clock content of the clock circuit is detected, it is considered that the clock circuit is in a stopped state or a faulty state in which the clock circuit is abnormally delayed. The abnormality notification and the contact output are performed to activate the auxiliary relay for alarm (n12 → n13 → n18).

If a change in the clock content of the clock circuit is detected even though the count value C of the clock monitoring timer is less than the lower limit value C1, it is considered that the clock circuit is in a defective state in which the clock circuit abnormally advances. , An abnormality notification and a contact output are performed to activate the auxiliary relay for alarm (n12 →
n15 → n18).

In the embodiment, only the ones of "second" of the clock content of the clock circuit is targeted for detecting a change in the clock content. However, in the clock circuit shown in FIG. May be set as targets, or a monitoring timer may be provided for each of the digits, and each monitoring timer may determine whether or not the timekeeping content changes within the allowable error range. You may make it. As a result, it is possible to detect an abnormal change due to a so-called bit drop or the like of the counter indicating the clock content of the clock circuit.

[0018]

Effects of the invention] According to the invention, when the clock circuit itself was abnormal operation is a failure, which can be found more quickly to constantly monitor, moreover, for example, a few minutes of delay or proceed to 1 day Automatically lowers the degree of accuracy to the extent that
It is possible to detect in. Therefore, such as automatic inspection ,
The process corresponding to the clocking time of the clock circuit is not carried out state and, the deviation of the start timing can prevent, causing malfunction encountered with the system fault in a state in which unit fails, A highly reliable digital relay without such problems can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital relay according to an embodiment of the present invention.

FIG. 2 is a diagram showing operation timings of a CPU.

FIG. 3 is a partial configuration diagram of a RAM.

FIG. 4 is a diagram showing the contents of time measurement of a clock circuit.

FIG. 5 is a diagram illustrating a relationship between a change in the clock content of a clock circuit and a count value of a clock monitoring timer.

FIG. 6 is a flowchart illustrating a processing procedure of a CPU corresponding to a relay program executed at the time of interruption.

FIG. 7 is a flowchart illustrating a processing procedure of a CPU corresponding to a main program.

Claims (1)

(57) [Scope of request for utility model registration] [Claim 1, further comprising a clock circuit for counting a time or time, the digital relay having a processing function in accordance with the clocking time of the clock circuit, Thailand timepiece monitor that counts at a constant period independent of the clock circuit and Ma, means for storing temporarily read out clocking time of the clock circuit,
Upon detecting a change in the timekeeping contents of the clock circuit by mismatch detection with counting contents of storage contents and the clock circuit of the storage unit
In both cases, the change cycle is monitored by the watch monitoring timer.
The means for counting and the count value by the means are specified in advance.
Means for determining whether it is less than the lower limit, and the count value of the clock monitoring timer is
Means for determining whether or not the change has occurred before reaching a count value corresponding to a predetermined upper limit value .