JP2555708Y2 - Digital relay - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital relay device comprising a main relay having a clock circuit and a fail-safe relay.

[0002]

2. Description of the Related Art Generally, a method of multiplexing a plurality of relays is employed as one of methods for improving the reliability of a protective relay device. For example, a main relay that performs the main part of the responsibilities of the relay device is combined with a fail-safe relay that prevents the main relay from malfunctioning and malfunctioning.

In general, a digital relay used as a protection relay has been provided with an automatic monitoring function for automatically checking the health of a protection system or confirming characteristics thereof, for example, for one to several days. Once, an automatic inspection is performed periodically. A clock circuit is provided to perform such a constant process in a relatively long cycle. The cycle of automatic inspection can be set arbitrarily from the outside within a certain range.
Executes a predetermined automatic inspection process at a set cycle with reference to a clock circuit.

[0004] In the relay device in which the main relay and the fail-safe relay are combined, it is determined whether or not the main relay should start an automatic inspection process from a built-in clock circuit.
At the start timing, an inspection start signal is transmitted to the fail safe relay side, and an automatic inspection is performed by itself. On the other hand, the fail-safe relay starts its own automatic inspection processing when receiving the inspection start signal from the main relay.

[0005]

However, in the conventional digital relay device provided with such a clock circuit, the starting timing of the automatic inspection is only performed based on the clocking content of the built-in clock circuit. If the clock circuit becomes defective due to any cause and stops, the automatic inspection will not be started even if the set cycle is exceeded. In addition, the conventional constant monitoring cannot detect whether or not the automatic inspection is performed regularly, and cannot detect a failure of the clock circuit. Therefore, a malfunction that would otherwise be found by the automatic inspection is not found, and the reliability is greatly reduced.

An object of the present invention is to enable a digital relay device including a main relay and a fail-safe relay to detect a faulty stop state of a clock circuit on the main relay side. It is an object of the present invention to provide a digital relay device capable of determining whether or not the relay is activated.

[0007]

Means for Solving the Problems] Bei this invention is a clock circuit for counting a time or time when the the automatic inspection means respectively
In a digital relay device consisting of a main relay and a fail-safe relay, the main relay
At a predetermined cycle based on the clock content of the in-relay clock circuit
Activate the main relay automatic inspection means and
Means for sending an inspection start signal to the Ilsafe relay
And the fail-safe relay is
Inspection start signal based on the contents of the clock circuit of Leh
Means for judging whether or not the reception cycle of the data exceeds a predetermined cycle .

[0008]

According to the digital relay device of the present invention, means for receiving an inspection start signal generated at regular intervals from the main relay, and means for determining whether or not the generation interval of the inspection start signal exceeds a predetermined cycle. Are provided on the fail-safe relay side. Therefore, if the clock circuit in the main relay is normal, an inspection start signal is given to the fail-safe relay side at predetermined fixed time intervals, and the fail-safe relay has a signal receiving interval within a predetermined period. Is determined. If the clock circuit on the main relay side is in a stop failure state for any reason, the fail-safe relay detects a state in which the inspection start signal is not received even after a predetermined time from the main relay. This determination is regarded as one of the items to be constantly monitored on the fail-safe relay side, and when a stop failure of the clock circuit on the main relay side is detected, a corresponding output is performed, whereby the failure state can be immediately notified.

[0009]

FIG. 1 is a block diagram showing a configuration of a digital relay device according to an embodiment of the present invention. In FIG. 1, 1
00 is a main relay, 101 is a fail-safe relay, and in this example, hardware having the same configuration is used. Taking the main relay 100 as an example, the CPU 10
By executing a program written in the OM 15 in advance, it functions as a main relay. The multiplexer 11 selects one of the signals to be measured, which is converted into a DC voltage signal of a predetermined level, sampled and held, and supplies the selected signal to the A / D converter 12. A / D
Converter 12 converts an input signal into digital data. The nonvolatile memory 13 stores various set values including an automatic inspection cycle. The clock circuit 14 includes a clock generator, a frequency divider, a clock counter, and a circuit that interfaces with a bus line of the CPU. RAM16
Is used as a temporary storage area for sampling data, a working area at the time of relay operation, and the like. DI / O1
7 is connected to the auxiliary relays 11 _MX and MX, the contact return signals of these auxiliary relays, and further to the fail-safe relay DI / O 27. Auxiliary relay 1
1 _MX is a test relay that turns on at the time of automatic inspection to open a trip route, and an auxiliary relay MX is a relay that turns on at the time of protection relay and closes a trip circuit.

On the other hand, the fail-safe relay 101 has the same configuration as the main relay 100 in this example,
U20 is connected to D of main relay 100 via DI / O27.
The inspection start signal output from the I / O 17 is received. The DI / O 27 is connected to two auxiliary relays 11 _FX and FX and contact return signals of these auxiliary relays. The auxiliary relay 11 _FX is turned on at the time of inspection to open the trip route, and the auxiliary relay FX is turned on at the time of protection relay to close the trip route.

Next, the processing procedure of the main relay 100 shown in FIG. 1 will be described with reference to the flowchart of FIG. First, the contents (current time) of the clock circuit are read, and it is determined whether or not it is time to start automatic inspection (for example, 9:00) (n1 → n2). When it is time to start the automatic inspection, first, an inspection start signal is transmitted to the fail-safe relay (n3). Subsequently, the auxiliary relay _11MX is turned on to open the trip route (n4). And 11 _MX
Is read, and it is determined whether or not the auxiliary relay _11MX is operating correctly (n5 → n6). 1
1 If the _MX contact is normally opened,
X is turned on (n7). Subsequently, a contact return signal of the MX relay is read to determine whether the relay is operating correctly (n8 → n9). If the MX contact is normally closed, then the auxiliary relay MX is turned off again and it is determined whether or not it has been operated correctly (n10 → n11 → n12). If MX contacts open normally, then turns off the auxiliary relay 11 _MX, determines whether 11 _MX contact is normally closed (n1
3 → n14 → n15). If 11 _MX contacts normally closed, it is assumed trip circuit is normal is performed followed by constant monitoring (n16). Steps n6 and n6
If it is determined to be abnormal in the determination of 9, n12 and n15,
In steps n17, n18, n19 and n20, the contents of the abnormality are stored and output to the outside (DI / O1).
Reference numeral 7 denotes an auxiliary relay (not shown) for reporting an abnormal state.
Is connected). When it is not time to start the automatic inspection, only monitoring is always performed (n2 → n16).

Next, the processing procedure of the fail-safe relay will be described with reference to the flowchart of FIG. First, after reading the contents of the clock circuit, it is determined whether an inspection start signal is transmitted from the main relay (n21 → n2).
2). If the inspection start signal is received from the main relay, the time at that time is stored (n23). After that, automatic inspection and constant monitoring are performed by the processing of steps n24 to n36. The processing contents of the automatic inspection and the constant monitoring are the same as those described with reference to FIG. 2 for the main relay, and the fail-safe relay automatically inspects the auxiliary relays 11 _FX and FX. When the inspection start signal has not been transmitted from the main relay side, the elapsed time since the previous inspection start signal was transmitted is obtained (n22 → n).
41). It is determined whether or not the elapsed time has exceeded a maximum cycle (for example, 10 days) that can be determined as an automatic inspection cycle. The state is stored and output (n42 → n43).

[0013]

According to the present invention, when the main relay stops due to failure in the clock circuit itself, which is a reference for determining the start timing of the automatic inspection, this can be quickly detected on the fail-safe relay side. In addition, it is possible to prevent the automatic inspection from becoming inoperative. As a result, it is possible to obtain a highly reliable digital relay device that does not encounter a system failure and cause a malfunction when the device is still in failure.

Although FIGS. 2 and 3 show only the procedure of automatic inspection and constant monitoring of the main relay and the fail-safe relay, the CPU fetches the measurement signal through short-period interrupt processing and performs the relay operation. Then, the auxiliary relay MX (FX on the fail-safe relay side) is turned on at a required point in time by comparison with the set value.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital relay device according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing procedure of a CPU on a main relay side.

FIG. 3 is a flowchart illustrating a processing procedure of a CPU on a fail safe relay side.

[Explanation of symbols]

 100-Main relay 101-Fail safe relay

Claims (1)

(57) [Scope of request for utility model registration] 1. A automatic and clock circuit for counting a time time or time
In a digital relay device comprising a main relay and a fail-safe relay each having an inspection means , the main relay is a clock relay of a clock circuit of the main relay.
Trigger the automatic inspection of the main relay at predetermined intervals based on the
And initiate a check for the fail-safe relay.
Means for transmitting a motion signal , and the fail-safe relay
The receiving cycle of the inspection start signal is determined based on the timing content of the measuring circuit.
A digital relay device comprising: means for determining whether a period exceeds a predetermined period .