JP2554104B2 - Display controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device, and more particularly, to a display device using a display element having bistability against an electric field such as a ferroelectric liquid crystal element. The present invention relates to a display control device suitable for application.

[Related Art] Conventionally, in a display device, as a liquid crystal display element using a liquid crystal compound, a scanning electrode group and a signal electrode group are configured in a matrix, and a liquid crystal compound is filled between the electrodes to form a large number of pixels. There is known a device which forms and displays image information.

As a driving method of this display element, a voltage signal is sequentially and periodically applied to the scanning electrode group, and a predetermined information signal is applied to the signal electrode group in parallel in synchronization with the signal of the scanning electrode group. Time division drive is used. Such a display element and its driving method have a problem that it is difficult to increase the pixel density or enlarge the screen.

That is, the response speed of the conventional liquid crystal is relatively high,
Moreover, because of its low power consumption, almost all TN (twisted nematic) type liquid crystal is practically used as a display element, and this type of liquid crystal has no electric field as shown in FIG. Structure in which nematic liquid crystal molecules with positive dielectric anisotropy are twisted in the thickness direction of the liquid crystal layer (helical structure)
Is formed, and the molecules of the liquid crystal are twisted (twisted) between the electrodes in each layer in parallel with each other and the electrode surface.
Forming a structure. On the other hand, as shown in FIG. 50 (B), when an electric field is applied, nematic liquid crystal molecules having positive dielectric anisotropy are aligned in the electric field direction, and as a result, optical modulation can occur. When such a liquid crystal is used to form a display element with a matrix electrode structure, in a region (selection point) in which both the scanning electrode and the signal electrode are selected, the liquid crystal molecules are equal to or more than a threshold value required to be aligned perpendicularly to the electrode surface. Voltage is applied, the voltage is not applied to the area (non-selection point) where neither the scanning electrode nor the signal electrode is selected, so that the liquid crystal molecules maintain a stable twisted array parallel to the electrode surface. ing. By disposing linear polarizers having a crossed Nicol relationship above and below such a liquid crystal cell, light does not pass at the selected point, and light passes at the non-selected point due to the twisted structure and optical rotation of the liquid crystal. , And can be used as an image device.

However, when the matrix electrode structure is configured, a limited area is also set in a region where the scanning electrode is selected and the signal electrode is not selected, or a region where the scanning electrode is not selected and the signal electrode is selected (so-called “half-selected point”). An electric field is applied. If the difference between the voltage applied to the selected point and the voltage applied to the half-selected point is sufficiently large and the voltage threshold required for aligning the liquid crystal molecules perpendicular to the electrode surface is set to an intermediate voltage value, the display element Works normally.

However, in this method, when the number of scanning lines (N) is increased, the time during which an effective electric field is applied to one selected point during scanning of the entire screen (one frame) (duty)
Ratio) will decrease at a rate of 1 / N. For this reason, the voltage difference as an effective value between the selected point and the non-selected point when the repetitive scanning is performed becomes smaller as the number of scanning lines increases, and as a result, the image contrast decreases and the crosstalk decreases. Is an unavoidable problem.

Such a phenomenon is caused by a liquid crystal used in a conventional display element that does not have a bistable state (a stable state in which liquid crystal molecules are aligned horizontally with respect to an electrode surface, and an electric field is effectively applied). Vertically aligned only while being driven) (that is, repetitive scanning) using the temporal accumulation effect
It is an inherently unavoidable problem that sometimes occurs. In order to improve such a problem, a voltage averaging method, a two-frequency driving method, a multiple matrix method, and the like have already been proposed.
Either method is insufficient, and the screen size and density of the display element have reached a plateau because the number of scanning lines cannot be sufficiently increased.

On the other hand, as a method for solving the above-described problem, for example, Japanese Patent Application Laid-Open No. 59-193426 or
In Japanese Patent Application Laid-Open No. 60-33535, the present applicant proposes a method of driving a liquid crystal having a bistable state with respect to an electric field. Liquid crystals that can be used in the above driving method include
Chiral smectic liquid crystals having ferroelectricity are the most preferable, and among them, chiral smectic C phase (SmC
^* ) Or H-phase (SmH ^* ) liquid crystals are suitable.

As shown in Fig. 51, SmC ^* has a layer structure in which liquid crystal molecules are parallel to each other, and the long axis direction of the molecules has an inclination with respect to the layer. These liquid crystal molecules have different tilting directions for each layer, and as a result form a helical structure.

As shown in FIG. 52, in SmH ^* , molecules have a layered structure in parallel, the long axis direction of the molecule is inclined with respect to the layer, and a hexagonal packing structure is formed in a plane perpendicular to the long axis of the molecule.

SmC ^* and SmH ^* have a helical structure composed of liquid crystal molecules, and their schematic diagram is shown in FIG.

In the figure, e3 is the liquid crystal component, e4 is the electric dipole moment, and e5 is the layer boundary surface. Here, each liquid crystal molecule e3 has a dipole moment in a direction orthogonal to its long axis direction, and moves while maintaining a constant angle θ with the Z axis orthogonal to the layer environment surface e5 to form a spiral structure. are doing. This figure shows a state where no voltage is applied, and if a voltage equal to or more than a certain threshold is applied in the X-axis direction, the liquid crystal molecule e3 causes the electric dipole moment e4 to be parallel to the X-axis. Orientation.

The SmC ^* or SmH ^* phase is one of the phase transitions depending on the temperature.
When these liquid crystal compounds are used, it is preferable to select an element according to a temperature range in which the display device is used, since these liquid crystal compounds are realized as one phase.

FIG. 54 shows the above-mentioned ferroelectric liquid crystal (hereinafter referred to as FLC: Ferroele).
ctric Liquid Crystal). e1 and e1 ′ are substrates (glass plates) coated with a transparent electrode such as In ₂ O ₂ , SnO ₂ or ITO (Indium-Tin Oxide), between which the liquid crystal molecular layer e2 is perpendicular to the glass surface The liquid crystal of the SmC ^* phase, which is oriented likewise, is sealed. The liquid crystal molecule e3 shown by a thick line has a dipole moment e4 in a direction orthogonal to the molecule e3. substrate
When a voltage above a certain threshold is applied between the electrodes on e1 and e1 ', the helical structure of the liquid crystal molecule e3 is unraveled, and the dipole moment e4 is biased toward the electric field. You can The liquid crystal molecules e3 have an elongated shape, exhibit refractive index anisotropy in the major axis direction and the minor axis direction, and therefore, for example, polarized light arranged in a cross-Nicol positional relationship with the orientation direction above and below the glass surface. It is easily understood that if the element is placed, it becomes a liquid crystal optical modulation element whose optical characteristics change according to the voltage application polarity.

Furthermore, when the thickness of the liquid crystal cell is made sufficiently thin (for example, 1 μm), the helical structure of the liquid crystal molecules is unwound even when no electric field is applied as shown in FIG. 55, and its dipole moment P or P ′ Takes either the upward or downward direction in the figure. In such a cell,
As shown in FIG. 55, electric fields E of different polarities and above a certain threshold value
Alternatively, when E 'is applied for a predetermined time, the dipole moment changes direction upward or downward according to the electric field E or the electric field vector of E', and accordingly, the liquid crystal molecules are in the first stable state f3 or in the second state. It is oriented to one of the stable states f3 '.

There are two advantages of using such an FLC as an optical modulation element. First, the response speed is extremely high (1
Second, the alignment of the liquid crystal molecules has a bistable state.

The second point will be explained with reference to FIG. 55, for example.
Is applied, the liquid crystal molecules e3 are oriented to the first stable state f3, which is stable even when the electric field is cut off. When an electric field E 'in the opposite direction is applied, the liquid crystal molecules e3 are oriented to the second stable state f3' and change the direction of the molecules, but remain in this state even after the electric field is cut off. That is, the liquid crystal molecules e3 have a memory property. Further, as long as the applied electric field E does not exceed a certain threshold value, the respective alignment states are maintained.

In order to effectively realize such high response speed and memory, a method that is as thin as possible as a cell is preferable.
Generally, 0.5 μm to 20 μm, particularly 1 μm to 5 μm is suitable.

Next, an outline of the FLC driving method will be described with reference to FIGS. 47 to 49.

FIG. 56 is a schematic view of a cell having a matrix electrode structure in which an FLC compound (not shown) is sandwiched in the middle. com is a scan electrode group, and seg is a signal electrode group. First, the case where the scan electrode com1 is selected will be described.

FIGS. 57 (A) and 57 (B) are examples of scanning signals, and an electric signal applied to each selected scanning electrode com1 and other scanning electrodes (unselected scanning electrodes) com2, The electric signals applied to com3, com4 ... are shown. FIG. 57 (C) and FIG. 57 (D) are examples of information signals, and the selected signal electrodes seg1, seg3,
It shows an electrical signal applied to seg5 and unselected signal electrodes seg2 and seg4.

57 and 58, the horizontal axis represents time and the vertical axis represents voltage. For example, when displaying a moving image, the scanning electrode group com is sequentially and periodically selected. Now, a threshold voltage for giving a first stable state of a liquid crystal cell having bistability with respect to a predetermined voltage application time Δt ₁ or Δt ₂ is −V _th1, and a threshold voltage for giving a second stable state. If the voltage is + V _th2 , the selected scan electrode com
As shown in FIG. 57 (A), the electrode signal given to (com1) is 2 V at phase (time) Δt ₁ and 2 V at phase (time) Δt ₂
Then, the alternating voltage is −2V. When an electrical signal having a plurality of phase intervals with different voltages is applied to the selected scan electrodes, an optical "dark" (black) is generated.
Alternatively, a state change between the first and second stable states of the liquid crystal corresponding to the "bright" (white) state can be rapidly caused.

On the other hand, the other scan electrodes com2 to com5 ... Have the central potential of the cell applied voltage, that is, the reference potential (for example, the ground state), as shown in FIG. 57 (B). Also, the electric signals given to the selected signal electrodes seg1, seg3, seg5 are:
It is V as shown in FIG. 57 (C), and the electric signal applied to the unselected signal electrodes seg2, seg4 is -V as shown in FIG. 57 (D). In the above, each voltage value is set to a desired value satisfying the following relationship.

V <V _th2 <3V −3V <−V _th1 <−V Among the respective pixels when such an electric signal is given, for example, the voltage waveforms applied to the pixels A and B in FIG. Shown in FIGS. 58 (A) and (B). That is, as is clear from FIGS. 58 (A) and 58 (B), in the pixel A on the selected scanning line, the threshold value is set at the phase Δt ₂ .
A voltage of 3 V exceeding V _th2 is applied. Further, the voltage -3V exceeding the threshold value -V _th1 is applied in the phase Delta] t ₁ the pixel B present in the same scanning line. Therefore, on the selected scanning electrode line, depending on whether or not the signal electrode is selected, the liquid crystal molecules are aligned in the first stable state when selected and the second stable state when not selected. Orient to a state.

On the other hand, as shown in FIGS. 58 (C) and 58 (D), the voltage applied to all the pixels is V or -V on the unselected scanning lines, and neither of them exceeds the threshold voltage. Therefore, the liquid crystal molecules in each pixel other than on the selected scanning line maintain the alignment corresponding to the signal state at the time of previous scanning without changing the alignment state. That is, when a scanning electrode is selected, a signal for one line is written, and the signal state can be held from the end of one frame to the next selection. Therefore, even if the number of scanning electrodes increases, the actual selection time / line does not change, and no reduction in contrast occurs.

As described above, in order to solve the problems of the display device using the conventional TN-type liquid crystal, the device has bistability with respect to an electric field, and further has a stable state even when no electric field is applied. FLC that realizes a display element that can be maintained
Has been made, but this FL
There are various characteristics to be considered regarding specific drive control of a display element using C.

[Problems to be Solved by the Invention] An object of the present invention is to provide an optical modulator (FLC) such as a ferroelectric liquid crystal element having bistability against such an electric field.
An object of the present invention is to provide a display control device capable of performing appropriate drive control while effectively utilizing the characteristics of the display device when using the elements.

[Means for Solving the Problems] In order to achieve such an object, the present invention has a scanning electrode group and a signal electrode group which are arranged in a matrix to form a pixel group, and the scanning electrode group is provided. A display control device for driving a display device in which a display element is disposed between the signal electrode group and the signal electrode group, the driving device having driving means for respectively driving the scanning electrode group and the signal electrode group, and outputting from the driving means. A scan electrode driving signal for driving the scan electrode group in one line scanning period has at least two phases, and a first phase of the two phases has a plurality of pulse signals of different polarities; It is characterized by having a plurality of pulse signals having a polarity which is in an inversion relation with the polarity of the signal of the phase.

[Operation] According to the above configuration, since the scan electrode drive signal has two phases which are in an inverse relationship to each other during the one line scan period for driving the scan electrodes, the polarity in the one line scan period is considered. The total sum of the driving energies can be made substantially zero. At the same time, since the scan electrode drive signal has a plurality of pulses having different polarities in each of the two phases, in combination with the signal electrode drive signal,
For example, writing after once erasing the display in a predetermined area (line writing in the block access mode) and erasing and writing the display information up to that time along with the writing (line writing in the line access mode) are possible. A writing (display) mode is possible.

[Examples] Hereinafter, the present invention will be described in detail with reference to the drawings.

 The description will be given in the following procedure.

(1) Device overview (2) Display configuration (3) Display control overview (3.1) Display frame (3.2) Display element drive waveform (3.3) Display element drive voltage (3.4) Temperature compensation (3.5) ) Display drive system (3.6) Clearing the display screen (4) Configuration of each part of the display control device (4.1) Main symbols (4.2) Control part (4.3) Memory space (4.4) Data output part, (4.5) A / D converter (4.6) D / A converter and power controller (4.7) Frame driver (4.8) Display driver (4.8.1) Segment side driver (4.8.2) Common side driver (4.9) Drive waveform (5) Display control (5.1) Outline of control procedure (5.2) Details of control size (5.2.1) Power on (initial) (5.2.2) Block access (5.2.3) Line access (5.2.4) Power off (6) Effect of Example (6.1) Effect of frame formation (6.2) Effect of temperature compensation (6.3) Image data input (6.4) Effect of arranging display drive section (6.5) Effect of screen clearing (6.6) Effect of power supply controller allocation (6.7) Effect of waveform change and inversion drive (7) Modification (7.1) Frame configuration (7.2) Temperature compensation timing and partial rewriting (7.3) 1 horizontal scanning period and drive voltage value (7.4) Waveform setting (7.5) Block access or line access selection (7.6) Number of scanning lines ( 7.7) Erasing the effective display area (7.8) Position of temperature sensor (7.9) Display, display controller and word processor (1) Outline of device FIG. 1 shows an embodiment of the present invention. Therefore, reference numeral 1 is a word processor main body as a host device which serves as a supply source of image data related to display to the display according to the present example. 50
Is a display control device according to the present example, and performs drive control of a display device with respect to display data and the like supplied from the word processor main body 1 in accordance with various conditions described later. Reference numeral 100 denotes a display configured using FLC. Reference numerals 200 and 300 denote segment-side drive units that drive signal electrodes and common-side drive units that drive scan electrodes, respectively, provided on the display 100 in accordance with drive data and the like supplied from the display control device main body 50 side. is there. Reference numeral 400 denotes a temperature sensor provided at an appropriate position on the display 100, for example, at a site exhibiting an average temperature.

In the display unit 100, 102 is a display screen, 104 is a display screen 1
Reference numeral 02 denotes an effective display area, and reference numeral 106 denotes a frame provided outside the effective display area 104 on the display screen 102. In this example, the frame portion 106
Are arranged on the display 100, and are driven to form a frame on the screen 102.

In the display control device 50, reference numeral 500 denotes a control unit which will be described later with reference to FIG.
Controls transmission and reception of various data to and from. Reference numeral 600 denotes a data output unit described later with reference to FIG. 16, which controls the display data supplied from the word processor main body 1.
Driving of the display driving units 200, 300, etc. according to the setting data from 0 and the like, activation of the control unit 500 for data setting and the like are performed. 700
Denotes a frame drive unit, which forms a frame unit 106 on the display screen 102 based on output data from the data output unit 600.

Reference numeral 800 denotes a power controller, which appropriately converts a voltage signal from the word processor 1 under the control of the control unit 500 to generate a voltage to be applied to the electrodes by the display driving units 200 and 300. Reference numeral 900 denotes a D / A conversion unit arranged between the control unit 500 and the power supply controller 800. The D / A conversion unit 900 converts the digital amount setting data of the control unit 500 into analog amount data and supplies it to the power supply controller 800. 950 is a temperature sensor 400 and a control unit 5
It is an A / D conversion unit arranged between 00 and 00, and converts temperature data of the analog amount detected by the display device 100 into a digital amount and supplies it to the control unit.

The word processor main body 1 has a function as a host device serving as a supply source of display data to the display device 100 or the display control device 50. In any case, the following data can be exchanged. That is, first, as data to be supplied to the display control device 50, D: a signal including image data, address data for designating a display position of data, and a horizontal synchronization signal.

The address data for designating the display address of the image data (corresponding to the display device on the effective display area 104) is, for example, the address data as it is if the host device has a VBAM corresponding to the effective display area 104. It can also be output. In this example, the word processor main body 1 superimposes this signal on the horizontal synchronizing signal or the blanking signal and supplies it to the data output unit 600.

CLK: Transfer clock for image data PD0 to PD3.

It is supplied to the data output unit 600.

PDOWN: A signal notifying that the system will be powered off.

It is supplied to the control unit 500 as a non-maskable interrupt (NMI).

And

In addition, as data to be supplied to the word processor main body 1 by the display control device 50, P ON / OFF: Notify that the display control device 50 has completed start-up and turn-off when the system power is turned on and off, respectively. Status to do.

The control unit 500 outputs.

Light: A signal for instructing on / off of the light source FL combined with the display device 100.

The control unit 500 outputs.

Busy: a synchronization signal that causes the word processor 1 to wait for the transfer of the signal D or the like in order for the display control device 50 to perform various settings during the initial operation or the display operation. That is, in this example, it is assumed that the word processor main unit 1 can receive the Busy signal.

The control unit 50 supplies the data via the data output unit 600.

(2) Configuration of Display FIG. 2 and FIG. 3 are an exploded perspective view and a cross-sectional view, respectively, showing one configuration example of the display 100 configured by using the FLC. In these figures, reference numerals 110 and 120 denote glass plates disposed at an upper portion and a lower portion, respectively, and provided with polarizers disposed so as to be in a crossed Nicols with respect to the orientation direction of the FLC element. Reference numeral 122 denotes a wiring portion provided on the lower glass substrate 120, and is composed of a transparent electrode 124 made of, for example, ITO and an insulating film 126. Reference numeral 128 denotes a metal layer to be added on the transparent electrode 124 when it is necessary to reduce the resistance of the electrode, and may not be added when the display is small. Reference numeral 112 denotes a wiring portion provided on the upper glass substrate 110, and the same transparent electrodes 114 as the respective portions 124 and 126 in the wiring portion 122 of the lower glass substrate 120.
And an insulating film 116 and the like.

The wiring directions of the wiring portions 112 and 122 are directions orthogonal to each other. For example, if the effective display area 104 is A5 size and its long side is used as the horizontal scanning direction and the resolution is 400 × 800 dots, 400 wirings are required in the wiring section corresponding to the effective display area. Alternatively, a group of 800 transparent electrodes is provided. In this example, a group of 400 transparent electrodes 114 is provided in the upper wiring portion 112 and a group of 800 transparent electrodes 124 is provided in the lower wiring portion 122 with the horizontal scanning direction as the common side. Further, a portion corresponding to the outside of the effective display area 104 inside the display screen 102 has transparent electrodes 150 for displaying a frame.
A group of 151 is provided in the same or different shape as the transparent electrodes 124 and 114 for data display.

Reference numeral 130 denotes an enclosing portion of the FLC 132, and a pair of alignment films 136 for aligning the axis of the FLC element (Z axis in FIG. 44), and the FLC element is aligned with the axis as shown in FIG. 55. A spacer 134 for defining the distance between the alignment films 136 so as to take the first or second stable state. 140 is a sealing material such as epoxy for sealing the FLC 132, 142 is a filling port for filling the FLC 132 in the enclosing portion 130, and 144 is a sealing member for sealing the filling port 142 after the filling.

210 and 310 are segment side drive units 200, respectively.
And the common drive element as a component of the common-side drive unit 300. In this example, the integrated drive circuit drives 80 transparent electrodes, and 10 and 5 integrated circuits, respectively. Arrange. Reference numerals 280 and 380 denote a substrate on which the segment drive element 210 is mounted, and a substrate on which the common drive element 310 is mounted, respectively. 282 and 382 are substrates 280 and 3, respectively.
A flexible cable connected to 80, 299 is a connector that connects the flexible cables 282 and 382 and is connected to the display controller 50 shown in the first figure.

115 and 125 are extraction electrodes formed continuously with the transparent electrodes 114 and 124, respectively, and drive element via the film-like conductive members 384 and 284, respectively.
Connect to 310 and 210.

In this example, display is performed by irradiating light from the light source FL disposed below the lower glass substrate 120 and driving the FLC element to the first or second stable state.

(3) Outline of display control When the display device as shown in FIGS. 2 and 3 is applied, there are the following various problems with respect to the characteristics of the FLC element. Focusing attention, an appropriate configuration of the display device 100 using the FLC element and an appropriate drive control thereof are realized.

(3.1) Display Frame When the display 100 is configured as shown in FIGS. 2 and 3, a range in which the group of the transparent electrodes 114 on the common side and the group of the transparent electrodes 124 on the segment side are arranged in a matrix. The area on the display screen 102 corresponding to the area is actually an area in which image data can be displayed, that is, the effective display area 104, but outside the common arrangement area and the segment side transparent electrode group in a matrix arrangement range. Display screen 10 including the area corresponding to at least a portion of the inside of the sealing material 140
A value of 2 is desirable in order to make the effective display area 104 completely visible.

However, simply disposing the transparent electrode group on the common side and the segment side only passes through the electrode group on either side in such a part, and therefore the FLC of that part is not suitable for displaying image data. Regardless, it will be floating. That is, in such a state, the FL of that part
Since C can be in the first or second stable state, a light transmitting area (white) and a non-transmitting area (black) are mixed in an area on the display screen 102 corresponding to that part, As a result, not only does the appearance of the display be impaired, but also the effective display area 104
May be difficult to specify, or an illusion may occur to the operator.

Therefore, in this example, such an effective display area 104
Transparent electrodes (hereinafter, referred to as frame transparent electrodes) 151 and 150 intersecting with the common-side or segment-side transparent electrodes, and by appropriately driving these, the frame portion 106 is formed. I do. As this frame transparent electrode, for example, 1 side on both sides of the arrangement range of the common side transparent electrode 114 on the upper glass substrate 110 and both sides of the segment side transparent electrode 124 on the lower glass substrate 120, respectively.
Six electrodes 151 and 150 are arranged. In FIG. 2, only one of the glass substrates 120 and 110 is shown on both sides for simplification.

(3.2) Driving Waveform of Display Element One of the features of the FLC display element is that it has a memory property. However, it relates to the driving waveform caused by the application time dependency of the threshold described later with reference to FIG. The problems and their solutions are described below.

In FIG. 56, scan electrodes com1 to com5 ... And signal electrodes se
Of the pixels formed at the intersections of g1 to seg5..., the shaded pixels correspond to the “bright” state (white), and the pixels indicated by the white background correspond to the “dark” state (black). These states are described above
This corresponds to a first stable state and a second stable state of the FLC. Focusing now on the display on the signal electrode seg1 in FIG. 56, the pixel A corresponding to the scan electrode com1 is in the "bright" state, and the other pixels B are all in the "dark" state.

FIG. 5A shows an example of the drive waveform in this case,
The scanning signal, the information signal given to the signal electrode seg1, and the voltage applied to the pixel A are shown in time series.

For example, in the case of performing the driving as FIG. 5 (A), when the scanning electrode com1 is scanned, the pixel A in time Delta] t ₁
Is applied with a voltage of 3 V exceeding the threshold value _Vth , the pixel A is in one stable state, that is, “bright” regardless of the previous history.
Transition to a state. Thereafter, Com2～com5 ... although while being scanned continuously applied voltage -V as shown in FIG. 5 (A) is, because this does not exceed the threshold value -V _th, pixel A is "bright" state Can be kept.

However, when displaying information in which one signal (corresponding to “dark” in this case) is continuously applied on one signal electrode, the number of scanning lines is extremely large and high-speed driving is performed. There are problems that arise when required.

FIG. 4 characteristically shows this, in which the horizontal axis represents the drive voltage value V and the vertical axis represents the pulse width ΔT (application time). As is clear from FIG. 4, the threshold value V _th (driving voltage value) has an application time dependency,
It is further understood that the shorter the application time, the steeper the curve. Therefore, when the driving waveform as shown in FIG. 5 (A) is taken and this is applied to an element which has an extremely large number of scanning lines and is driven at high speed, for example, the pixel A is "bright" at the time of com1 scanning. Even if it is transferred to the state, co
Since the voltage of -V is always applied after the scanning of m2, the transition can be performed even at a low threshold value due to the accumulation of the application time until the scanning electrode com1 is scanned again, and the pixel A is inverted to the "dark" state. You can see that there is a risk that

As a driving waveform for preventing such a phenomenon, for example, a method shown in FIG. 5B can be used. In this method, a scanning signal and an information signal are not continuously transmitted, but a predetermined time interval Δt ′ is provided as an auxiliary signal application period, and an auxiliary signal for setting a signal electrode to a ground state during this period is provided. I have. During the auxiliary signal application period, the scanning electrode is also grounded, so that the voltage applied between the scanning electrode and the signal electrode is a reference potential, and the voltage application time dependency of the threshold voltage of the FLC shown in FIG. It can be substantially eliminated. Therefore, it is possible to prevent the “bright” state generated in the pixel A from being inverted to the “dark” state. The same applies to other pixels.

Further, another more preferable example can be implemented by applying the driving waveform shown in FIG. 6 to the scanning electrode and the signal electrode group.

In FIG. 6, the scanning signal is an alternating pulse signal of ± 2V. An information signal is sent to the signal electrode group in synchronization with the pulse signal, which is a voltage of + V or -V corresponding to the information of "bright" or "dark", respectively. now,
When the scanning signals are viewed in chronological order, a time interval Δt ′ is provided as an auxiliary signal application period between com n (the n-th scanning electrode) and com n + 1 (the n + 1-th scanning electrode). Then, when an auxiliary signal having a polarity opposite to that of the signal electrode group at the time of comn scanning is sent to the signal electrode group during this time, the time series signal given to each signal electrode is, for example, seg1 to seg3 in FIG.
As shown in. That is, α'in FIG.
The auxiliary signals of ε ′ have polarities opposite to the polarities of the information signals α to ε, respectively. Therefore, for example, in FIG. 6, when the voltage applied to the pixel A is viewed in chronological order, even if the same information signal is continuously applied to one signal electrode, the voltage actually applied to the pixel A is Since the voltage below V _th alternates, the dependency of the voltage application time on the threshold voltage in the FLC is eliminated, and the desired information (in this case, “bright”) formed at the time of com1 scanning is written in the next write Is not inverted until the operation is performed.

The two examples of the drive waveforms described above are conceptual for the sake of description. In the embodiments described later, the driving of the effective display area 104 and the frame 106 in the display screen 102, or the mode of actual access, and further, Different suitable drive waveforms are used depending on the temperature. Further, although the above-mentioned waveform is positive and negative symmetrical, it is not necessarily symmetrical in the embodiments described later.

(3.3) Driving voltage of display element The FLC display element according to this example is, as described above, also applied when the liquid crystal molecules are oriented so as to have their dipole moment in the direction of the electric field, and when the electric field is removed. The feature is to maintain the orientation.

By the way, the state change from one of the two stable states realized as described above to the other depends on the voltage value applied to the display element.

That is, FIGS. 7A and 7B show the change over time of the drive voltage (applied voltage) and the transmittance of the FLC. In the figure (A), the drive voltage is the threshold voltage −V.
_In this case, the transmittance changes from one state to the other state (for example, “bright” to “dark”).
FIG. 7B shows a case where the driving voltage does not exceed the threshold value. At this time, although the liquid crystal molecules react, the orientation does not reverse, and the transmittance returns to the original state.

Furthermore, the threshold differs depending on the type of FLC and also changes depending on the driving temperature. This will be described later with reference to FIG.

Next, as described above with reference to FIGS. 4 and 6, the driving voltage values are positive / negative of the scanning signal, positive / negative of the information signal,
And five values of a reference potential are required, and these drive voltages are generated by an apparatus according to the present embodiment, which will be described later, using an appropriate power supply.

As is clear from the above, when setting the drive voltage, appropriate temperature compensation in consideration of the threshold value and the like must be performed.

(3.4) with respect FLC display control of the temperature compensation this embodiment, it should be taken into account in particular the temperature compensation of the SmC ^* phase as described above F
The driving conditions related to each other, such as the pulse width (voltage application time) and the driving voltage value, vary greatly depending on the temperature of the FLC, and the range of these driving conditions allowed at a predetermined temperature is narrowly limited. For this reason, fine temperature compensation during FLC driving is required.

This temperature compensation is FLC temperature detection, in effect the display screen 1
This is performed by detecting the ambient temperature in 02, setting the drive voltage value corresponding to the detected temperature, and setting the pulse width, that is, one horizontal scanning period. In view of the operation speed of the display screen 102 and the like, manual compensation is extremely difficult. Therefore, temperature compensation is a unique requirement in FCL display element control.

Hereinafter, a description will be given of how the FLC driving conditions such as the pulse width and the driving voltage value change with the temperature fluctuation.

FIG. 4 shows the relationship between the drive voltage value and the pulse width as described above, and it can be seen from FIG. 4 that a larger drive voltage V is required as the pulse width ΔT becomes shorter.

The pulse width ΔT has an upper limit ΔTmax and a lower limit ΔTmin.
Exists for the following reasons. That is, at the time of so-called refresh driving, the frequency f of the applied voltage (= 1 /
If ΔT) is less than about 30 Hz, flickering occurs, so the frequency f has a lower limit, that is, ΔTmax, and the frequency f must be higher than the video rate, that is, higher than the speed of data transfer from the word processor main body 1 side. Then
Since the display screen 102 and the word processor body 1 cannot communicate with each other, the frequency f has an upper limit, that is, ΔTmin.

In addition, similarly for the drive voltage V, the upper limit Vmax and the lower limit
Vmin exists. This is mainly due to various functions on the drive device side.

FIG. 8 shows the relationship between the drive voltage and the temperature when the temperature Temp is plotted on the horizontal axis and the logarithm of the drive voltage V is plotted on the vertical axis.
This figure shows the threshold voltage value V _th accompanying a temperature change when the pulse width ΔT is fixed. As is clear from the figure,
It is understood that the drive voltage value decreases as the temperature increases.

From the description with reference to FIGS. 4 and 8, it can be understood that as the temperature increases, the drive voltage value decreases or the pulse width decreases.

FIG. 9 is a diagram for providing the relationship between the various driving conditions as described above to the actual driving. FIG. 7 shows a look-up table described later in an analog manner. The look-up table stores data on various driving conditions corresponding to the values detected by the temperature sensor 400.

FIG. 9 is a diagram in which the horizontal axis indicates the temperature Temp, and the vertical axis indicates the drive voltage V and the frequency f (= 1 / ΔT). When the frequency f is fixed in the temperature range (A), the temperature Temp Rises, the drive voltage value V drops and exceeds Vmin. Therefore, at the temperature point (D), a larger frequency f is set to a fixed value,
The drive voltage value V corresponding thereto is also determined. Thereafter, similar operations are repeated in the temperature ranges (B) and (C) and the temperature point (E). The shape of the curve formed as described above depends on the characteristics of the liquid crystal and the like, and the number of staircase waves and sawtooth waves can be determined as appropriate.

 Further, in the embodiment, the following is considered.

The characteristics of the FLC element change significantly even in the temperature range in which it is normally used, and it may not be sufficient to adjust the pulse width and voltage by defining a single drive waveform as described above. For example, even in the range of 45 ° C to 5 ° C, the operating speed may be different on the order of several times. In such a case, the operator feels uncomfortable due to the difference in environmental conditions such as time zone and season. Will also occur.

Therefore, in the embodiments described below, the temperature range that is normally used is divided, and appropriate drive waveforms are defined in each of the divided temperature ranges, and the pulse width is also changed for each drive waveform according to the temperature. The operating characteristics are averaged by adjusting the voltage and the voltage.

(3.5) Display Driving Method In this example, the mode of data access to the display screen 102 includes line access performed for each horizontal scanning line (line corresponding to the common-side transparent electrode 114) and several lines as one unit. Block access to be performed for each of the blocks described above, and access is performed by any of the preset settings. Further, the block or line relating to the access can be recognized by the real address data from the word processor main body 1 as the host device.

Here, FIG. 10 shows m blocks BLK1, ..., BLKl, ..., BLKm (1 ≦ l ≦, which include a predetermined number of lines in the effective display area 104.
m) is shown. In this example, 400 common side transparent electrodes 114 (400 lines) in the vertical scanning direction.
And divides the effective display area 104 into 20 blocks (m = 20) in units of 20 lines. And
When accessing data for such a divided block, first, display of all lines included in the block is erased, and then data is sequentially written from the first line to the last line of the block.

On the other hand, when the display device 100 is configured as shown in FIGS. 2 and 3, the FLC element has a memory property,
Data that is not updated on the display screen does not need to be refreshed, and it suffices to access only the changed data to the display screen.

In this example, according to the function of the work processor main body 1 which is the host device, refresh drive for constantly refreshing the display from the first line to the last line of the effective display area 104, that is, a display device having no memory is driven. In this case, refresh driving equivalent to the so-called refresh driving in the above case and partial rewriting driving in which only the block or line is rewritten when a change occurs are possible. That is, when the word processor main body 1 transmits refresh data in the same manner as the refresh for a display device having no memory, a refresh operation is performed, and when a change occurs, the image data of the block or line is changed. Is transmitted, a partial rewriting operation is enabled.

Further, when erasing a block or writing to a line, driving based on the temperature compensation data described in (3.4) above is performed. In the refresh drive mode, the temperature compensation data is updated during a period from the end of access to the last line to the access to the top line, that is, during a vertical flyback period. On the other hand, when partial rewriting is performed, it can be performed at regular intervals by a periodic interrupt.

In addition, considering the driving condition described in (3-2),
When a positive or negative asymmetric drive waveform is applied to a line, the positive or negative energy is applied to that line more than the other, and the stable state of the FLC element changes as it is, and attention is paid to the memorability of the FLC element. It is considered that the control is adversely affected. Therefore, in the embodiment, by giving an appropriately determined waveform and a waveform obtained by inverting the waveform in the driving period of one line (hereinafter, this is referred to as in-line inversion), the total driving energy in the one line is calculated. It is set to 0 so that no change occurs in the stable state of the FLC element.

Further, the writing drive of the display device 100 is performed by sequentially scanning while selecting the scanning power source 114 (common line), and simultaneously supplying a signal to the signal electrode 124 at the time of the selection. When the same waveform is applied to the lines, the elements exhibit the same optical response characteristics that are evenly shifted on the time axis for each line, which allows the scanner to display on the display screen.
You will feel flicker on 102. Therefore, in this embodiment, the drive waveform is inverted every line (every horizontal scanning) or every several lines, that is, an opposite phase waveform is given to every adjacent line or every several lines (hereinafter Is called MH inversion). This is based on the fact that human beings recognize the optical response in terms of surface, and therefore, if one adjacent line or several lines are driven in opposite phase, it is possible to prevent the swell from being felt on the display screen. .

In addition, in the embodiment, in the refresh drive mode, a process of inverting the drive waveform for each line every one unit (one frame) drive from the first line to the last line or every N frame drive (hereinafter, this is a frame (Reverse). That is, as a result of performing in-line inversion for a certain line of one frame, an appropriate waveform (hereinafter referred to as a normal waveform) I ′ and its inverted waveform I are given to the line in this order when the frame is driven. If so, the inverted waveform I and the normal waveform I ′ are provided in this order at the time of driving after the next frame or N frames. The effect of this frame inversion will be described later.

(3.6) Clearing of Display Screen In this example, since the FLC element has a memory property, the FLC element maintains the first or second stable state without applying a voltage. In other words, the previous screen is maintained unless a voltage is applied.

Therefore, it is desirable to clear the display screen 102 and at least the effective display area 104 when the power is turned off. This is because, for example, power cutoff can be recognized based on the state of the display screen 102. Also, the clear state of the display screen may change while the power is shut off for some reason, and meaningless data may be displayed.This prevents the actual display data from mixing with meaningless data during use. For this purpose, it is desirable to clear the effective display area 104 when the power is turned on.

Focusing on this point, in this example, the effective display area 104 is cleared when the power is turned on, the frame 106 is formed, and these are cleared even when the power is turned off. In clearing the effective display area 106, block erasure as described in (3.5) above is performed for all blocks.

Further, in such a clearing operation, the structure is such that the data can be erased without receiving the supply of screen erasure data (for example, all-white data) from the word processor main body 1 serving as the host device. And speeding up clearing by eliminating the need for transfer.

(4) Configuration of each part of display control device Each part of the display control device 50 for realizing each function described in "(3) Elements of display control" will be described in detail.

(4.1) Main symbols First, the signals and data transmitted and received between each section are summarized.

(4.2) Control Unit FIG. 11 shows a configuration example of the control unit 500. Here, 501 is, for example, a CPU in the form of a microprocessor that controls each unit according to the control procedure shown in FIG. 41, and 503 is a fourth executed by the CP 501.
This is a ROM in which various tables shown in FIG. 12 are expanded in addition to a program corresponding to the control procedure shown in FIG. A RAM 505 is used by the CPU 501 for work or the like in the process of executing the control procedure.

In this example, the RAM 505 stores a counter for frame inversion, that is, an area FC used as a counter by storing a value N indicating how many frames the frame is inverted.
NT and counter for MH inversion, that is, the area LCNT that stores a value that indicates how many lines each of which gives an antiphase waveform and is used as a counter, and when setting the waveform according to temperature, adopted at that time A register CX used for recognizing the waveform being generated is provided.

PORT1 to PORT6 are port sections for which input / output directions can be set, and ports P10 to P17, P20 to P27, and P30 to P3, respectively.
7, P40 to P47, P50 to P57 and P60 to P67. P
ORT7 is an output port and has P70 to P74. DDR1
˜DDR6 are input / output setting registers (data direction registers) for setting the switching of the input / output directions of the port sections PORT1 to PORT6, respectively. In this example, the ports P13 to P17 (signals A3 to A
7), ports P21 to P25 and P2 of PORT2
7. P40 and P41 of port PORT4 (corresponding to signals A8 and A9, respectively), ports P53 to P57 of port PORT5, port P62 of port PORT6 and port P72 of port PORT7
To P74 and the terminals MP0, MP1 and STBY of the CPU 501 are not used.

507 and 509 are a reset unit for resetting the CPU 501 and an operation reference clock (4M
Hz) is a clock generator that supplies.

TMR1, TMR2, and SCI are timers having a reference clock generation source and a register, and capable of dividing the reference clock in accordance with the settings in the register. First, the timer TMR2 divides the frequency of the reference clock according to the register setting, and generates a signal Tout serving as a system clock of the data output unit 600.
The data output unit 600 generates a clock signal that defines one horizontal scanning period (1H) of the display 100 based on the signal Tout. Timer TMR1 is the operating time on the program and the display screen 10
2 is used to adjust 1H, and such adjustment is realized according to the set value in the register.

The timers TMR1 and TMR2 output the signal IR as an internal interrupt when the set time based on the set value expires or when the next time measurement operation starts following the time up.
Q3 is supplied to the CPU 501, and the CPU 501 accepts it as necessary.

Note that the timer SCI is not used in this example.

Further, in FIG. 11, AB and DB are respectively CP.
An internal address bus and data bus connecting the U501 and each unit, and 511 is a handshake controller for the port units PORT5 and PORT6 and the CPU 501.

(4.3) Memory space of ROM (4.3.1) Configuration of memory space FIG. 12 shows a configuration example of a memory space allocated to the ROM 503. Here, in each area of AOOOH to A3FFH and A4OOH to A7FFH, data for specifying the A / D conversion unit 950 and the D / A conversion unit 900 at the time of access are stored, respectively. Data for designating the display drive register (see FIG. 16) when the data output unit 600 is accessed is expanded in A8OOH to ABFFH.

Areas COOOH to E7FFH are areas to be referred in response to the real address data RA / D sent from the word processor main body 1, and whether the address data sent at the time of block access is related to the block head line or not. It consists of a jumping table for making a determination and a line table for specifying the common side line to be driven for the sent real address data RA / D.

Areas E8OOH to FEFFH are areas for storing various parameter groups used for control described later with reference to FIGS. 42 and 45 to 47, and a block-related data area (E8OOH for storing the number of blocks (20 in this example)). ~), A D / A converter related data area (E) that stores data for adjusting the D / A converter 900 for variably setting the transparent electrode drive voltage according to the temperature.
9OOH ~), display unit 100 in block access mode
Clock To which is the reference for the above 1 horizontal scanning period (1H) setting
Block access timer TMR that stores setting data (TCONR) to register TCONR in timer TMR2 that outputs ut
2 setting data area (EAOOH ~), register setting data (CNTB) of timer TMR1 for delay time setting for adjusting the operation time on the display unit 100 and the time for control operation,
It has timer TMR1 setting data areas (EBOOH-, ECOOH-, EDOOH-) that store (CNTL) and (CNTBB).

In line access mode, 1 on display 100
Timer TMR that outputs clock Tout that is the reference for H setting
Line access timer TMR2 setting data area (EEOOH) that stores setting data (TCONRL) to register 2 of TCONR
~), And a line access jumping table area (EFOOH ~) for activating a program for driving with a waveform according to the temperature in the line access mode.

Region FOOOH ~ is shown in Figs. 41 to 42 and 45 to 4
This is a program area that stores programs corresponding to the processing procedures described later with reference to FIG.

(4.3.2) Jumping table (COOOH ~) in block access mode In this example, the real address data RA sent from the word processor main unit 1 side at the time of block access.
The processing path differs depending on whether / D is related to the block top line. This is based on the fact that, when address data corresponding to the first line of a block is supplied, the display in that block is cleared, and then the lines in the block are sequentially written.

For this reason, it is necessary to recognize whether or not the real address data RA / D sent from the word processor main unit 1 corresponds to the head line of the block. It is conceivable to sequentially compare and determine the address data each time the real address data is input.

However, according to such successive comparison, the processing time becomes different as the number of objects to be compared increases. That is, the number of comparison processes increases or decreases depending on the order of comparison comparison processing steps in the program.

Therefore, in the present embodiment, the following determination processing using the jumping table is performed to make the determination time uniform.

For example, as shown in FIG. 13, when the real address data from the word processor 1 is "03" H (line number "3"), this data is shifted left by 1 bit and the upper 2 bits are set to "1". Then, when the least significant bit is set to “0”, offset data “COO6” H is obtained. If this data is used as an address in the memory space, and a code indicating whether or not the block is the head line is stored in the address in the memory space, it is possible to determine whether or not all the actual address data is the block head line in exactly the same execution time. Can be identified.

Furthermore, the CPU 501 used is the index register (IX)
Can be used and the address jumped by the index register can be jumped (eg "JUMP IX" can be processed, the offset data is stored in IX and the jumping address is written in the jumping table. As a result, when the above command is executed, it becomes possible to immediately start appropriate processing.

In this example, an index register and one capable of using the above instructions are used as the CPU 501, and a jumping table (COOOH to C31EH) is provided corresponding to the line number (0 to 399) as shown in FIG. The procedure to be activated (specifically, the start address in the program area of the procedure) is stored in each address of the table.

In FIG. 14, BLOCK, LINE, and FLINE respectively indicate a block erasing procedure at the time of block access, a line writing procedure, and a procedure for updating the temperature compensation data accompanying the last line writing in the effective display area 104. And these are shown in FIGS. 45 (A) to (D).
Will be described later.

At the time of line access, only the last line needs to be determined in order to determine whether the temperature compensation data update procedure is to be performed. Therefore, the comparison target is one, and the line number is described above. The determination using the jumping address such as is not performed.

(4.3.3) Line Table The actual address data RA / D needs to be converted depending on the configuration of the common-side drive unit 300. For example, in this example, the driving unit 300 includes five common driving elements 310, each of which outputs 80 bits, and outputs 4 bits every 20 bits.
A block is formed, and 400 scanning lines are provided as common side lines. To select one of the scanning lines, (1) one of the five common driving elements 310 is selected.

(2) One of the four blocks assigned to the element 310 is selected.

(3) One line is selected from 20 lines in the block.

Process.

In this example, as shown in FIG. 15, a 2-byte line selection address is used, and the 12th to 8th bits thereof are used for selecting the element 310, the 6th and 5th bits are used for selecting the block, and the 4th bit is used. ~ Allocate 0th bit for line selection.
The conversion from the real address data to the line selection address data can be performed in substantially the same manner as the processing of FIG. 13 described for the jumping table, and the line selection address data may be developed in the line table.

In FIG. 15, reference numeral 680 denotes a decoder unit for selecting the element 310 (selecting the element chip).
With this configuration, and because 5 bits of the 12th to 8th bits are allocated for chip select, it is possible to add up to ²⁵ = 32 elements 310. At this time, it is possible to select 2560 scanning lines.

(4.3.4) Various parameter storage areas In this example, the driving condition of the display 100, that is, the driving voltage, one horizontal scanning period, and the delay data are changed according to the temperature condition, and the waveform data is also changed in the line access mode. This is changed to realize optimum drive control. Therefore, based on the temperature measurement data from the temperature sensor 400, the driving conditions must be corrected when driving.

Areas E9OOH to EEFFH are areas in which this correction data is stored, and the following storage is performed in this example in order to improve the efficiency of the reading process of various parameters according to temperature as described later.

That is, for one or a certain range of temperature in one step, for example, one D / A converter related data,
(TCONR) and (CNTB), (CNTL) or (CNTBB)
Assuming that (TCONRL) is associated, a group of parameters corresponding to temperature is stored in an area where the lower 2 bytes have the same value. In substantially the same manner as described with reference to FIG. 13, the temperature data obtained from the A / D converter 950 or temperature data obtained by appropriately processing the temperature data is used as the address of the lower 2 bytes, and the upper 2 bytes are sequentially rewritten and read. For example, a group of parameters corresponding to the temperature is obtained.

For example, if the temperature data is “0080” H, first access the address “E980” H, which is the sum of “E900” H, to access the related data (driving voltage) for the D / A converter corresponding to that temperature. ) Is obtained, and then the timer TMR2 is accessed by accessing the address “EA80” H obtained by adding “0100” H to “E980” H.
Setting data (TCONR) (data for generating a basic clock that defines one horizontal scanning period on the display screen)
Is obtained. Hereinafter, by similarly performing addition and access, CNTB, CNTL, and CNTBB corresponding to the temperature are sequentially obtained.

Further, especially in the line access mode, the waveform is changed according to the temperature, ΔT changes significantly, and the data (TCONR) in the block access mode cannot be used as it is. Data from EEOOH to temperature and waveform (TCONRL)
Read out and set.

In addition, in the jumping table area EFOOH to be used in the line access mode, the start addresses of programs for driving with a waveform according to the temperature are stored in advance, and the jumping table for block access (14th The startup process is performed in the same manner as (see the figure).

In this example, the operating temperature range of 45 ° C. to 5 ° C. is assumed, and this range is divided into three, and in the range of 45 ° C. to 35 ° C., the waveform described later with reference to FIG.
In the temperature range of 35 ° C to 15 ° C, the waveform described later with reference to Fig. 30 (hereinafter referred to as N waveform) does not include inversion in the line, and in the temperature range of 15 ° C to 5 ° C. The waveform described below with reference to FIG.
It is called a waveform. ) Are set respectively to control. For this reason, in this example, different programs are started in each temperature range, and the routines LSTRA0, LSTRN0, and LSTRC0 relating to the output of the A waveform, the N waveform, and the C waveform, respectively.
The top address of the table is tabulated on the area EFOOH ~ corresponding to the temperature.

(4.4) Data Output Unit (4.4.1) Configuration FIG. 16 shows an example of the configuration of the data output unit 600. Here, reference numeral 601 denotes a data input unit which is connected to the word processor main body 1 and receives the signal D and the transfer clock CLK.
The signal D is a signal to which the image signal and the horizontal synchronizing signal are added and transmitted by the word processor main body 1. In this example, the real address data is superimposed and supplied during the horizontal synchronizing signal or the horizontal blanking period. Is done. Thus, the data input unit 601 switches the data output path according to the presence or absence of the detection of the horizontal synchronizing signal or the horizontal blanking period, and upon detection, recognizes the signal component superimposed at that time as real address data. The data is output as real address data RA / D, and when not detected, the signal components between them are recognized as image data and output as 4-bit parallel image data D0 to D3.

When the data input unit 601 recognizes the input of the real address data, it activates the address / data identification signal A /.
It is guided to the generation unit 605. The generator 603 outputs an interrupt signal ▲ ▼ in response to the arrival of the signal A /, which is an interrupt command ▲ according to the setting of the switch 520.
The signal is supplied to the control unit 500 as ▼ or ▲ ▼, and the operation in the line access mode or the block access mode is performed. On the other hand, the DACT generation unit 605 outputs a DACT signal for identifying the presence or absence of access of the display device 100 in response to the input of the signal A /, and outputs the DACT signal to the control unit 500.
▲ ▼ It leads to the generation unit 611 and the gate array 680.

The generator 611 generates a signal ▲ for activating the gate array 680 in response to the input of the trigger signal from the trigger generator 613 when the DACT signal is activated. The trigger generation unit generates a trigger signal in response to a write signal ▼ instructing the control unit 500 to take in temperature information from the temperature sensor 400 to the A / D conversion unit 950. At this time, ▲ ▼ Trigger generator
613 is selected by a chip select signal ▲ ▼ generated by the device selector 621. That is,
When the control unit 500 performs the chip select of the A / D conversion unit 950 to read the temperature data, the trigger generation unit
613 is also selected, and the frame drive is also activated according to the line signal ▲ ▼.

Reference numeral 619 denotes a busy gate which sends a signal BUSY for notifying the busy state of the display control device 50 to the word processor 1 in response to a busy signal IBUSY from the control section 500.

621 receives signals A10 to A15 from control unit 500, and signals ▲ ▼ to perform chip select of A / D conversion unit 950, D / A conversion unit 900 and data output unit 600 according to the values.
Output ▲ ▼. 623 is activated in response to the signal ▲ ▼, and at this time, the latch pulse gate array 625 is set based on the signals A0 to A4 from the control unit 500. The latch pulse gate array 625 is used to select each register of the register section 630, and has a number of bits corresponding to the number of registers of the register section 630. In this example, the register section 630 has 22 areas of 1 byte each, and the latch pulse gate array 625 has a 22-bit configuration in which each area corresponds to 1 bit. That is, when the register selector 623 sets the bit of the latch pulse gate array 625, the area corresponding to the bit is selected, and the read signal ▲ ▼ or the write signal from the control unit 500 to the latch pulse gate array 625 is selected. ▲
In response to the supply of ▼, data reading or data writing to the selected register via the system data bus is performed.

In the register section 630, RA / DL and RA / DU are real address data registers for storing lower and upper one bytes of the real address data RA / D, respectively, and this storage is performed by the real address storage control section 641.

DCL and DCU are horizontal dot count data registers for storing the lower and upper 1 bytes of data corresponding to the value of the number of dots (800 dots in this example) in the horizontal scanning line direction of display. The horizontal dot number counter 643, which is activated at the transfer time of the image data D0 to D3 and counts an appropriate clock, has a latch signal ▲ when performing a counting operation equal to the numbers stored in the registers DC L and DC U.
The generation unit 645 of ▼ is caused to generate it.

DM is a drive mode register in which mode data corresponding to line access or block access is written.

DLL and DLU are registers for the common line selection address data, and store the lower and upper one byte of the 16-bit data shown in FIG. 15, respectively. The data stored in the register DLL includes address data CA6 and CA5 for block designation (corresponding to the sixth and fifth bits in FIG. 15) and address data CA4 to CA0 for line designation (FIG. 15). (Corresponding to the 4th to 0th bits). Further, the data stored in the register DLU is supplied to the decoder section 650, and the chip select signals ▲ ▼ to ▲ for selecting the common drive element 310.
Output as ▼.

CL1 and CL2 are 1-byte areas for storing drive data to be supplied to the common-side driving unit 300 when driving (line writing) the common-side line in the block access mode. SL1 and SL2 are also used for driving the segment-side line. This is a 1-byte area for storing drive data to be supplied to the side drive unit 200.

CB1 and CB2 are 1-byte areas for storing drive data to be supplied to the common-side drive unit 300 when driving the common-side line during block erase in the block access mode, and SB1 and SB2 are similarly supplied to the segment-side drive unit 200 This is a 1-byte area for storing drive data to be executed.

CC1 and CC2 are 1-byte areas for storing data to be supplied to the common-side drive unit 300 when driving the common-side line during line writing in the line access mode.
Similarly, C1 and SC2 are 1-byte areas for storing drive data to be supplied to the segment side drive unit 200.

The following three 1-byte areas are areas for storing data for switching the frame driving unit 700, and registers FV1, FCVc, FV2, FV3, FSVc, FV4 are provided for each 4 bits.

661 is a multiplier, which is a pulse signal Tout from the control unit 500.
Is doubled, for example. 663A, 663B, 663C and 663D are 3-phase, 4-phase, 6-phase and 12-phase ring counters of the output of the multiplier 661, and one horizontal scanning period (1 when selecting N waveforms in block access mode or line access mode.
H) is divided into four, three, two, and no divisions, respectively. The divided period is hereinafter referred to as ΔT. For example, in the case of three divisions, 1H is formed by 3ΔT.

In the line access mode, when selecting the A waveform and the C waveform related to the in-line inversion control that uses the normal waveform I ′ and the inverted waveform I in combination, the output period of the waveform I or I ′ (hereinafter, 1H ^* period) is selected. This means that 1H ^* periods are combined to form 1H. Also, 1H = 1H ^* when no line inversion is performed.) Is divided into four, three, two or none by the ring counter. Will be divided. At this time, for example, in the case of 3 divisions, with 3ΔT
Will be made to IH ^*, is set to approximately smaller becomes the value in comparison with ΔT in this case ΔT in this case is not carried out in-line inversion.

Reference numeral 665 denotes a multiplexer for selecting any one of the outputs of the ring counters 663A to 663D, and is set according to the contents of the drive mode register DM, that is, according to data indicating how many divisions of 1H are to be performed. You. For example, 3
In the case of division, the output of the four-phase ring counter 663B is selected.

Reference numeral 667 denotes a four-phase ring counter for each output of the ring counters 663A to 663D, and 669 denotes a multiplexer set similarly to the multiplexer 665.

FIG. 17 shows the clock Tout, the output waveform of the multiplier 661, and the output waveforms of the ring counters 663A to 663D and 667. That is, the ring counters 663A to 663
If any of 63D output is selected, 4ΔT / 1H, 3ΔT / 1
H, 2ΔT / 1H or ΔT / 1H (or 4ΔT / 1H ^* , 3ΔT / 1
H ^* , 2ΔT / 1H ^* or ΔT / 1H ^* ) is selected, and its output waveform is supplied as a shift clock to a shift register unit 673 described later to output ON / OFF data for each ΔT. Further, one of the outputs of the four-phase ring counter 667 is selected by the multiplexer 669, and this output waveform is supplied to the shift register section 673 as a shift / load signal to set the operation at the selected number of divisions. Be seen.

Referring to FIG. 16 again, in the register section 630, on / off data for each ΔT of the clear signal ▼ and the enable signal CEN sent to the common side driving section 300 are stored in the areas CL1, CB1 and CC1 in the area CL2. , CB2 and CC2 similarly store ON / OFF data of the drive waveform defining signals CM1 and CM2 for each ΔT. Also, the areas SL1, SB1 and S
On / off data for each ΔT of the clear signal ▲ ▼ and the enable signal SEN to be sent to the segment side driving unit 200 are stored in C1, and for each ΔT of the waveform defining signals SM1 and SM2 in the regions SL2, SB2 and SC2. Stores ON / OFF data of.

In this example, the storage area for each signal data has a 4-bit configuration, and one bit corresponds to 1ΔT on / off data. That is, in this example, the maximum number of divisions of 1H or 1H ^* is 4.

Reference numeral 671 denotes a multiplexer unit coupled to the regions CL1 to SC2, which outputs signal data at the time of line writing in the block access mode, block erasing, and driving at the time of line writing in the line access mode according to the contents of the drive mode register DM. Choose one. In this multiplexer section 671, MPX1 is divided into areas CL1, CB1 and CC
A multiplexer that selects 4-bit data for any signal from 1 to 4, MPX2 is a multiplexer that selects 4-bit data for the signal CEN, and MPX3 is an area
Multiplexer that selects 4-bit data for either signal CM1 from CL2, CB2 and CC2, MPX4 is the same signal CM
A multiplexer for selecting 4-bit data for 2. MPX5 is a multiplexer for selecting 4-bit data for any of the signals ▲ ▼ from the areas SL1, SB1 and SC1, MPX6 is a multiplexer for selecting 4-bit data for the signal SEN, and MPX7 is for areas SL2, SB2 and SC2.
, MPX8 is a multiplexer for selecting 4-bit data for the signal SM2, and MPX8 is a multiplexer for selecting 4-bit data for the signal SM2.

Reference numeral 673 denotes a shift register unit having shift registers P / S1 to P / S8 for parallel / serial (P / S) conversion respectively coupled to MPX1 to MPX8 of the multiplexer unit 671, and the output of the multiplexer 665 is used as a shift clock signal. The output period ΔT of the supplied 1-bit ON / OFF data is defined. Further, the output of the multiplexer 669 is provided as a preset signal for performing the operation with the set number of divisions.

Reference numeral 675 denotes a multiplexer unit having multiplexers MPX11 to MPX18 coupled to the shift registers P / S1 to P / S8, respectively, and bit selection data (registers) of 4-bit on / off data of each signal stored in the registers CL1 to SC2. DM
On / off data is output based on the P / S conversion.

An output unit 677 performs the same processing as the shift register unit 673 and the multiplexer unit 675 with respect to the registers FV1, FCVc, FV2, FV3, FSVc, and FV4.
A gate array which is opened according to ▼ and guides the switch signals ▲ ▼ to ▲ ▼, ▲ ▼ and ▲ ▼ to the frame drive unit 700.

690 is a signal in response to the activation of the chip select signal DS1 of the D / A converter 900, that is, when the D / A converter 900 is accessed.
Clock E generated by CPU 501 by sending MR to control unit 500
It is the MR occurrence that changes the pulse width of.

(4.5) A / D Conversion Unit FIG. 18 shows a configuration example of the A / D conversion unit 950. Where 95
Reference numeral 1 denotes an A / D converter, and reference numeral 953 denotes an amplifier that amplifies a detection signal of the temperature sensor 400 to a level suitable for the A / D converter 951.

When detecting the temperature, the control unit 500 sends a chip select signal ▲ via the device selector 621 of the data output unit 600.
In addition to supplying ▼, a line signal ▲ ▼ (shown here as ▲ ▼) is transmitted. A / accordingly
The D converter 951 converts an analog amount of temperature detection signal obtained from the temperature sensor 400 via the amplifier 953 into a digital amount, and activates the signal ▲ ▼ at the end of the conversion to perform A / D conversion.
The control unit 500 is notified of the end of conversion.

In response to this, the control section 500 supplies a read signal ▲ ▼ (shown here as ▲ ▼) to the A / D converter 951, and in accordance with this, the A / D converter 951 transmits digital temperature data to the signal DD0. Control unit 50 via system bus as ~ DD7
Send to 0.

The temperature detection timing can be performed during the vertical flyback period from the end of the last line drive to the start of the first line drive when refresh drive for constantly refreshing the display from the first line to the last line of the effective display area 104 is performed. . Further, when partial rewrite driving for rewriting only the block or the line when the display data is changed is performed, the partial rewrite driving can be performed periodically by, for example, a timer interrupt.

(4.6) D / A Conversion Unit and Power Supply Controller FIG. 19 shows a configuration example of the D / A conversion unit 900 and the power supply controller 800.

In the D / A converter 900, 901 is a D / A converter, and 903 is an amplifier that amplifies the output so as to be suitable for the next stage.

In the power supply controller 800, 810, 820, 825, 830 and 840 are variable gain amplifiers for generating voltage signals V1, V2, VC, V3 and V4, respectively, and the voltage V1 is an amplifier.
By guiding the output of 903 to the amplifier 810, the voltage V2, VC, V3
And V4 output the output of amplifier 810 to amplifiers 820, 825, 8 respectively.
Generated by leading to 30 and 840. 821 is an amplifier 81
An inverter inserted between 0 and 820, 841 is an amplifier 810
It is an inverter inserted between 840.

Here, the voltages V1 and V2 are the positive and negative driving voltages supplied to the common side driving unit 300, the voltages V3 and V4, respectively.
Are the positive and negative drive voltages respectively supplied to the segment side drive unit 200, and the voltage VC is the reference potential given to each drive unit 200, 300. These voltage signals are also supplied to the frame drive unit 700.

In this example, VC is fixed and V1, V
The gain adjustment of each of the amplifiers 810, 820, 825, 830 and 840 is performed in advance so that the ratio of the difference between 2, VC, V3, and V4 becomes 2: −2: 0: 1: −1.

When changing and setting the drive voltage according to the temperature,
The reference numeral 500 supplies a chip select signal ▲ ▼ via the device selector 621 of the data output unit 600 to select the D / A converter 901. Here, if the basic clock for the operation of the D / A converter 901 is different from the control unit 500, the signal ▲ ▼
Is also supplied to the MR generation unit 690 arranged in the data output unit 600 to generate the signal MR, so that the control unit 500 supplies an appropriate clock signal E to the D / A converter 901. Thus, the control unit 500 activates the write signal ▲ ▼ (shown here as ▲ ▼) and also supplies the digital data for change setting as DO0 to DD7 to the D / A converter 901 via the system bus. In response, the D / A converter 901 converts the data into an analog signal and outputs the analog signal via the amplifier 903.

As a result, the amplifier 810 generates the voltage V1 and the voltages V2, VC, V3 and V4 having the above ratio with respect to V1.

Although the voltage V2 and the like are generated in accordance with the voltage V1 in the example of FIG. 19, the output of the amplifier 903 may be separately led to each of the variable gain amplifiers 810, 820, 825, 830, and 840. Further, a variable gain amplifier which can programmatically adjust the gain may be used. Also,
It is needless to say that the configuration of the power supply controller 800 is not limited to the above configuration and can be various configurations as long as it can generate a multi-valued voltage according to the driving mode of each of the driving units 200 and 300. .

(4.7) Frame Drive Unit FIG. 20 shows a configuration example of the frame drive unit 700. Where 71
0,715,720,730,735 and 740 are voltage signals V
1, a switch for turning on / off the supply paths of VC, V2, V3, VC and V4. Switch signals supplied from the gate array 680 of the data output unit 600 via inverters 711, 716, 721, 731, 736 and 741, ▲ ▼, ▲
Controlled by ▼, ▲ ▼ and ▲ ▼.

When driving the frame, the register unit 630 of the data output unit 600
Depending on the contents of the registers FV1, FCVc and FV2 provided in, that is, signals ▲ ▼, ▲ ▼ and ▲ ▼
The switches 710, 715, and 720 are switched according to the state of (1), and a signal having a waveform having three values of V1, VC, and V2 can be applied to the frame transparent electrode 151 parallel to the common line. Further, switches 730, 735 and 740 are switched according to the contents of registers FV3, FSVc and FV4, that is, according to the states of signals ▲, ▼ and 、, and V3, VC
And V4 can be applied to the frame transparent electrode 150 parallel to the segment line.

(4.8) Display drive unit (4.8.1) Segment side drive unit FIG. 21 shows a schematic configuration example of the segment drive element 210 constituting the segment side drive unit 200. Where 220
Input 4-bit parallel image data D0-D3 sequentially,
It is a 4 × 20 bit shift register that is aligned with 80-bit parallel data, and operates according to the input of the shift clock SCLK. Reference numeral 230 denotes an 80-bit latch unit, and the image data D0 to D3 are guided to the shift register 220 of the next-stage segment drive element 210, and the ten elements 2
When 80-bit parallel data is aligned in all ten shift registers 220,
When a latch signal ▼ is supplied from the generation unit 645, 80-bit parallel data is latched.

240 is a signal from the data output unit 600 ▲ ▼, ▲
▼, an input logic circuit that receives SM1 and SM2 and performs a predetermined logic operation, and 250 generates prescribed data of each segment drive waveform corresponding to the content of each bit data of the latch unit 230 from the operation data of the input logic circuit 240 Is a control logic unit. Reference numeral 260 denotes a switch signal output unit having a level shifter and a buffer for performing a level shift of data generated by the control logic unit 250, and 270 receives the voltage signals V3, VC and V4 and is switched according to the output of the switch signal output unit 260. This is a driver for guiding V3, VC or V4 to the segment lines S80 to S1.

FIG. 22 shows a detailed structural example of the segment drive element 210 shown in FIG. 221 in the shift register 220
Is a D-type flip-flop corresponding to one bit, that is, one segment line. In the latch unit 230, 231 is a latch circuit. In the switch signal output unit 260, 261
275, 273 and 27 in level shifter, driver 270
4 turns on / off the supply paths of the voltages VC, V3, and V4 in accordance with the switch signal from the switch signal output unit 260, respectively.
This is a switch that turns off.

(4.8.2) Common Driving Unit FIGS. 23 and 24 show a schematic configuration example and a detailed configuration example of the common driving element 310 constituting the common driving unit 300, respectively. Here, 340 is an input logic circuit, and when the chip select signal ▲ ▼ is given from the decoder unit 650 of the data output unit 600, signals CA5, CA6, CE
In addition to block selection by N, line selection signal CA0 ~
CA4, signals ▲ ▼, CM1 and CM2 are received to perform a predetermined logical adjustment.

A decoder unit 345 selects a common line to be driven based on the line data related to the signals CA0 to CA4 supplied from the input logic circuit 340. One element 310 can select 80 lines. In this example, 20 lines are defined as one block, and four blocks are allocated to one element 310. In FIG.
345 is surrounded by a broken line for each part where 20 lines are decoded.

Reference numeral 350 denotes a control logic unit, which specifies drive waveforms of a block selected by the input logic circuit 340 or a line selected by the decoder unit 345 from drive data related to the signals CM1, CM2 and ▲ ▼ supplied by the input logic circuit 340. Generate data.

360 is a switch signal output unit having a level converter and a buffer for performing level conversion of data generated by the control logic unit 250, and 370 receives voltage signals V1, VC and V2 and switches according to the output of the switch signal output unit 360 And a driver for selectively supplying V1, VC or V4 to the common lines C1 to C80.

In this example, the common-side element 310 having such a configuration is used.
, That is, 400 common lines correspond to the effective display area 104.

In FIG. 24, 361 is a level converter, 375,3
Reference numerals 71 and 372 denote switches for turning on / off the supply paths of the voltages VC, V1 and V2, respectively, in accordance with the switch signal from the switch signal output unit 360.

(4.9) Drive waveform (4.9.1) Outline of display FIG. 25 schematically shows the display 100. Here, com and seg are a common line corresponding to the common side transparent electrode 1114 provided on the upper substrate 110 and a segment line corresponding to the segment side transparent electrode 124 provided on the lower substrate 120, respectively. FLC is provided. Fco
m and Fseg are frame common lines provided on both sides of the arrangement range of the common line com in parallel with the common line com, and frames provided on both sides of the arrangement range of the segment line seg in parallel with the segment line seg. It is a segment line for. Thus, an area on the display screen 102 corresponding to a set of intersections of the common line com and the segment line seg on FIG. 25 forms an effective display area 104, and the frame common line Fcom and the frame segment line Fseg A set of intersections with the segment line seg and intersections between the frame segment line Fseg and the common line com form a frame portion 106 outside the effective display area 104.

Note that in FIG. 25, four common lines com and four segment lines seg are shown for simplification, and one frame common line Fcom and one frame segment line Fseg are shown on each side. In the embodiment, 400 common lines com and 800 segment lines seg are arranged so that they can be driven one by one, and the common line Fcom for frames and the segment line Fesg for frames are arranged on both sides by 16 lines and driven together. It is as described above.

(4.9.2) Driving Mode of Display In this embodiment, the display 100 is driven as follows.

Regarding the effective display area 104, as described in (3.5) above, in the block access mode, block erasure is performed first, and then writing is performed for each line. In the line access mode, only writing for each line is performed. In this example, the area 104
Are driven with different waveforms at the time of block erase in the block access mode, at the time of line writing in the same mode, and at the time of line writing in the line access mode.

In line access mode, the temperature range is 45
Writing is performed with three kinds of waveforms of A waveform, N waveform, and C waveform according to the temperature of 35 ° C to 35 ° C, 35 ° C to 15 ° C, and 15 ° C to 5 ° C, respectively.

The correspondence between these modes and the reference drawings is as follows.

Block erasing in block access mode → Figures 26 (A), (B) and Figure 27 Line writing in block access mode → Figures 28 (A), (B) and Figure 29 Line acques mode 45 Range of ℃ to 35 ℃ → Fig. 34 Range of 35 ℃ to 15 ℃ in line access mode → Fig. 30 (A), (B), Fig. 31, Fig. 32, Fig. 33 (A) and (B) ) Range of 15 ℃ to 5 ℃ in line access mode → Fig. 35 Regarding the frame 106, the frame along the frame common line Fcom (hereinafter referred to as the horizontal frame) and the frame along the frame segment line Fseg ( (Hereinafter referred to as a vertical frame) at a different time and with a different waveform. That is, regarding the horizontal frame, the line Fcom and the lines Fseg and seg are set when the effective display area is not accessed (for example, the vertical blanking period during refresh driving and the interrupt by the timer during partial rewriting).
The vertical frame is formed by driving the common line com in line writing in any mode.
By driving the frame segment line Fseg with a waveform that matches the driving waveform of the above, the frame segment line Fseg is formed in cooperation with the common line com.

(4.9.3) Driving waveform of effective display area when 1H = 1H ^{* In} this embodiment, during block erasing in block access mode, line writing in the same mode, and N waveform selection in line access mode (35 ° C.) Up to 15 ℃) 1
The horizontal scanning period (1H) is divided into three, and driving is performed so that V1, VC or V2 is supplied to the common line com and V3, VC or V4 is supplied to the segment line seg during each ΔT period.

Table 1 shows an example of data set in the register areas CL1 to SC2 in the register unit 630 of the data output unit 600. In the table, “x” is an unused bit, and in this example, it is the 42nd bit.
At the time of activation of a processing procedure described later with reference to the drawing, predetermined data shown in Table 1 is developed in the sixth to fourth bits and the second to zeroth bits of the register areas CL1 to SB2. On the other hand, in the process of executing the processing procedure, the multiplexer unit 671 distinguishes the block erase in the block access mode, the line write in the same mode, and the line write in the line access mode into the register CB1 as appropriate in the register area DM of the drive mode. ~
Data to select SB2, registers CL1-SL2 or registers CC1-SC2, and multiplexers 665 and 669
, And data for allowing 3 bits of bit 6 to 4 or bit 2 to 0 to be selected and sequentially outputting 1 bit for a period of ΔT are stored.

Tables 2 and 3 show truth tables for the common drive element 310 and the segment drive element, respectively. In these tables, “×” indicates a case where the selected drive voltage V is not affected by either “1” or “0”. In Table 3, Q is 1-bit image data, that is, image data output from the latch 231 (see FIG. 22) of the latch unit 230. White data is obtained when Q = 0 and black data is obtained when Q = 1. Is output.

FIG. 26 (A) shows the contents of registers CB1 and CB2 (first
2 shows the waveforms of the signals CEN, ▲ ▼, CM1, and CM2 according to Table 2) and the waveform of the voltage signal V applied to the common line com by the logic of the common drive element 310 (see Table 2). Further, FIG. 3B shows registers SB1 and SB2.
Signal SEN, ▲ ▼, SM depending on the contents of (See Table 1)
1, the waveform of SM2 and the waveform of the voltage signal V applied to the segment line seg by the logic of the segment drive element 210 (see Table 3).

Therefore, when erasing the block in the block access mode, the common line com and the segment line seg in the block selected by the signals CA5 and CA6 are associated with the driving of the element 310 selected by the chip select signal ▲ ▼.
27, a difference between the voltages applied to the respective lines, that is, a composite waveform of the voltage signals as shown in FIG. 27 is added. Then, all the information of the block is cleared of white data by the value 3V0 of the voltage applied over the period ΔT.

At this time, as described above, ΔT or 1H and the voltages V1 to V4, VC are corrected according to the temperature.

FIG. 28 (A) shows a waveform of each signal CEN or the like based on the contents of the registers CL1 and CL2 and a voltage signal V applied to the common line com by the logic of the common drive element 310.
And the waveform of. FIG. 2B shows registers SL1 and SL2.
Waveforms of each signal SEN, etc. according to the contents of the above, the logic of the segment drive element 210 and the contents of the image data (Q)
Indicates a waveform applied to the segment line seg.

Therefore, at the time of line writing in the block access mode, the signal C in the block of the element 310 selected by the chip select signal ▲ ▼ and the signals CA5 and CA6.
At the intersection of the common line com and the segment line seg selected by A1 to CA4, FIG. 29 (A) or (B)
The composite waveform of the voltage signal shown in FIG.
Here, at the point where the waveform as shown in FIG. 29 (A) is applied, the display data does not change. That is, at that point, the state of becoming white data by the previous block erasing is retained. On the other hand, at the point where the waveform shown in FIG. 29 (B) is applied, white data is obtained by the voltage value 3V0 applied over the first period ΔT, but the voltage applied over the subsequent period ΔT The display data is inverted and becomes black by -3V0.

FIG. 30 (A) shows waveforms of signals CEN and the like which are output based on the setting of the contents of registers CC1 and CC2 in the temperature range of 35 ° C. to 15 ° C. at the time of line writing in the line access mode, and these. Accordingly, the waveform (N waveform) of the voltage signal V applied to the common line com by the logic of the common drive element 310 is shown. The same figure (B) shows each signal output based on the contents of the registers SC1 and SC2.
Waveforms such as SEN and corresponding waveforms applied to the segment line seg by the logic of the segment drive element 210 and the content (Q) of the image data are shown.

Note that these show normal waveforms in the temperature range, and when driving with an inverted waveform every line or every several lines, registers CC1 and CC2
It is sufficient to appropriately set the contents of (1) to output a waveform obtained by inverting the waveform to the common line com shown in FIG. 30 (A) according to the signal CEN or the like. The waveform output to the segment line seg may be that shown in FIG.

Thereby, at the time of line writing in the line access mode, the selected common line com and segment line s
The composite waveform of the voltage signal shown in FIG. 31 (A) or (B) is added to the intersection with eg. Here, FIG. 31 (A)
At the point where a voltage signal having a waveform as shown in FIG. 4 is applied, the voltage 2V0 and V0 applied over the first period ΔT and the next period ΔT respectively exceed the threshold value of the condition for obtaining white data, and the last period ΔT Since the applied voltage V4 does not exceed the threshold value for obtaining black data, the display is white. In addition, at the point where the waveform shown in FIG.
The display is white during the first 2ΔT period, but the last period Δ
The voltage -3V0 applied to T inverts the display, and black data is displayed.

32 and 33 (A) and (B) respectively,
The inversion waveform, the combined waveform when Q = 0, and the combined waveform when Q = 1 are shown, and white data and black data are obtained for the inverted waveform, respectively.

(4.9.4) Driving waveform including in-line inversion FIGS. 34 (A) to (E) show driving waveforms in the temperature range of 45 ° C. to 35 ° C. (A) is applied to the common line com. A waveforms (B) and (C) are
And the waveform supplied to the segment line seg according to Q = 0. The A waveform is basically a combination of the N waveform shown in FIG. 30 (A) and the inverted waveform, and the normal waveform I ′ and the inverted waveform I are each 3
Make up 1H ^* with ΔT. An appropriate rest period, for example, 1H ^* is provided between these waveforms, and 3H ^* constitutes 1H, that is, one horizontal scanning period. The value of ΔT is the setting data of timer TMR2 (TCONRL) from ROM503 according to the temperature condition.
Is set appropriately by reading.

In FIGS. 6D and 6E, black data and white data are displayed by adding the waveform of the segment line seg to the waveform A of FIG. That is, the hatched portion is involved in writing. In addition, these and Fig. 30 ~
In the case of FIG. 33, the polarity of the segmented waveform and the portion of the composite waveform to be written are opposite. This is because ΔT is smaller when the A waveform is used than when the N waveform is used. The waveform applied to the segment line is changed according to the change setting in the registers SC1 and SC2.

FIGS. 35 (A) to 35 (E) show driving waveforms in the temperature range of 15 ° C. to 5 ° C., where (A) is a C waveform when applied to the common line com, (B) and (C). Are respectively Q
Waveforms added to the segment line seg according to = 1 and Q = 0, (D) and (E) respectively have Q = 1
And composite waveforms when Q = 0 (black and white respectively)
, And writing is performed in the hatched portion.

In the C waveform, the normal waveform I ′ and the inverted waveform I
Each make up 1H ^* with 2ΔT. These are, for example, 1H ^*
Are combined with a rest period.

As shown in FIGS. 34 and 35, the A waveform and the C waveform include in-line inversion.
Inversion is performed, and in addition, frame inversion is performed.

Now, as shown in Figure 36, the screen at a certain point (1F)
At the m-th segment line and scan direction sc
It is assumed that “white”, “white”, “black”, and “black” are displayed at the intersections with the n−1 to n + 2th common lines on an. If this is scrolled on the next screen (2F), the segment line and n + th line will be displayed on 1F.
Assuming that the intersection with the third common line is "white", the segment line and the n-1 to n + th lines on 2F.
The display data of the intersection with the second common line are “white”, “black”, “black”, and “white”, respectively.

FIG. 37 is an explanatory diagram for explaining a drive mode in the case of performing display as shown in FIG. 36 while performing MH inversion and frame inversion with the A waveform shown in FIG. 34. For simplification, here, the case where the inversion is performed for each line and each frame is shown.

In the period of 1F, as shown in the upper left part of the figure, the A waveform and the inverted waveform of the A waveform are sequentially added to the common lines com n−1, n, n + 1, n + 2 line by line.
At this time, according to the waveforms (corresponding to “white”, “white”, “black”, and “black”, respectively) added to the segment line segm every 1H, hatching is performed as shown in the lower left part of the figure. A synthesized waveform in which writing is performed in the portion that has been written is obtained.

Next, in the 2F period, as shown in the upper right part of the figure, the common lines com n-1, n, n + 1, n + 2 are sequentially supplied with waveforms obtained by inverting the waveforms applied to the corresponding lines in 1F. . And at this time the segment line segm
Waveforms added every 1H (In 2F, the data in 1F is scrolled, so "white", "black", "black",
(Corresponding to "white"), a composite waveform in which writing is performed in the hatched portion is obtained as shown in the lower right portion of FIG.

(4.9.5) Relationship between temperature and ΔT or V in line access mode Fig. 38 shows an example of the relationship between temperature in line access mode and ΔT selected accordingly, and Fig. 39 also shows the temperature and the corresponding value. An example of the relationship with the selected V value is shown.
In either case, in the range of 45 ℃ ~ 35 ℃, A waveform, 35 ℃ ~
This is a case where driving is performed with an N waveform in the range of 15 ° C. and with a C waveform in the range of 15 ° C. to 5 ° C.

Further, the solid line in FIG. 40 is a diagram showing the temperature and the responsiveness of the screen when driven in this way. In the display device CS1017 (manufactured by Chisso Corporation) used by the present applicant, when driving is performed while appropriately changing ΔT and V with only the N waveform in the range of 45 ° C. to 5 ° C., as shown by the broken line in FIG. Responsiveness changed over ~ 3Hz, but when waveform, ΔT and V were changed according to temperature, the responsiveness was almost 8H as shown by the solid line in the figure.
could be averaged to z.

(4.9.6) Mode of Frame Drive In this example, as described above, the horizontal frame is formed at the same time as the vertical blanking period or at the same time as the driving of the A / D conversion unit 950 is started. It is formed during line writing in the effective display area 104. Further, the frame is provided in the same color as the background color of the effective display area 104, that is, in the case of displaying information in black, it is provided in white.

Table 4 shows registers FV1, FCVc, FV2, FV3, FSVc and FV4 for switching the frame driving unit 700 to form a frame.
Shows the data to be set. Here, the common line Fc for the frame
Since om is almost independent of the driving of the effective display area 104, the change setting of the contents of the data ▼, ▼ and ▲ is not performed. In this example,
The drive data of the frame common line Fcom is set so that a waveform equal to the drive waveform of the common line com shown in FIG. 26A is obtained when the horizontal frame is formed.

On the other hand, with respect to the frame segment line Fseg, the driving of the frame common line Fcom or the common line com is performed when the horizontal frame is formed, when the vertical frame is formed during line writing in the block access mode, and when the line is written in the line access mode. Since the waveforms are different, the registers FV3, FV4, and FSVc are changed and set so that white data is displayed in accordance with each.

Specifically, as the drive data of the frame segment line Fseg, a waveform equal to the drive waveform of the segment line seg shown in FIG. 26 (B) at the time of horizontal frame formation is obtained at the time of vertical frame formation at the time of line writing in the block access mode. 28th
A waveform that is the same as the drive waveform when the segment line seg shown in FIG. 3B when Q = 0 is obtained when the vertical frame is formed during line writing in the line access mode.
Segment line se shown in Fig. (C) or Fig. 35 (C)
Change settings are made so that a waveform equal to the drive waveform when Q = 0 of g is obtained.

As a result, the horizontal frame is formed by driving with the waveform shown in FIG. 27, the vertical frame has the waveform shown in FIG. 29 (A) in the block access mode, and FIG. 31 (A) in the line access mode. , (A), FIG. 34 (E), or FIG. 35 (E).

(5) Display control (5.1) Outline of control procedure There are two main features of the display control according to this example. For one, from the display control device 50 side to the word processor main body 1,
Data transfer and display screen 10 by sending a Busy signal
It is to synchronize with the operation of 2. This is essentially due to the fact that the display element using the FLC changes one horizontal scanning period depending on the temperature in order to make its operation effective.

Secondly, while a normal word processor transfers only image data sequentially, periodically and continuously (in a so-called refresh mode), the word processor body 1 of the present embodiment uses such data before the image data. It is to transfer address data for designating a pixel to be driven. Further, it is possible to transfer and drive image data of only a specific portion by the address data instead of the refresh mode. Things. This is because the display element using the FLC has a memory property, so that it is sufficient to access only the pixels that need to update information.

In order to enable the above display control, the word processor body 1 of the present embodiment, in addition to the functions of a normal word processor, receives a Busy signal and stops the transfer of address data. And a function to transfer the data.

By effectively using the features in the above display control, particularly the second feature, the following two display control modes are implemented.

That is, block access and line access. Block access means, for example, that 20 scanning electrode lines are set as one block, the screen of one block of the effective display area 104 is erased at one time, and the blocks to be covered are all “white”. Information is accessed for each scanning line to write characters and the like. On the other hand, the line access is an access for each scanning line to write information, and is not performed to make all the white in advance.

FIG. 41 shows these display control modes by a program flow, and the outline of the display control in this example will be described below with reference to FIG.

In FIG. 41, first, when the power of the word processor main body 1 is turned "ON", the INIT routine is automatically started (step S10).
1). Here, the Busy signal is set to “ON”, the driving of the frame 106, the erasing of the effective display area 104 and the temperature compensation therefor are performed when the power is turned on.
Interrupt request as F "▲ ▼ or ▲ ▼
Wait until comes. This interrupt request ▲ ▼ or ▲
▼ is generated when address data is transferred from the word processor main body 1,
If the address data does not come, the program will not be executed,
It remains on the display screen 102.

Next, when the address data is transferred and an interrupt request is issued, depending on whether this internal interrupt request is ▲ ▼ or ▲ ▼, the procedure of step S102 is followed.
If ▼, proceed to the BSTART routine. This branch separates the above-mentioned block access or line access. That is, if the process goes to the LSTR routine, it becomes a line access, and if it goes to the BSTART routine, it makes a block access.

By the way, in this example, the setting of ▲ or ▼ is manually performed in advance by the switching means 520 provided at an appropriate portion of the display control device main body 50.

When the line access mode is set by the switching means 520 and ▲ ▼ occurs, the following program is executed to proceed to the LSTR routine. First, before proceeding to the LSTR routine, step S103
Based on the temperature compensation data obtained in the INIT routine in
By referring to the line access mode data in the lookup table shown in FIG. 12, the system clock data for line access is set in the register TCONR of the timer TMR2.

Next, in step S104, the frame counter FCNT, line counter LCNT, and waveform recognition register CX are set.
Here, frame counter FCNT and line counter LC
NT is a counter provided to invert the drive waveform every N frames and M lines, and the waveform recognition register CX is a register provided to change the drive waveform according to the temperature of the FLC. is there. That is, in this step, setting is made as to how many frames and how many lines the drive waveform is to be inverted, and which of the three waveforms to be described later to be used is calculated based on the temperature compensation data in INIT. , Set the data in register CX.
The data setting in the register CX may be performed by referring to a table based on the temperature data. Step
In step S105, the line access jumping table shown in FIG. 12 is referred to based on the temperature data, and the respective routines LSTRA0 and LST corresponding to the three waveforms A waveform, N waveform, and C waveform are used.
Determine whether to proceed to RN0 or LSTRC0.

After that, line writing is performed by executing any one of the above-mentioned three routines and the routine subsequent thereto. This line writing is frame-by-frame and line-by-line,
Further, for the A waveform and the C waveform, the polarity of the drive waveform is inverted within one horizontal scanning period.

When the program execution shifts to the routine of the last line access of the frame, the line writing of the last line is performed,
Next, the frame drive and temperature compensation data are updated, the Busy signal is set to "OFF", and the interrupt request ▲ ▼ is waited for. When there is an interrupt request ▲ ▼, it is judged whether or not the drive waveform is changed, and the LSTR routine corresponding to the waveform is restarted.

On the other hand, in the case where the block access mode is set by the above-described switching means 520, the BSTART routine is started when a ▼ occurs due to the address data transfer. Here, the Busy signal is set to “ON”, the transferred address data is read, and it is determined whether the data is the top line of the block, the last line of the effective display area 104, or a line other than the above (step S107). And S108). Here, if the address data is the first line and not the last line, the process branches to the LINE routine. Here, line writing for one line is performed based on the transferred image data. Next, the Busy signal is set to "OFF" and an interrupt request is waited (step S109). Here, internal interrupt request ▲ ▼
If so, the BSTART routine is started again.

In step S108, the address data is displayed in the effective display area 104.
If it is the last line of, execution branches to the FLINE routine. Here, line writing for one line is performed. Next, the frame drive and the temperature compensation data are updated, and the Busy signal is turned “OFF”.
Wait for an interrupt request (step S110). Here, if there is an interrupt request ▲ ▼, the BSTART routine is started again.

In step S108, if the address data is the top line of the block, execution branches to the BLOCK routine. Here, all blocks to which the line specified by the address belongs are erased,
The area of this block is set to "white" (step S11).
1). Next, the process proceeds to the LINE routine (step S109), and the same processing as described above is performed. The display control in the block access mode is performed and the information is written in the procedure as described above.

In addition, the word processor main unit 1 outputs a power down signal ▲
When ▼ is sent to the control unit 500, a non-maskable interrupt request NMI is
Is started. Here, the Busy signal is set to “ON”, the effective display area 104 is erased, and all areas are set to “white”. Next, set the power status signal and Busy signal to “OF”.
F ", thereby turning off the power of the word processor 1 (step S112).

As is apparent from the above description, no matter which of the two forms of the display control, that is, the block access and the line access, is implemented, the address data is sequentially and periodically spread over the entire effective display area. In the case of continuous transfer, refresh drive is performed,
Further, if the address data of a predetermined portion is transferred intermittently, the partial rewriting drive is performed.

The details of the control procedure described below are described on the assumption that the address data and the image data are transferred from the main unit 1 in the refresh mode.

(5.2) Details of control procedure (5.2.1) Power-on (initial stage) When the power of the word processor 1 is turned on,
The automatically activated process will be described with reference to FIGS. 42 and 43.

FIG. 42 shows a flowchart of the processing to be started,
This is the INIT routine described above with reference to FIG. FIG. 43 shows a time chart of the INIT routine and the PWOFF routine described later.
The processing performed by 0 will be described.

S201: Power status (P ON / OFF signal is set to “ON” and signal Light is set to “OFF”, and at the same time via the data output unit 600
The Busy signal is turned on and output to the word processor main body 1. While the Busy signal is being output, no address data is transferred from the word processor 1. this is,
This is because one horizontal scanning period is changed depending on the temperature in order to effectively drive the FLC display element. That is, since the FLC display element drive time in the effective display area 104 and the data transfer time from the word processor body 1, that is, the VRAW operation time in the word processor body 1 cannot be completely synchronized, the display control device body The 50 side outputs a Busy signal for synchronization (Fig. 43, time point: only the numbers below).

S203: Set drive waveform generation control data for driving the initial frame portion and the effective display area in a predetermined area in the register unit 630 of the data output unit 600. This is ROM5 of the ROM in the control unit 500
The waveform generation control data stored in 03 is set in the register unit 630 of the data output unit 600 as shown in Tables 1 and 4.

S205: The drive voltage value for the initial frame drive and the system clock data that is the basis of one horizontal scan period are
It is set in the register TONR in the timer TMR2 of the A conversion unit 900 and the control unit 500. Also, basic time data for each of block access, line access, and block access at power-on / off is set.

S207: The control unit 500 transfers the frame drive control data from the data output unit 600 to the frame drive unit 700, and the frame drive unit 700 drives the frame based on this. By such driving, the image quality of the frame portion 106 is improved, and the display screen 102 is always kept in a favorable state. This is the frame 1 while driving the effective display area 104.
This is because a voltage is also applied to 06 so that the light transmittance changes and a part of the frame 106 does not become turbid and deterioration of image quality does not occur.

Further, in this example, the frame portion 106 is set to “white (the state of transmitting light from the light source FL)”, the effective display area 104 is set to “white (the state of transmitting light)”, and Are displayed in “black”. “Black” in these displays
And the definition by "white" is not limited to the above example,
The display in which “black” and “white” are reversed or the frame 106
A display for distinguishing between the effective display area 104 and the effective display area 104 is also possible by the device according to the present example.

The frame driving in step S207 is performed over one horizontal scanning period. During this period, in FIG.
Driving by applying a voltage signal to the frame transparent electrode 150 and the segment electrode 124 not provided on the lower glass substrate 120 and the frame transparent electrode 151 provided on the upper glass substrate 110 and parallel to the common electrode 114. I do. Therefore, the driving of the entire frame portion is not performed during this period, and the driving of the remaining frame portion (vertical frame) is performed by using the common electrode together when erasing the effective display area 104 described later in step S213. .

In this step, A / D
Conversion is performed. In such A / D conversion, ambient temperature information of the display screen 102 detected by the temperature sensor 400, that is, FLC temperature information is read by the A / D conversion unit 950 and converted into digital data (time point and).

S209: Perform temperature compensation. That is, the A / D conversion data obtained above is read, and the drive voltage V, the system clock, the delay data and the temperature compensated temperature are compensated by referring to the look-up table (FIG. 12) stored in the ROM 503 in the control unit 500. Respectively.

The above process will be described in detail below with reference to FIG. FIG. 44 shows the A / D conversion data, the drive voltage V, the system clock that is the basis of one horizontal scanning period, the algorithm for converting each delay time, and the look-up table. For example, FIG. It is assumed that temperature data 80H is obtained. This 80H indicates the lower bits of the address in the table, and the A / D
In the conversion, an operation is performed to convert analog temperature data into digital temperature data corresponding to the lower bits of the address.

Here, the arithmetic unit ALU of the control unit 500 uses the data 0080H.
E9 corresponding to the address upper bit data of the drive voltage data table area (D / A conversion unit related data area)
Offset 00H. As a result, the content of the index register IX is set to E980H, and data corresponding to this address is obtained. The temperature-compensated drive voltage value is output to the power supply controller 800 via the D / A converter 900. Next, the arithmetic unit ALU increments the upper bit data by 1 while keeping the lower bit data of the index register IX as it is, and sets the content to EA80H. This corresponds to the address of the system clock table in the table, thereby obtaining temperature-compensated data.
The system clock data which is the basis of this one horizontal scanning period is set in the time constant register TCONR of the timer TMR2.

By the same processing, each delay time data in block access, line access, and block access at power-on / off is set in the registers CNTB, CNTL, and CNTBB for the timer TMR1, respectively.

S211: The drive start time of the effective display area 104 is synchronized. That is, in order to completely synchronize the start of access on the program and the actual start of driving of the effective display area, when the rising edge of the clock output pulse Tout of the timer TMR2 of the control unit 500, for example, comes, the control unit 500 Apply the CPU's internal interrupt request IRQ3. Thus, the actual driving of the effective display area is started (time point).

S213: Erasure of the effective display area 104, that is, the entire area is “white” in this example. As a result, the display screen 102 at the time of power-on becomes good in combination with the above frame driving.

The effective display area 104 is erased by driving, for example, 20 scanning lines as one block for each block, and thus one block is erased in one horizontal scanning period.

This driving is not performed by receiving image data for setting the entire effective display area 104 to “white” from the word processor main body 1, and performing a predetermined block erasing waveform,
As described above, this is performed by automatically setting the program. This makes it possible to erase the effective display area during power on / off.

S215 1 Adjust the horizontal scanning period. That is, register CN
The TBB delay data is set in the counter, and based on this data, the timer TMR1 counts its own clock pulse. Thereby, one horizontal scanning period between the effective display area 104 and the program execution time is adjusted, and an internal interrupt request IRQ3 is generated when a predetermined time comes.

That is, the timer TMR1 sets a predetermined time from the basic time data set in step S205 and the delay time data by temperature compensation obtained in step S209,
When the time taken from a certain appropriate time is counted, an internal interrupt request is generated.

S216: The above steps S211, S213, and S215 are performed for each block, that is, for each horizontal scan. Therefore, in this step, it is determined whether or not all blocks in the effective display area 104 have been completed. If the determination is negative, the process returns to step S211 again, and the above processing is repeated until all blocks have been completed (time).

S217: If it is determined in step S216 that all blocks (valid display areas) have been completed, the Busy signal is set to “OFF”, and the signal D can be transferred from the word processor body 1. At the same time, the signal Light is turned “ON”. At this time, the operator of the word processor main body 1 feels that the power is turned on by displaying the display screen 102 after turning on the power of the main body 1. The processing in steps S201 to S215, particularly the driving of the frame 106 of the display screen 102 and the effective display area 104, is already performed as the initial display control (time point).

S219: Wait for an interrupt request ▲ ▼ or ▲ ▼. These ▼ and ▼ are generated when the address data is transferred from the word processor main body 1, and by this, execution of each program described later is started. Therefore, the standby program is executed until the address data is transferred, and the common line and the segment line are held at the same potential.
Or set to ground. At this time, the display screen 102 remains stopped. Alternatively, the power supply to the display device 100 may be stopped, for example, the power supply to the power supply controller 800 itself may be cut off to turn off the generation of the voltage signal.

By the way, as mentioned above, ▲ ▼ or ▲
Which of the interrupt requests ▼ is generated is preset, and these settings are arbitrarily made by the operator according to the usage pattern of the word processor operator, data handled by the word processor, and the like.

(5.2.2) Block access Regarding the block access display control activated by the interrupt request ▲ ▼ after the above-mentioned predetermined initial control (INIT routine), FIG. 45 (A) to (D), 48
A description will be given with reference to FIGS.

45 (A) to (D) show the ROM of the control unit 500, respectively.
FIG. 503 is a flowchart of a display control program stored in the form shown in FIG. 12, which is activated at each stage of block access display control.

48 (A) and 48 (B) are time charts of such display control.

When the Busy signal is set to “OFF” (time point in FIG. 48: only the numbers will be described below), the control unit 500 in the standby state causes the interrupt request ▲ ▼ generated when the address data is transferred (time point). The BSTART routine shown in FIG. 45 (A) is started (time) by input (time). The display control in the BSTART routine will be described below with reference to FIG.

S301: Read address data. The address data RA / D transferred to the data output unit 600 is read into the control unit 500.

S303: Based on the read address data, the address conversion as described in the above (4.3.2) is performed, and the address of the program to be executed is set with reference to the jumping table shown in FIG.

S305: The Busy signal is set to “ON” (time), and the next address data transfer is rejected.

S307: Execution branches to the program at the address set in step S303 (time). Where address data RA / D
Is the start line address of the block, and to the BLOCK routine, if it is the last line address of the effective display area, FL
If the address is other than the above, execution branches to the INE routine.

When the BLOCK routine shown in FIG. 45 (B) is started, the following processing is performed.

S309: Perform address conversion and setting. That is, the address data RA / D transferred to the registers RA / DL and RA / DU in the register section 630 of the data output section 600 are read, and based on the address data, the address data RA / D is written as described in (4.3.3) above. Next, address conversion for selecting a line to be driven is performed. The converted address is referred to the line table shown in FIG. 12 to obtain such address data. This data is stored in the register in the register section 630 of the data output section 600.
Set to DL L and DL U.

S311: The drive mode is block access. That is, data indicating block erase in the block access mode is set in the register DM in the register section 630 of the data output section 600.

S313: Synchronize the operation start time. That is, as described above, in order to completely synchronize the operation timing between the effective display area 104 and the program execution, the timer TMR2 of the control unit 500 is used.
Waits for, for example, a rising edge of the clock output pulse Tout of the device, and generates an internal interrupt request IRQ3 when such an edge occurs. This synchronizes the output pulse Tout with the program execution timing, and thus the output pulse
Since Tout is the basis of one horizontal scanning period and operation timing in the effective display area 104, the program execution and the operation timing of the effective display area 104 can be synchronized.

S315: Adjust the time until the end of image data transfer. That is, as shown in the time chart of FIG. 48 (A), the image data transfer is performed immediately after the address data transfer, and the access to the effective display area 104 is started after this transfer end (time point).

Here, the image data transfer time means that if, for example, 800 bits of image data for one scan are transferred from the word processor body 1 in parallel at 4 MHz at 5 MHz, the transfer is 40 μsec, and in addition, the image data is transferred to the segment side. The time stored in the drive unit 200 is adjusted.

By the way, this routine BLOCK is mainly for block erasing, and although the block erasing does not require image data, it is the line This is because the data transfer for access is performed. Alternatively, the program may not be executed for an equivalent time without transferring the image data.

S317: Start block erase (time point). Thereby, one block, that is, for example, 20 scanning lines is accessed in one horizontal scanning period (1H), and such a block is set to all “white”. As described above, these driving operations are performed not by receiving all “white” image data but by setting a predetermined block erase waveform.

Further, as is clear from FIG. 48 (A), in the effective display area 104, at the time point (time point) at which this block erase is started,
Either the last line writing of the previous block has been completed or the vertical blanking period has ended.

S319: Perform the program adjustment for one horizontal scanning period. That is, as described above, since the access time in the effective display area 104 is designed to change with the temperature change of the FLC display element, the length of one horizontal scanning period in these effective display areas 104 is long. The program execution time is adjusted accordingly.

As a specific method, the timer TMR1 in the control unit 500 and a clock which it owns, for example, measures the time from the time (time point) when the program is started after the address data is transferred, and the control unit is operated when a predetermined time has passed. CPU 501 in 500
The internal interrupt request IRO3 is generated and the program is branched to the next program routine.

Here, as to how to determine the required time, as described in step S209 of (5.2.1) above, the table area CNTB shown in FIG. 12 is obtained by combining the program execution time and the delay time by temperature compensation. Is stored as count number data, and the timer TMR1 compares the count number of its own clock with the contents of CNTB, and when it counts a predetermined value, generates an internal interrupt request IRQ3. .

When a predetermined time has elapsed, the program execution branches to the LINE routine due to the occurrence of IRQ3 (time).

FIG. 45 (C) shows a flowchart of the LINE routine, and this routine is a continuation of the BLOCK routine.
Alternatively, it is started as a continuation of the DC BSTART routine. In the following, description will be made as a continuation of the BLOCK routine, and in the description of each step, detailed description of the same processing as described above will be omitted.

S321: When the LINE routine is started by IRQ3 (at the time), address conversion and setting are performed.

S323: The drive mode is set to block access mode line writing. That is, data indicating this is set in the register DM in the register section 630 of the data output section 600.

S325: Synchronize the operation start time.

S327: Adjust the time until the end of image data transfer. Here, if the image data has been transferred in the previous BLOCK routine, there is no need to perform the data transfer, and the equivalent time in the program may be passed without execution.

S329: Start line access (time). At this point, block erasing ends. Based on the transferred image data for one scanning line, writing or displaying of information for one scanning line of the block leading line is performed.

S331: 1 Adjust horizontal scanning time (time point).

Interrupt request with S333, S335 Busy set to "OFF" (time)
Wait for ▼ to come, during which time the program will not be executed.

When the address data is transferred (time), an interrupt request ▼ is generated (time), and the BSTART routine is started (time). Thereafter, the LINE routine is executed after the BSTART routine, and writing of the second scan line of the block is performed. As described above, by repeatedly executing the BSTART routine and the LINE routine, the writing of the scanning lines of all the blocks is completed, and the next block is erased and the lines are written.

When the address data indicating the last line of the effective display area 104 is transferred through the above processing, the processing shown in the flowchart of FIG. 45 (D) and the time chart of FIG. 48 (B) is activated. To be done.

That is, when the address data indicating that it is the last line of the effective display area 104 is transferred (FIG. 48 (B)).
At the time of: Only the numbers below are indicated), interrupt request ▲
▼ occurs (time), and the BSTART routine described above is started (time). Here, since the address data indicates the last line of the effective display area 104, after this routine, the FLINE routine shown in FIG. 45 (D) is activated (time point).

Hereinafter, each step of the FLINE routine will be described mainly with reference to FIG. 45 (D) and FIG. 48 (B). The detailed description of the same processing as described above is omitted.

S336, S337, S339, S341, S343: Set Busy to "ON" to perform address conversion and setting.
The drive mode is set to the line write in the block access mode, and the operation start time is synchronized. Further, time adjustment until the end of image data transfer is performed.

S345: Start writing the last line (time point). At this point, the writing of the second to last line in the effective display area 104 is completed.

S347: It is determined whether or not the last line writing in the effective display area 104 has been completed. If completed, the process proceeds to the next step S349. This determination is made only when the last line of the effective display area 104 is accessed. In the case of other access, only the access start time is monitored.

S439: In this step, the waveform control data for the frame driving performed in the next step is transferred to the register unit 630 of the data output unit 600.
Set to to update the data. It is also possible to drive the frame without updating the data by independently setting the frame drive system and the like.

Incidentally, in the INIT routine shown in FIG. 42 or the like or already described, the frame drive voltage value is set together with the waveform data setting, but it is performed in the vertical blanking period as in this step. In the frame drive, the drive voltage value obtained by temperature compensation in the INIT routine is used as a reference.

S351, S353 Start driving the frame 106 and A / D conversion (time point). From this point, the vertical retrace period begins. At the same time as the end of A / D conversion, a drive voltage value, a system clock, and delay time data are obtained based on the A / D converted temperature data.
That is, the temperature compensation data is updated.

In the frame driving in step S351, only a part (horizontal frame) of the frame 106 is driven to be all “white”, and the remaining portion (vertical frame) is not displayed in the effective display area to be performed later.
It is already described in the description of the INIT routine that the operation is performed in parallel with the operation of 104. However, the drive system of these frames 106 is changed to the effective display area 1
If it is independent of the drive system of 04, it is possible to drive the frame 106 at once.

In addition, the frame 106 is formed by performing electric driving to improve the image quality outside the effective display area 104. However, the frame 106 may be covered mechanically or by painting. Accordingly, it is needless to say that the image quality outside the effective display area 104 may not be considered.

S355, S357: Set the Busy signal to "OFF" to request an interrupt ▲ ▼
Wait for (time).

As described above, writing of the last scanning line in the effective display area 104, frame driving in the vertical blanking period immediately after that, and temperature compensation are performed.

After that, the address data, that is, the effective display area 104
When the address data of the uppermost scanning line is transferred (time), an interrupt request ▲ is generated (time), and the execution of the BSTART routine is started (time).
Thereafter, erasing and line writing are performed sequentially for each block.

(5.2.3) Line Access On the other hand, the line access display control activated by the interrupt request ▲ ▼ after the above-mentioned predetermined initial control (INIT routine) is shown in FIG.
This will be described with reference to (L) and FIGS. 49 (A) to (D).

46 (A) to (L) respectively show the ROM 50 of the control unit 500.
3 is a flowchart of a display control program stored in the form shown in FIG. 12, which is activated at each stage of line access display control.

FIGS. 49 (A) to (D) show time charts of such display control.

The main difference between the line access of the present embodiment and the previous block access is that there is no block erasure, and information is updated for each scan line, that is, display is performed without erasing scan lines or the like in advance. is there. Further, line writing in line access is performed line by line, frame by frame, and by inverting the polarity of the drive waveform within one horizontal scanning period. Hereinafter, the same processing as that in the above block access display control will be described by omitting the detailed description.

When the Busy signal is set to “OFF” (time point in FIG. 49 (A) or (C): only the numbers are shown below), the control unit 500 in the standby state is caused by the address data being transferred (time point). Interrupt request ▲ ▼
Depending on (time point), the LSTR0 routine shown in FIG. 46 (A) is started (time point). This LSTR0 routine is either LSTRA0 corresponding to the A waveform, LSTRN0 corresponding to the N waveform, or LSTRC0 corresponding to the C waveform, and is selected according to the temperature of the FLC as described above. Among them, in the FLC driving executed by the LSTRA0 and LSTRC0 routines and thereafter, the drive waveform is inverted in polarity within one horizontal scanning period, and the A waveform or the C waveform is formed depending on the inverted waveform, the normal waveform, and the drive pause period therebetween.

In the following description, the letters A, N or C inserted in the routine name corresponding to the waveform may be omitted.

The display control in the LSTR0 routine will be described below with reference to FIG.

S401: Read address data.

S402: It is determined whether the read address data is for the last scanning line of the effective display area 104. If it is the data of the final scanning line, branch to the FLLN0 routine of step S404,
If it is other data, it branches to the LLN0 routine.

The display control related to the LLN0 routine is described below.
0 or LLNC0 Fig. 46 (C) and 49
This will be described with reference to FIG.

S410, S411, S413: The Busy signal is set to "ON" (time point) to perform address conversion and setting. The drive mode is set to line access.

S414, S415: Synchronize the operation start time and adjust the time until the end of the image data transfer.

S416: Here, the inverted waveform of the first half is set. That is, the inverted waveform data of the A waveform or the C waveform in the common line drive is used as the content of the register.

S417: By outputting the waveform data of the register REG2 to the registers CC1 and 2, SC1 and 2 of the data output unit 600,
The line access by the inverted waveform in the first half of one horizontal scanning period is started (time point).

S418: Time adjustment for one horizontal scanning period is performed (time point). Here, a drive suspension period set between the line access with the inverted waveform in the first half of one horizontal scanning period and the line access with the normal waveform in the latter half to be described later is formed. This is performed using the delay time data of the registers CNTB and CNTL of the timer TMR1, and in this example, the pause period is formed using the delay time data of one CNTB and four CNTL.

S419, S421, S422, S423: Here, the same processing as the above-described steps S411, S413, S414, S415 is executed, but the time adjustment processing of step S423, since the data transfer has already been completed, the processing of step S415 No execution for the same time as.

S424: Similar to the process of step S416, the normal waveform of the latter half is set here. That is, A waveform or C
The normal waveform data of the waveform is the content of register REG2.

S425: Similar to the process of step S417, line access by the normal waveform in the latter half of one horizontal scanning period is started (time point).

By the processing of step S417 and this step, writing by the composite waveform is performed in either the first half or the second half of the pause portion of one horizontal scanning period.

S426: Wait for a predetermined time for adjusting one horizontal scanning period, and when the internal interrupt request IRQ3 is generated (time point), restart the program and execute LINVA0 or LINVC0
Go to routine.

Hereinafter, referring to FIG. 46 (I) and FIG. 49 (A), LI
The NVA0 and LINVC0 routines will be described.

S430, S431: Set the Busy signal to “OFF” (time point), interrupt request ▲
Wait for ▼.

S432, S433, S434: When the address data is transferred (time point) and the interrupt request ▲ ▼ is generated (time point), it is determined whether the line counter LCNT is 0 or not.
The process proceeds to S433, resets the line counter LCNT, and proceeds to the LSTRA1 or LSTRC1 routine.

When a negative decision is made, the operation proceeds to step S434, in which the content of the line counter LCNT is decremented by 1 and LSTRA0 or LSTR.
Return to C0.

When it is determined in step S402 of the LSTR0 routine that the transferred address data is for the last scan line of the effective display area 104, the process branches to the ELLN0 routine.

Hereinafter, referring to FIG. 46 (E) and FIG. 49 (B),
The display control of the FLLN0 routine will be described.

S440, S441, S443: The Busy signal is turned "ON" (at the time of FIG. 49 (B): Only the numbers are shown below), and address conversion and setting are performed. Also,
Line access the drive mode.

S444, S445: Synchronize the operation start time and adjust the time until the end of image data transfer.

S446: The inverted waveform of the first half is set in the same manner as in step S416 described above.

S447: Similar to step S417 described above, line access by the inverted waveform in the first half of one horizontal scanning period is started (time point).

S448: Adjust the time for one horizontal scanning period (time point). Here, in step S418, the drive suspension period is formed as described above.

S449, S451, S452, S453: The same processing as the above-described steps S441, S443, S444, S445 is executed, but the time adjustment processing of step S453 is equivalent to the processing of step S445 because the data transfer has already been completed. No time is spent.

S454: Similar to the process of step S446, the normal waveform of the latter half is set here.

S445: Similar to the process of step S447, line access by the normal waveform in the latter half of one horizontal scanning period is started (time point).

S456: It is determined whether or not the writing of the last line of the effective display area 104 is completed. If finished, go to the next step S457.
Proceed to.

S457: In this step, the waveform control data for frame drive performed in the next step is set.

S458, S459: Driving the frame 106 and starting A / D conversion (time point). At this point, the writing of the last scanning line of the effective display area 104 is completed. At the same time as the end of A / D conversion, the temperature compensation data is updated.

When the process of step S459 ends, the program execution is FI
Go to NVA0 or FINVC0 routine.

Hereinafter, referring to FIG. 46 (K) and FIG. 49 (B), FI
The NVA0 or FINVC0 routine will be described.

S460, S461: Set Busy signal to "OFF" to request interrupt ▲ ▼
Wait for (time).

S462: When the address data is transferred (time point) and the interrupt request ▲ ▼ is generated (time point), it is determined whether to change the control routine. That is, the contents of the waveform recognition register CX are calculated based on the temperature data of the temperature compensation performed after the last scan line access, and the contents are compared with the contents of CX up to now. If different in this comparison, the process returns to step S104 described above in FIG. 41 to change the control routine,
In step S105, one of the routines corresponding to the new waveform is selected. If they are not different, the process proceeds to step S463.

In this way, in the FLC display control by line access, F
When the temperature range of LC has been changed when it was detected, the drive waveform is changed to perform more appropriate display control.

S463, S464, S465: Here, it is determined whether or not the frame counter TCNT is 0. If the determination is affirmative, the process proceeds to step S464, the frame counter and the line counter are reset, and the process proceeds to the LSTR1 routine.

The LSTR1 routine and its subsequent routines are almost the same as the LSTR0 routine and its subsequent routines, which have been described so far and are generally shown in FIG. 46 (A), as shown in FIG. 46 (B) in its entirety. It is the same routine, but the difference is that the line access by the LSTR0 routine accesses the first half of the line access with the inverted waveform and the latter half with the normal waveform, whereas it accesses the first half with the normal waveform and the latter half with the inverted waveform. is there. The routines LLN1, FLLN1, LINV1 and FINV1 that follow the LSTR1 routine are shown in FIGS. 46 (G), 46 (H), 46 (J) and 46.
Each is shown in FIG.

From the above, for example, the frame counter FCNT
If the value of the line counter LCNT is set to 1 and the value of the line counter LCNT is set to 1, the scanning line to be accessed first is written in the first half of one horizontal scanning period. Is written in the first half,
Thereafter, writing is sequentially and alternately performed in the first half or the second half to reach the final scanning line. Then, in the next cycle, the scan lines written in the first half in the previous cycle are written in the second half, and the scan lines written in the second half in the previous cycle are written in the first half.

In the line access with the N waveform, the polarity of the waveform is not inverted within one horizontal scanning period. However, as described above, by appropriately setting the values of the frame counter FCNT and the line counter LCNT, the polarity inversion of the waveform is performed for each frame and line according to the values.

Display control relating to the N waveform will be described below with reference to FIGS. 46 (D) and (F) and FIGS. 49 (C) and (D). The routines different from the routines described so far are LLNN0 and 1 and FLLNN0 and FLLNN1, and the LLNN0 and 1 routines are S470, S471, S474, S475: These processes are similar to those described above, ie The Busy signal is turned "ON" (time point), and address conversion and setting are performed. Next, the drive mode is set to line access, and the operation start time is synchronized. Also, the time until the end of image data transfer is adjusted.

S475-1: Set the waveform here. That is, the N waveform data is the content of the register. However, the waveform data set in the LLNN0 routine is normal waveform data,
In the LLNN1 routine, it is inverted waveform data.

S476: Register waveform data in register C of data output unit 600
By outputting to C1 and 2, SC1 and 2, line access with a normal waveform or an inverted waveform is started (time point).

S477: One horizontal scanning period is adjusted.

After the processing described above, program execution proceeds to the LINVN0 or LINVN1 routine. These routines are described above
Since it is the same as LINVA0 or LINVA1, its explanation is omitted.

By the above routine, the N waveform of one line is accessed, and when the line access is repeated to reach the final line, the FLLNN0 or FLLNN1 routine is started.

The routine will be described below with reference to FIGS. 46 (F) and 49 (D).

S480, S481, S483, S484, S485: These processes are the same as those described above, that is, the Busy signal is turned "ON" (time point), and address conversion and setting are performed. Next, the drive mode is set to line access, and the operation start point is synchronized. Also, the time until the end of image data transfer is adjusted.

S485-1: In step S475-1, set the waveform in the same manner as described above. However, the waveform data set in the FLLNN0 routine is normal waveform data, and the inverted waveform data in the FLLNN1 routine.

S486: In the same manner as described above in step S476, line access with a normal waveform or an inverted waveform is started (time point).

S487, S488, S489, S490: In these steps, first, it is judged whether or not the writing of the last line of the effective display area 104 is finished, and when it is finished, the waveform control data for driving the frame is set in the next step. .

Next, driving of the frame 106 and A / D conversion are started (time point). Simultaneously with the end of A / D conversion, the temperature compensation data is updated and the process proceeds to the FINVN0 or FINVN1 routine.

The FINVN0 and FINV1 routines are shown in Fig. 46 (K) and 4
Since it is the same as the routine described above with reference to FIG. 6 (L), its explanation is omitted.

(5.2.4) Power Off If the operator of the word processor 1 performs an operation of turning off the power using a key or the like, at this time, a PWOFF routine related to display control when the power is turned off is started.

The display control will be described below with reference to the time chart shown in FIG. 43 and the flowchart shown in FIG.

When the operator operates a key or the like to turn off the power, the word processor main body 1 sends a signal to the control unit 500.
▼ A signal is sent, which causes the CPU 501 of the control unit 500.
To non-maskable interrupt request NMI, PWOFF
The routine is invoked. This interrupt request NMI is an unconditional interrupt, and the following process is immediately started regardless of what process the control unit 500 is performing. That is, the S501: Busy signal is turned "ON", and at the same time, the Light signal is turned "OFF" (at the time of Fig. 43: only the numbers below are shown).

S503: Synchronize the operation start time. This is the same processing as described.

S505: Driving of the effective display area 104 is started (time point). This drive erases one block of the effective display area 104 in one horizontal scanning period as in the INIT routine. With this driving, the entire area of the area 104 is set to “white”, and the image quality is improved to prepare for the next display.

S507: One horizontal scanning period is adjusted. This processing is also the same as that described above.

S509: Since the above steps S503, S505 and S507 are performed every time one block is erased, in this step, it is determined whether or not all the blocks, that is, all the erasure of the effective display area 104 have been completed. .

S511: When it is determined that the processing has been completed in step S509 (time), the power status (P ON / OFF) signal is set to “OFF”, and the Busy signal is also set to “OFF” (time). Above P
The word processor itself 1 by the "OFF" of the ON / OFF signal
The power supply of the entire display device including is shut off (time point).

(6) Effects of Examples According to the above examples, the following effects can be obtained.

(6.1) Effect of Forming Frame When a display device is configured with FLC elements, by providing the frame portion 106 outside the effective display area 104 on the display screen 102, the FLC element corresponding to the area outside the effective area 104 can be formed. Not only is it possible to prevent the appearance of the display screen 102 from being deteriorated due to the unstable state, but it is also possible to prevent the effective display area 104 from being clearly displayed and prevent the scanner from giving an illusion.

In particular, when the frame electrodes are arranged corresponding to the frame portion 106 and the frame is electrically formed as in this example, the display screen 10
The mechanical arrangement position is compared with the case where the effective display area 104 is mechanically divided by placing a mechanical member such as metal or plastic as a frame on 2 or painting it. Is unnecessary, and a blind spot that may occur due to the mounting of the mechanical member does not occur depending on the handling position of the display device. Further, the flexibility in forming the frame is improved, for example, the frame can be formed in the same color or a different color from the background color of the display data on the effective display area 104.

(6.2) Effect of temperature compensation Since the driving energy (voltage and pulse width) of the FLC element corresponding to the effective display area 104 and the frame portion 106 is compensated according to the temperature immediately before the writing timing, the temperature condition is not affected. Therefore, stable driving is possible, and the display reliability of the display device using the FLC element can be improved.

In particular, as in this example, by performing the update of the compensation data during the vertical blanking period, it is possible to perform a highly efficient display process, and the horizontal direction according to the temperature data detection command, that is, the drive command of the A / D converter 950 Since the frame is also driven, the display processing efficiency can be further improved.

(6.3) Effect of control in response to image data input A means is provided to wait for input of image data from the host device, and operation is started in response to the input, so that display without memory is displayed. Similar to the display using the element, continuous refresh driving can be performed regardless of whether or not the display content is changed, and the display data is updated only when the display content is changed. Discontinuous driving is also possible. As a result of the refresh driving, almost no specification update of the existing host device is required. As a result of enabling discontinuous driving,
It is possible to reduce the power consumption, and it is sufficient for the host device to send the data only when the screen needs to be updated. Therefore, the load on the software or hardware on the host side can be reduced.

Since the busy signal is transmitted to the host device in response to the input of one unit (for example, one line) of image data, various settings can be performed thereafter. In this case, it is sufficient to add a function of receiving a busy signal and waiting for transfer of image data to the host device.

Further, in this example, the operation should be started / stopped according to the presence / absence of input of real address data supplied in addition to image data from the word processor main body 1 as a host device, and access should be made based on the real address data. Recognition of a block or a line enables partial rewriting, and furthermore, updating of temperature compensation data at the time of refresh driving becomes possible during a vertical blanking period.

(6.4) Effect of disposing display drive unit The electrodes (common co) provided on the display 100 composed of FLC elements
m, segment line seg, frame common line Fcom, frame segment line Fesg) is provided with a plurality of voltage supply lines and switches for connecting / disconnecting the respective supply lines and electrodes, and waveforms for switching settings Since the means (common side driving section 300, segment side driving section 200, frame driving section 700) for performing supply of data is provided, the electrodes can be appropriately driven with various driving waveforms depending on the content of the waveform data.

Further, in the embodiment, since the waveform data can be appropriately changed and supplied in the process of control, it becomes possible to drive the block erasing, the image forming, the frame forming, the screen clearing and the like with an appropriate waveform. Can be improved.

(6.5) Effect of forcibly clearing the screen Since the display screen 102 of the display unit 100 composed of FLC elements is cleared when the power is turned on and off, the display screen 102 can be made clear by looking at the display screen 102. You will be able to easily recognize when power is turned on or when power is turned off.

In particular, in the embodiment, when the power is turned on / off, the clearing can be performed by itself without receiving the supply of clearing data (for example, all white data) from the host device side. Higher speed of clearing can be achieved.

Also, the configuration that allows you to clear the screen yourself,
For example, when clearing the screen during operation, it is also effective to apply control not to receive all-white data from the host device but merely to receive a command to that effect and to clear itself in response to this command.

(6.6) Effect of arranging power supply controller Electrodes (line co
m, seg, Fcom, Fseg) can be changed, so that an optimal voltage can be supplied to the electrode according to the temperature condition and the driving condition.

In particular, in the embodiment, the ternary voltage of +,-and the reference potential can be applied to the common side lines com and Fcom, and the ternary voltage can be similarly applied to the segment side lines seg and Fseg. , A total of five different voltages can be generated. Also, by fixing one value (VC) and setting the relative ratio of other values in advance, and by making some output voltages to be used to determine other output voltages, Since a total of five values of voltage can be generated according to the change of the output voltage of, the adjustment of the appropriate voltage value according to the temperature condition and the like becomes easy.

In addition, while the IC used for the common side drive element is required to have a high withstand voltage, the IC used for the segment side drive element is required to have a high operating speed, but one voltage is fixed as in this example. Then, if the voltage is changed while maintaining the relative ratio to it, the specifications of both can be unified and the manufacturing process can be simplified.

(6.7) Effect of waveform change and inversion drive In the line access mode, the temperature range that is normally used is divided, and the appropriate drive waveform is specified in each divided temperature range, and also for each drive waveform. Since the pulse width and the voltage are adjusted according to the temperature, the operating characteristics can be averaged.

Further, as a result of performing the in-line inversion, the total drive energy in one line can be set to 0, so that the stable state of the FLC element can be secured.

Further, as a result of performing the MH inversion, one line or several lines adjacent to each other are driven in opposite phases, and it is possible to prevent the scanner from feeling undulations on the display screen.

In addition, as a result of performing the frame inversion, the timing at which the data of the same color is written is deviated at the intersection of the common line and the segment line. For example, comparing FIG. 31 (A) with FIG. 33 (A), white data is written in the first middle half of the former and in the latter half of the latter, and segm + com n-1 in FIG. Focusing on the point, white data is written in the first half of the first floor and in the second half of the second floor. As a result, the threshold characteristic of the FLC element when written in the first half and the threshold characteristic when written in the latter half are combined, and V
The operating point on the −ΔT curve expands, and a margin is obtained.

(7) Modification (7.1) Configuration of Frame 106 In the embodiment, the frame 106 is formed electrically. However, the present invention is not limited to this.
It is also possible to cover the portion corresponding to the second frame 106 with a mechanical means such as plastic or by coating or the like so that the image quality of the portion outside the effective evaluation area 104 is not considered. Further, even when the frame is driven by electric drive, if the frame drive system is provided independently, the frame can be driven at once. Further, when the frame is formed by electric driving, the frame may be formed not only in the same color as the background color as in the above example but also in the same color as the data color.

Furthermore, in the above example, the frame transparent electrodes 150 and 151 are connected to the drive units 200 and 3
Although the drive is performed by the frame drive unit 700 provided independently of 00, the same or the same drive element as the elements 210 and 310 is provided for both or either of them, as a part of the drive control of the drive units 200 and 300. Drive control may be performed.

(7.2) Timing of Temperature Compensation and Partial Rewriting In the above embodiment, the temperature compensation was performed during the vertical blanking period. This was possible because it was premised that the address data and the image data were transferred periodically and continuously (in the refresh mode). However, the timing of the temperature compensation is not limited to the above example and can be set at an appropriate time, for example, the address data of a specific portion is intermittently (in the partial rewriting mode).
In the case of transfer, there is no vertical blanking period, and thus the temperature compensation is not performed in the display control in the above example,
The display control may be improper.

Therefore, when driving in the partial rewrite mode,
It is desirable to perform temperature compensation in a fixed cycle. For this purpose, for example, the clock may be measured by a timer included in the control unit 500, an internal interrupt request may be made at a fixed period, and the Busy signal may be turned “ON” to perform temperature compensation.

In order to enable driving in the partial rewrite mode, in addition to the function of the word processor in the above embodiment,
It may have a function of transferring address data and image data of a specific portion. Alternatively, even when the address data is transferred in the refresh mode as in the above-described embodiment, it is possible to adopt a configuration in which whether or not to activate the display control is determined based on the presence or absence of image data after the address data.

Further, the temperature compensation may be performed by an appropriate calculation without using the table method as in the above example.

(7.3) One horizontal scanning period and driving voltage value The relationship between the temperature range as shown in FIG. 9 and the corresponding frequency (ie, one horizontal scanning period) and driving voltage value is not limited to this. For example, if the temperature range is made narrower and the frequency and the drive voltage value are set appropriately in response to this, fine temperature compensation can be performed.

(7.4) Waveform setting In the above embodiment, in the block access mode,
When the waveform data for image formation is set once in the register 630, the waveform data was not updated. However, even with the device configuration of the above example, the waveform and waveform are not updated at an appropriate stage of display control.
It is obvious that the control data of 1H division number can be updated. Thereby, drive waveforms corresponding to various drive conditions can be generated.

Also in the block access mode, it is possible not only to select the waveform data according to the driving condition as in the above example but also to change the waveform data according to the temperature so as to obtain an appropriate waveform. In this case, for example, in the area EAOOH-in FIG. 12, EEOOH-regular data corresponding to the temperature is stored in the same manner as other setting data,
The waveform data may be changed and set in the same manner as the above-mentioned line access mode. In addition, the apparatus can be used to determine the optimum waveform by allowing the waveform data to be arbitrarily changed.

Further, in the above example, the change of the waveform data is set by the program used according to the temperature, but it may be set by the reading using the jumping table.

In addition, in the above example, 1H
^Although the quiescent period of ^* is provided, an appropriate time can be set for this quiescent period, and when such a quiescent period is not provided, the normal waveform and the inverted waveform are fused to generate a new waveform. be able to. For example, in the example of FIG. 34 (A), if the pause period is not provided, the first 2ΔT period
It is possible to generate a waveform that takes V1, V2 in the next 3ΔT period, and V1 in the last 1ΔT. That is, the arbitrary waveforms can be combined to generate another arbitrary waveform having different optical response. In addition, it goes without saying that the drive waveform is not limited to the above example, and an arbitrary waveform can be set even for the one including in-line inversion.

(7.5) Selection of block access or line access Selection of block access or line access, that is, an interrupt request ▲ ▼ or ▲ ▼
Is selected by the operator in the above embodiment in accordance with the usage form and the form of data to be written. This means that, for example, if the size of one block on the display screen 102 corresponds to the size of the character string to be displayed, and if the data to be written is only characters, numbers, etc., Block access is effective because it can be handled.

On the other hand, if the displayed image is a symbol, a graphic pattern, or the like having various different sizes, the display or rewriting must be performed beyond the size of the block, so that the line access becomes more appropriate. .

(7.6) Number of Scanning Lines In the above embodiment, the number of scanning lines per block was set to 20 and the entire effective display area was set to 400. However, the present invention is not limited to this. However, since the selection time / line cannot be reduced by increasing the number of scanning lines, it is possible to increase the number of scanning lines to achieve a higher definition and larger screen.

(7.7) Deleting the effective display area 104 In order to initialize the display screen, the effective display area 104
Was erased automatically when the power was turned on / off, that is, without receiving all "white" data from the word processor body 1. However, it is a matter of course that the screen clearing may be performed either on or off. Also, in the display control of block access and line access,
When it becomes necessary to erase the entire effective display area, the erase can be performed regardless of the transferred data.

Therefore, for example, a control signal such as an unconditional interrupt may be transmitted by operating a key or the like of the word processor main body 1, so that the control section 500 erases the effective display area 104.

(7.8) Position of the temperature sensor 400 The temperature sensor 400 is appropriately disposed at a position representative of the distribution temperature based on the FLC temperature distribution obtained in advance through experiments or the like. In order to improve the accuracy, a plurality of temperature sensors may be used.

(7.9) Display 100, display control device 50, and word processor main unit 1 The form of signals transmitted and received between word processor main unit 1 and control device 50, for example, signal D (including signal A /, image data, and real address data The form of ()) is not limited to the above example, and may be an appropriate form.

Further, in the above embodiment, the display and the display control system according to the word processor have been described as examples, but the present invention is not limited to the above example, and it is needless to say that the present invention can be applied to a display or a television of a computer terminal. is there.

Further, as a device that effectively utilizes the property that the FLC display element has memory, a display device using a larger screen than is conceivable in an existing television is also possible.

Furthermore, the present invention is effective when applied to the case of displaying a still image or an image whose screen update frequency is relatively low. For example, when the present invention is applied to a receiver such as a text broadcast or an information service, or a display device such as a clock face or a 7-segment display in a message display unit of various devices, the drive may be performed when a screen change occurs. Therefore, it is a large process that contributes to power saving.

In these cases, all screens may be updated when the screen is changed, or when there is a partial change, only that part may be updated in the same manner as the partial rewriting described above. Further, in these cases, the temperature compensation may be performed by a periodic interrupt, and thus the screen to be updated next will have been subjected to the drive correction. In the case where the screen updating cycle is long or in the case of a device that performs partial rewriting, when temperature compensation is performed, the entire data being displayed at that time may be re-output and rewritten from, for example, VRAM or the like. According to this, it is possible to always maintain a uniform and good display state over the entire screen.

[Effects of the Invention] As described above, according to the present invention, means for adding a certain drive waveform to the scan electrode and a waveform obtained by inverting the drive waveform is provided. Therefore, in-line inversion, MH inversion, or Frame inversion becomes possible, so that the optical modulator such as the FLC element is in a stable state or in a good display state, or V-ΔT.
The expansion of the operating point on the curve can be secured. As a result, when a display device is constructed using an FLC element having bistability with respect to an electric field, appropriate drive control can be performed while effectively utilizing the characteristics.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of a display device and a control system according to an embodiment of the present invention. FIGS. 2 and 3 are exploded views showing an example of a configuration of a display according to the embodiment. FIG. 4 is a diagram for explaining the relationship between the drive voltage and the application time, and FIGS. 5 (A), (B) and 6 illustrate the drive waveform of the FLC element. 7 (A) and (B) are diagrams showing the relationship between the drive voltage and the transmittance of the FLC element, and FIG. 8 is a diagram showing the relationship between the temperature of the FLC element and the drive voltage. FIG. 9 is a diagram illustrating an example of a relationship between temperature, drive voltage, and frequency stored as data in a storage area of a control unit according to the present embodiment, and FIG. 10 is an effective diagram according to the present embodiment. FIG. 11 is an explanatory diagram showing block divisions of a display area. FIG. 11 is a block diagram showing one configuration example of a control unit according to the present embodiment. FIG. 12 is a diagram showing an example of a configuration of a memory space in the control unit shown in FIG. 11, FIG. 13 is an explanatory diagram for explaining address conversion according to the present embodiment, and FIG. FIG. 15 is an explanatory diagram showing an example of correspondence between line numbers and jumping tables, FIG. 15 is a block diagram for explaining a method of selecting a scanning line in the present embodiment, and FIG. 16 is a diagram of a data output unit according to the present embodiment. FIG. 17 is a block diagram showing an example of the configuration, FIG. 17 is a waveform diagram showing signals of each unit for setting drive waveform generation in the data output unit shown in FIG. 16, and FIG. 18 is an A / D converter according to this embodiment. 19 is a block diagram illustrating an example of the configuration of a D / A converter and a power supply controller according to the present embodiment. FIG. 20 is an exemplary block diagram illustrating an example of a frame drive unit according to the present embodiment. FIG. 21 is a block diagram showing a configuration example, and FIG. 21 is a segment-side drive according to this embodiment. FIG. 22 is a block diagram showing a schematic configuration example of the element, FIG. 22 is a circuit diagram showing a detailed configuration example of the segment side drive element shown in FIG. 21, and FIG. 23 is a schematic configuration example of the common side drive element according to the present embodiment. FIG. 24 is a block diagram showing, FIG. 24 is a circuit diagram showing a detailed configuration example of the common side drive element shown in FIG. 23, and FIG. 25 is an explanatory view showing the display in a simplified manner for explaining the drive mode of the display. 26 (A) and (B) are waveform diagrams for explaining an example of the drive waveforms of the common line and the segment line at the time of block erasing, and are shown in FIG. 27 and FIGS. 26 (A) and (B). FIG. 28 (A) and FIG. 28 (B) are waveform diagrams showing the combined waveforms of the drive waveforms of the common line and the segment line. Waveform diagram for explaining an example of a waveform, FIG. 29 (A) and (B) Figure 28 is (A) and (B)
FIG. 30 (A) and FIG. 30 (B) are waveform diagrams showing the combined waveforms of the drive waveforms of the common line and the segment line shown in FIG. 30, and FIG. 30 (A) and FIG. 31 (A) and 31 (B) are explanatory views for explaining an example of FIG.
32 is a waveform diagram showing a composite waveform of the drive waveforms of the common line and the segment line shown in FIG. 32, FIG. 32 is a waveform diagram showing an inverted waveform of the N waveform, and FIGS. 33 (A) and 33 (B) are waveforms shown in FIG. 34 is a waveform diagram showing a synthesized waveform when output, FIG. 34 (A) to (E) are waveform diagrams for explaining the A waveform used in the high temperature region of the line access mode, and FIG. 35 (A) to (E). Is a waveform diagram for explaining the C waveform used in the low temperature region of the line access mode, FIG. 36 is an explanatory diagram for explaining the display state when MH inversion and frame inversion are performed, and FIG. 36 is a waveform diagram for explaining the manner of performing the driving shown in the figures, FIGS. 38 and 39 are explanatory diagrams showing the relationship between temperature and pulse width and voltage, respectively, and FIG. 40 is a diagram showing temperature and display responsiveness. 41 is an explanatory diagram for explaining the relationship between 42 is a flowchart showing a schematic configuration of a display control procedure according to an example, FIG. 42 is a flowchart showing an example of an initial processing procedure of the display control procedure according to the present embodiment, FIG. 43 is an initial processing shown in FIG. A time chart for explaining the operation of the present embodiment in the time processing, FIG. 44 is an explanatory view for explaining an algorithm for converting temperature data into drive voltage data and time data, according to the present embodiment, and FIG. Figures (A)-(D) and Figures 46 (A)-(L)
FIG. 47 is a flowchart showing an example of a detailed display control procedure in the block access mode and the line access mode according to the present embodiment, and FIG. 47 is a flowchart showing an example of a detailed display control procedure at power-off according to the present embodiment. 48 (A) and (B) and FIGS. 49 (A) to (D),
45 (A)-(D) and 46 (A)-
FIG. 50 is a schematic diagram for explaining the operation of the present embodiment according to the display control procedure shown in (L), FIG. 50 is a schematic diagram for explaining the TN liquid crystal, and FIG. 51 is a schematic for explaining the SmC ^* liquid crystal. 52, FIG. 52 is a schematic diagram for explaining the SmH ^* liquid crystal, FIG. 53 is a schematic diagram for explaining the structure of FLC molecules, and FIG. 54 is a schematic diagram showing an example of a display element using FLC, 55 is a schematic diagram showing an example of an FLC display element applicable to the present invention, FIG. 56 is a schematic diagram showing an example of a cell having a matrix electrode structure applicable to the present invention, and FIG. 57 (A) to FIG. (D) and Figures 58 (A)-(D) show FL
FIG. 6 is a waveform diagram showing a waveform of a voltage applied to a C element. 1 Word processor 50 Display control unit 100 Display 102 Display screen 104 Effective display area 106 Frame 110 Upper glass substrate 112 Wiring unit 114,124… Transparent electrode, 115,125… Extraction electrode, 116,126… Insulating film, 120 …… Lower glass substrate, 122 …… Wiring part, 128 …… Metal layer, 130 …… FLC sealing part, 132 …… FLC, 134 ... spacer, 136 ... alignment film, 140 ... sealing material, 142 ... filling port, 144 ... sealing member, 150,151 ... transparent electrode for frame, 200 ... segment side driving section, 210 ... segment driving element , 220: shift register, 230: latch unit, 240: input logic circuit, 250: control logic unit, 260: switch signal output unit, 270: driver, 300: common side drive unit, 310: … Common drive element, 340 …… Input logic circuit, 345 …… Decoder, 350 …… Control logic section, 360 switch signal output section, 370 driver, 380 board, 382 flexible cable, 384 conductive member, 400 temperature sensor, 500 control section, 501 CPU 503 ROM ROM 507 507 Reset unit 509 Clock generation unit 511 Handshake controller 600 Data output unit 601 Data input unit 603 IRQ generation unit 605: DACT generator, 611: ▲ ▼ generator, 613: FEN trigger, 619: Busy gate, 621: Device selector, 623: Register selector, 625: 22-bit latch pulse gate array 630: Register section, 641: Real address storage control section, 643: Horizontal dot number counter, 645: ▲ ▼ generation section, 650: Decoder section, 661: Multiplier, 663A to 663D: Ring counter , 665,669 …… Multiplexer, 667 …… 4 phase phosphorus Counter, 671,675: Multiplexer unit, 673: Shift register unit, 677: Output unit, 680: Gate array, 690: MR generator unit, 700: Frame drive unit, 710, 715, 720, 730, 735, 740: Switch, 800: Power supply Controller, 810,820,825,830,840 …… variable gain amplifier, 900 …… D / A converter, 901 …… D / A converter, 950 …… A / D converter, 951 …… A / D converter, FL …… light source, PORT1 to PORT6: Port, DDR1 to DDR6: Input / output setting register, TMR1, TMR2: Timer, AB: Address bus, DB: Data bus, com: Common line, seg: Segment line, Fcom …… Frame common line, Fseg …… Frame segment line.

Claims (6)

(57) [Claims] 1. A display device comprising a scan electrode group and a signal electrode group arranged in a matrix to form a pixel group, and a display element arranged between the scan electrode group and the signal electrode group. 1. A display control device for driving, comprising: driving means for respectively driving the scanning electrode group and the signal electrode group; and scanning electrode driving in a one-line scanning period for driving the scanning electrode group output from the driving means. The signal has at least two phases, the first phase of the two phases has a plurality of pulse signals of different polarities, and the plurality of pulse signals of a polarity having an inversion relationship with the polarity of the signal of the second phase A display control device having. 2. The display control device according to claim 1, wherein the display element is an optical modulation element having bistability with respect to an electric field. 3. The optical modulation element is a ferroelectric liquid crystal element, and the display device is configured so that the ferroelectric liquid crystal element has a memory property. The display control device according to item 2 or item 2. 4. The display according to claim 1, wherein the drive means inverts the polarity of the scan electrode drive signal for each M (M is a natural number) line. Control device. 5. The device according to claim 4, wherein M is N times (N is a natural number) times the number of scanning lines of the display device.
The display control device according to item. 6. The display control device according to claim 1, wherein the application times of a plurality of pulse signals of different polarities forming the first phase are different.