JP2738688B2 - Display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a display control device.
Display element having bistability against electric field such as dielectric liquid crystal device
Display control device suitable for a display device using
Is what you do. [Prior art] Conventionally, in a display device, a liquid crystal display using a liquid crystal compound is used.
As the display element, the scanning electrode group and the signal electrode group
With a liquid crystal compound between the electrodes.
It is known to display image information by forming pixels
I have. The driving method of this display element is as follows.
Next, a voltage signal is applied periodically, and the signal electrode group
Signal is applied in parallel in synchronization with the scanning electrode group signal
Time-division driving is used. Such a display element
And its driving method can increase the pixel density or increase the screen
Has a problem that it is difficult to increase
Was. That is, the response speed is relatively high among conventional liquid crystals,
In addition, because of low power consumption, it is practical as a display element
Most TN (twisted nematic) liquids
The liquid crystal of this type is as shown in FIG. 50 (A).
Nematic liquid with positive dielectric anisotropy in the absence of electric field
Crystal molecules twisted in the thickness direction of the liquid crystal layer (helical structure)
Are formed, and the molecules of the liquid crystal are formed between the two electrodes in each layer.
Parallel to the electrode surface and twisted (twisted)
Forming the structure. On the other hand, as shown in FIG.
When an electric field is applied, the nematic
Liquid crystal molecules are arranged in the direction of the electric field, resulting in optical modulation.
Can be rubbed. Matrix using such liquid crystal
When the display element is configured with a scanning electrode structure, the scanning electrode
In the area (selection point) where both the and the signal electrode are selected, the liquid crystal
The voltage above the threshold required to align molecules perpendicular to the electrode surface
Pressure is applied and neither scan electrode nor signal electrode is selected
No voltage is applied to the area (non-selected point),
The electrode is twisted (twisted) parallel to the electrode surface.
It maintains a constant array. Above and below such a liquid crystal cell,
Need to place linear polarizers in a crossed Nicols relationship
At the selected point, no light is transmitted, and at the non-selected point,
Image element because light is transmitted by twist structure and optical rotation
It becomes possible. However, when a matrix electrode structure is constructed,
Area where the scanning electrodes are selected and the signal electrodes are not selected
Alternatively, if the scanning electrode is not selected and the signal electrode is selected
Finite electric field is also applied to the region (the so-called “half-selected point”)
I will. Voltage applied to selected point and applied to half selected point
The difference from the voltage is large enough to move the liquid crystal molecules perpendicular to the electrode surface.
The voltage threshold required for arrangement is set to this intermediate voltage value
If so, the display element operates normally. However, in this method, the number of scanning lines (N) is increased.
When scanning the entire screen (one frame),
The time during which an effective electric field is applied to one selected point (duty
Ratio) decreases at a rate of 1 / N. For this,
Between selected and non-selected points when scanning backward
The voltage difference as the effective value increases as the number of scanning lines increases.
Resulting in reduced image contrast and
Stoke is an unavoidable problem. Such a development is a conventional process that does not have a bistable state.
The liquid crystal used for the display element (the liquid crystal molecules
The flat state is the stable state, and the electric field is effectively marked.
Vertical orientation only during the application).
Drive using the result (ie, scan repeatedly)
It is an inherently unavoidable problem that sometimes arises. This
Voltage averaging method, dual frequency drive
Although the dynamic method and the multi-matrix method have already been proposed,
Either method is insufficient, and the screen size of the display
Higher density is achieved by the inability to increase the number of scanning lines.
The situation had reached a plateau. On the other hand, as a method to solve the above-mentioned problems,
For example, JP-A-59-193426 or JP-A-6-193426
In Japanese Patent Publication No. 0-33535, the Applicant
We are proposing a method for driving a liquid crystal with a constant state.
You. As a liquid crystal that can be used in the above driving method,
Chiral smectic liquid crystals with dielectric properties are most preferred
The chiral smectic C phase (SmC ^* )
Or H phase (SmH ^* A) liquid crystal is suitable. SmC ^* The liquid crystal molecules have a parallel layer structure, as shown in Figure 51.
And the long axis direction of the molecule is inclined with respect to the layer.
You. The tilt direction of these liquid crystal molecules differs for each layer, resulting in
As a helical structure. SmH ^* As shown in Fig. 52, the molecules take a layer structure in parallel.
The long axis of the molecule is tilted with respect to the layer,
It has a hexagonal filling structure in a plane perpendicular to the axis. SmC ^* And SmH ^* Has a helical structure of liquid crystal molecules
FIG. 53 shows a schematic diagram thereof. In the figure, e3 is the liquid crystal molecule and e4 is the electric dipole moment.
And e5 indicate layer boundary surfaces, respectively. Where each
Of the liquid crystal molecule e3 in the direction perpendicular to its long axis
And a certain angle with the Z axis perpendicular to the layer boundary surface e5.
Exercise while maintaining the degree θ, forming a spiral structure
You. This figure shows a state where no voltage is applied.
Assuming that a voltage above a certain threshold is applied in the X-axis direction
Then, the liquid crystal molecule e3 has an electric dipole moment e4 along the X-axis.
Orientation to be parallel. SmC ^* Phase or SmH ^* A phase is one of the phase transitions due to temperature conditions
These liquid crystal compounds are used
When the display device is used,
It is preferred to make a selection. FIG. 54 shows the aforementioned ferroelectric liquid crystal (hereinafter referred to as FLC: Ferroele
ctric Liquid Crystal)
It is shown in a typical manner. e1 and e1 ′ are In _Two O _Two , SnO _Two is there
Or a transparent electrode such as ITO (Indium-Tin Oxide)
Substrate (glass plate), between which the liquid crystal molecule layer e2
SmC oriented perpendicular to the glass surface ^* Phase liquid crystal enclosed
Have been. The liquid crystal molecule e3 shown by the bold line is the molecule e3
It has a dipole moment e4 in the orthogonal direction. substrate
Apply a voltage above a certain threshold between the electrodes on e1 and e1 '
And the helical structure of the liquid crystal molecule e3 unwinds, dipole moment
The liquid crystal molecules e3 are oriented so that
You can change direction. The liquid crystal molecule e3 has an elongated shape
And has a refractive index anisotropy in the major axis direction and the minor axis direction.
And therefore, for example, the orientation direction and
If you place the polarizers arranged in the Snicol positional relationship,
This is a liquid crystal optical modulator whose optical characteristics change depending on the polarity.
It is easy to understand. Furthermore, when the thickness of the liquid crystal cell is made sufficiently thin (for example,
In this case, an electric field is applied as shown in FIG.
The helical structure of the liquid crystal molecules is unwound even without
Child moment P or P 'is upward or downward in the figure
Take either of the following conditions: In such a cell,
As shown in FIG. 55, electric fields E of different polarities exceeding a certain threshold value
Alternatively, when E 'is given for a predetermined time, the dipole moment
Is upward corresponding to the electric field vector of the electric field E or E '
Or change the direction to downward, and the liquid crystal molecules
Either the first stable state f3 or the second stable state f3 '
Orientation. Advantages of using such an FLC as an optical modulation element
There are two points. First, the response speed is extremely high (1).
Second, liquid crystal molecules are bistable.
Is to have a state. The second point will be described with reference to FIG. 55, for example.
Is applied, the liquid crystal molecules e3 are oriented to the first stable state f3
However, this state is stable even when the electric field is turned off. Also reverse
When the electric field E 'is applied, the liquid crystal molecules e3 are in the second stable state.
Orients to the state f3 'and changes the direction of the molecule, but again
This state remains even when the electric field is turned off. That is, the liquid crystal
The molecule e3 will have memory. Also give the electric field
As long as E does not exceed a certain threshold,
Has been maintained. Effectively realizing such high response speed and memory
In order to achieve this, the cell method is preferably as thin as possible.
Generally, 0.5 μm to 20 μm, especially 1 μm to 5 μm
Are suitable. Next, the outline of the FLC driving method will be described with reference to FIGS. 47 to 49.
Will be explained. FIG. 56 shows a matrix in which an FLC compound (not shown) is interposed in the middle.
It is a schematic diagram of a cell having a trix electrode structure. com
This is a scanning electrode group, and seg is a signal electrode group. Run first
The case where the inspection electrode com1 is selected will be described. FIGS. 57 (A) and 57 (B) are examples of scanning signals.
And applied to each selected scan electrode com1
The electrical signal and the other scan electrodes (the unselected scan electrodes)
Pole) Indicates electric signals applied to com2, com3, com4 ...
You. FIG. 57 (C) and FIG. 57 (D) show one example of the information signal.
It is an example, respectively, the selected signal electrode seg1, seg3,
given to seg5 and unselected signal electrodes seg2, seg4
4 shows an electric signal. 57 and 58, the horizontal axis represents time.
And the vertical axis represents the voltage. For example, to display a video
In this case, the scanning electrode group com is sequentially and periodically selected.
You. Now, a predetermined voltage application time Δt ₁ Or Δt _Two Against
Provides a first stable state of a bistable liquid crystal cell
-V _th1 And give a second stable state
+ V for the threshold voltage _th2 And the selected scan
The electrode signal given to electrode com (com1) is shown in Fig. 57
Phase (time) Δt as shown in (A) ₁ Then 2V,
Phase (time) Δt _Two Now, with an alternating voltage of -2V
is there. Different voltages are applied to the selected scanning electrodes.
When an electric signal having a plurality of phase intervals
Equivalent to the "dark" (black) or "bright" (white) state
Fast change of the state of the liquid crystal between the first and second stable states;
Can be awakened quickly. On the other hand, the other scanning electrodes com2 to com5.
As shown in (B), the central potential of the cell applied voltage,
It is at a quasi-potential (for example, a ground state). Also selected
The electrical signals given to the signal electrodes seg1, seg3, seg5
V as shown in FIG. 57 (C), and
The electrical signals given to the signal electrodes seg2 and seg4 are shown in FIG.
-V as shown in (D). Each of the above
The voltage value is set to a desired value that satisfies the following relationship.
You. V <V _th2 <3V −3V <−V _th1 <-V Each pixel when such an electric signal is given
That is, for example, it is applied to pixels A and B in FIG. 56, respectively.
FIG. 58 (A) and (B) show the voltage waveforms. Sand
That is, as apparent from FIGS. 58 (A) and (B), the selected
In the pixel A on the scanning line, the phase Δt _Two At the threshold
Value V _th2 A voltage exceeding 3 V is applied. Also, the same scanning
In the pixel B existing on the line, the phase Δt ₁ At -Vth
A voltage exceeding 1 -3V is applied. Therefore, selected
Whether a signal electrode is selected on the scanning electrode line
Accordingly, if selected, the liquid crystal molecules have a first stable state.
To the second stable state if not selected.
Turn around. On the other hand, as shown in FIGS. 58 (C) and (D),
On scan lines that are not selected, the power applied to all pixels
The voltage is V or -V, neither of which exceeds the threshold voltage.
No. Therefore, in each pixel other than on the selected scanning line,
Liquid crystal molecules were scanned last time without changing the alignment state
Orientation corresponding to the current signal state
You. That is, when the scanning electrode is selected,
Is written, and one frame is completed.
Until the next time it is selected, its signal state can be retained
That is. Therefore, even if the number of scanning electrodes increases,
No change in selection time / line, no reduction in contrast
Does not occur. As described above, a table using a conventional TN-type liquid crystal
In order to solve the problems of the indicator,
It is stable and even when no electric field is applied.
FLC that realizes a display element that can maintain a stable state of
Has been proposed, but this FL
Regarding specific drive control of display element using C, various
There are important characteristics to consider. [Problems to be Solved by the Invention] An object of the present invention is to provide, for example,
Optical modulators such as ferroelectric liquid crystal devices (FLC
Element) to constitute a display device,
Since proper drive control is performed while effectively utilizing the characteristics
The present invention provides a display control device that can be used. [Means for Solving the Problems] To achieve the above object, the present invention provides a scanning electrode group.
And the signal electrode group, wherein the scanning electrode group and the signal electrode
Display devices with ferroelectric liquid crystal display elements arranged between groups
The driving signal supplied to the scanning electrode group is
The waveform has an inverted waveform during the driving period, and the inverting function is
N (n is the same as the driving signal and the same scanning electrode)
Drive in which the (natural number) th and (n + 1) th waveforms are in an inverting relationship
It is characterized by having a means for supplying a signal. [Operation] According to the above configuration, the scanning electrode is provided within one driving period.
Waveform is inverted, and the waveform is
Are inverted, and furthermore, the n-th
The waveform and the (n + 1) th waveform are inverted. Thereby, when driving the scanning electrodes and the signal electrodes,
Voltage application time to threshold voltage of ferroelectric liquid crystal display
Can be reduced. Examples Hereinafter, the present invention will be described in detail with reference to the drawings. The description will be made in the following procedure. (1) Outline of device (2) Configuration of display (3) Outline of display control (3.1) Display frame (3.2) Display element drive waveform (3.3) Display element drive voltage (3.4) Temperature compensation (3.5) ) Display drive system (3.6) Clear display screen (4) Display control device components (4.1) Main symbols (4.2) Control unit (4.3) Memory space (4.4) Data output unit, (4.5) A / D converter (4.6) D / A converter and power supply controller (4.7) Frame driver (4.8) Display driver (4.8.1) Segment driver (4.8.2) Common driver (4.9) Drive waveform (5) Display control (5.1) Overview of control procedure (5.2) Details of control procedure (5.2.1) Power on (initial) (5.2.2) Block access (5.2.3) Line access (5.2.4) Power OFF (6) Effect of the embodiment (6.1) Effect of frame formation (6.2) Effect of temperature compensation (6.3) Control of the control in response to image data input Effect (6.4) Effect of display drive unit arrangement (6.5) Effect of forced screen clear (6.6) Effect of power supply controller arrangement (6.7) Effect of waveform change and inversion drive (7) Modification (7.1) Frame configuration (7.2) Temperature compensation timing and partial rewriting (7.3) One horizontal scanning period and drive voltage value (7.4) Waveform setting (7.5) Block access or line access
Selection (7.6) Number of scanning lines (7.7) Erasure of effective display area (7.8) Position of temperature sensor (7.9) Display, display controller and word processor
FIG. 1 shows an embodiment of the present invention. Where 1 is this example
Supply the image data related to the display to the display related to
A word processor as a host device. 50
Is a display control device according to this example, and is a word processor book.
For the display data etc. supplied from the body 1, various conditions described later
The display is driven and controlled according to the above. 100 using FLC
The configured display. 200 and 300 are display control devices
Each according to the drive data etc. supplied from the main unit 50 side
To drive signal electrodes provided on the display 100.
Drive unit and common drive unit that drives the scanning electrodes
It is. 400 is a suitable position of the indicator 100, for example, average temperature
Is a temperature sensor provided at a portion exhibiting the following. In the display 100, 102 is a display screen, 104 is a display screen 1
02 is the effective display area on the display screen 106.
It is a frame provided outside the area 104. In this example, the frame 106
The electrodes corresponding to are arranged on the display 100 and driven to drive
A frame portion is formed on the screen 102. In the display control device 50, 500 is described later with reference to FIG.
The display unit 100 and the word processor 1
It controls the transmission and reception of various data with the server. 600 is Fig. 16
Is a data output unit described later, and is a word processor.
The control unit 50 for the display data supplied from the main body 1
Drive of the display drive units 200, 300, etc. according to the setting data from 0
Operation and activation for data setting of the control unit 500 are performed. 700
Denotes a frame drive unit, and output data from the data output unit 600
The frame 106 is formed on the display screen 102 based on the. 800 is a power supply controller under the control of the control unit 500.
The voltage signal from the word processor frame 1
To generate the voltage applied to the electrodes by the display drive units 200 and 300
I do. 900 is between the control unit 500 and the power controller 800
It is a D / A converter arranged, and the digital quantity of the controller 500
Is converted to analog data and the power supply
Supply to Troller 800. 950 is temperature sensor 400 and control unit 5
The A / D converter is located between the
Converts output analog temperature data to digital data
And supplies it to the control unit. The word processor body 1 includes a display device 100 or a display system.
A host device that supplies display data to the control device 50
Of course, and of course other forms of host
Alternative to remote devices such as computers and image reading devices
Is possible, but in any case,
Data can be exchanged. That is, first
As data to be supplied to the display control device 50, D: an image data, an address for designating a display position of the data.
Signal including horizontal data and horizontal synchronization signal. Display address of image data (table in effective display area 104
Address data that can be specified
Is a host device having a VRAM corresponding to the effective display area 104.
Output the address data as it is
It can also be done. In this example, the word
The processor 1 converts this signal into a horizontal synchronization signal or a return signal.
The data is superimposed on the line erase signal and supplied to the data output unit 600. CLK: transfer clock for image data PD0 to PD3. The data is supplied to the data output unit 600. PDOWN: A signal notifying that power to the system is to be shut down. Supplied to control unit 500 as non-maskable interrupt (NMI)
I do. And Further, the display control device 50 is provided to the word processor 1.
P ON / OFF: When the system power is turned on and off
At that time, the display control device 50 side starts up and
Status to notify that shutdown has been completed. The control unit 500 outputs. Light: ON / OFF of the light source FL combined with the display device 100
Signal to indicate. The control unit 500 outputs. Busy: The display control device 50 side is
The word processor 1 to make various settings
A synchronization signal that causes the transfer of the signal D to wait. That is, the book
In the example, the word processor 1 sends this Busy signal
Acceptable. The control unit 500 supplies the data via the data output unit 600. (2) Configuration of display Fig. 2 and Fig. 3 are each configured using FLC.
Exploded perspective view and cross section showing an example of the configuration of the display 100 shown in FIG.
FIG. In these figures, 110 and 120 are respectively
Glass plates placed on the top and bottom
Arranged so that it becomes crossed Nicol with respect to the orientation of the child
Is provided. 122 is provided on the lower glass substrate 120
Wiring part, for example, transparent electrode 124 such as ITO and insulating
Consists of a membrane 126. 128 is transparent when low electrode resistance is required
It is a metal layer to be added on the electrode 124, and the display is small.
Need not be added. 112 is on the upper glass substrate 110
It is a wiring part provided, and is provided on the wiring part 122 of the lower glass substrate 120.
Transparent electrodes 114 similar to the respective parts 124 and 126 in FIG.
And an insulating film 116 and the like. The wiring directions of the wiring portions 112 and 122 are orthogonal to each other.
It is. Also, for example, the effective display area 104 is
Using its long side as the horizontal scanning direction,
Supports the effective display area if you want to provide
Then, 400 or 800 transparent electrode groups are set in the wiring section.
In this example, the horizontal scanning direction is the common side.
And a group of 400 transparent electrodes 114 on the upper wiring section 112,
A group of 800 transparent electrodes 124 is provided in the wiring section 122 of the section.
You. Also, outside the effective display area 104 inside the display screen 102
In the portion corresponding to, transparent electrodes 150 for displaying a frame,
If 151 groups are the same as the transparent electrodes 124 and 114 for data display
Or different shapes. Reference numeral 130 denotes a sealing portion of the FLC 132, and the axis of the FLC element (see FIG. 44)
A pair of alignment films 136 for aligning (Z axis) and
Then, the FLC element is changed to the first or second type as shown in FIG.
The distance between the alignment films 136 is regulated so as to take a stable state.
And a spacer 134. 140 encloses FLC132
Sealing material such as epoxy, etc., 142 filled with FLC 132 in the enclosure 130
Filling port 144 to seal the filling port 142 after the filling
It is a sealing member to be performed. 210 and 310 are respectively the segment side drive unit 200
Segment drive element and como
Drive element that is a component of the drive unit 300
In this example, it is an integrated device that drives 80 transparent electrodes.
Circuits are provided, 10 and 5 respectively. 280
And 380 each have a segment drive element 210
Places the substrate to be mounted and the common drive element 310
Substrates 282 and 382 are substrates 280 and 3 respectively.
Flexible cable connected to 80, 299 is flexi
Cable 282 and 382, connect the display
The connector is connected to the control device 50. 115 and 125 are connected to the transparent electrodes 114 and 124, respectively.
Continuously formed extraction electrodes.
Drive elements via conductive members 384 and 284
Connect to 310 and 210. In this example, the lower part of the lower glass substrate 120
Light is radiated from the arranged light source FL, and the FLC element is moved to the first or second position.
Performs display by driving to the second stable state. (3) Overview of display control Applying a display as shown in FIGS. 2 and 3
In such cases, the following problems regarding the characteristics of the FLC element
In this example, we pay special attention to
Configuration of the indicator 100 using the
Drive control is realized. (3.1) Display frame The display 100 was constructed as shown in FIG. 2 and FIG.
In the case, the group of the transparent electrodes 114 on the common side and the segment side
In a range in which a group of transparent electrodes 124 are arranged in a matrix.
The corresponding area on the display screen 102 is
The displayable area, that is, the effective display area 104
There are transparent electrodes on the common side and segment side
Outside the matrix arrangement range of the group and inside the sealing material 140
Display screen 10 including the area corresponding to at least a part of
2 means that the effective display area 104 is completely visible
Desirable above. However, the common side and segment side transparent
Just by arranging the pole group, such a part will eventually
Only the electrodes on one side pass through, so
FLC of the part is floating regardless of the display of image data
It becomes In other words, in such a state, the FL
Since C takes the first or second stable state,
The area on the display screen 102 corresponding to the minute
(White) and non-transparent area (black) are mixed.
The effective display area 104 not only impairs the beauty of the result display
It is difficult to clearly indicate, or cause an illusion to the operator
Condition can also occur. Therefore, in this example, such an effective display area 104
Of the common side or segment side transparent electrode
Transparent electrodes (hereinafter referred to as frame transparent electrodes) 151 and
And 150, and by driving these appropriately,
The part 106 is formed. As a transparent electrode for this frame
Of the transparent electrode 114 on the common side on the upper glass substrate 110.
Segments on both sides of the installation area and on the lower glass substrate 120
On both sides of the arrangement range of the transparent electrode 124, for example, 1
Six electrodes 151 and 150 are arranged. Note that FIG.
For the sake of simplicity, the
And only one on each side is shown. (3.2) Display element drive waveform One of the features of the FLC display element is that it has memory characteristics.
The threshold application time, which will be described later with reference to FIG.
The problem with the drive waveform due to the dependence
And their solutions are described below. In FIG. 56, scanning electrodes com1 to com5.
Of the pixels formed at the intersections of g1 to seg5 ...
Indicates a “bright” state (white), and a pixel indicated by a white background indicates a “dark” state
(Black). These states are described above
Corresponds to a first stable state and a second stable state of the FLC
Things. Now, note the display on the signal electrode seg1 in Fig. 56.
At first, the pixel A corresponding to the scanning electrode com1 has a “bright” shape.
And all other pixels B are in the “dark” state.
You. FIG. 5A shows an example of the driving waveform in this case.
A scanning signal, an information signal given to the signal electrode seg1, and an image
And the voltage applied to the element A in time series.
You. For example, when driving is performed as shown in FIG.
When the scanning electrode com1 is scanned, the time Δt ₁ Pixel at
A has a threshold V _th Voltage of 3V exceeding
Regardless of history, pixel A is in one stable state, ie,
Transition to the "bright" state. After that, com2 ~ com5… are scanned
During this time, a voltage of -V is applied as shown in FIG.
But this is the threshold -V _th Pixel
A can keep the "bright" state. However, in this way, one signal electrode
Signals (in this case, corresponding to "dark") continue to be given
When displaying information, the number of scanning lines is extremely large.
There is also a problem that arises when high-speed driving is required. FIG. 4 shows this characteristic characteristically.
In the figure, the horizontal axis represents the drive voltage value V, and the vertical axis represents the pulse width ΔT (when applied)
Interval). As is apparent from FIG.
Value V _th (Drive voltage value) has an application time dependency,
The shorter the application time, the steeper the curve.
Understood. From this, it was carried out in FIG. 5 (A).
The driving waveform is as follows, and the number of scanning lines is extremely large.
When applied to elements driven at high speed, for example,
Element A is co even if it is shifted to the "bright" state during com1 scanning.
Since the voltage of -V is always applied after the m2 scan,
Accumulation of application time until scan electrode com1 is scanned
This enables transition even at a low threshold, and pixel A
The danger of reversing to a "dark" state
Recognize. FIG. 5 shows a driving waveform for preventing such a phenomenon.
The method shown in (B) can be used. This way
Does not send scanning and information signals continuously.
In addition, a predetermined time interval Δt 'is set as the auxiliary signal application period.
During this period, an auxiliary signal that grounds the signal electrode
It shows the mode of giving. In this auxiliary signal application period,
Since the scanning electrode is also grounded similarly,
The voltage applied between the signal electrodes is the reference potential and is shown in FIG.
Substantially applies voltage application time dependence on threshold voltage of FLC
Can be eliminated. Therefore, it occurred at pixel A
It can prevent the “bright” state from reversing to the “dark” state.
Wear. The same can be said for other pixels. Still another more preferred example is the drive shown in FIG.
By applying a dynamic waveform to the scanning electrodes and the signal electrode group,
Can be implemented. In FIG. 6, the scanning signal is an alternating pulse of ± 2 V.
Signal. The information signal is synchronized with the pulse signal.
Sent to the electrode group, this is the "bright" or "dark" information
Corresponding to + V or -V, respectively. now,
When the scanning signals are viewed in time series, com n (the n-th scanning
Pole) and com n + 1 (n + 1th scan electrode)
Time interval Δt 'is provided as the auxiliary signal application period
You. During this time, the signal electrode group receives signals during comn scanning.
When an auxiliary signal with a polarity opposite to that of the signal electrode group is sent, each signal electrode
Are given, for example, in seg1 to seg3 in FIG.
It is as shown in That is, α ′ in FIG.
The auxiliary signals of ε 'are inverted with the polarities of the information signals α to ε, respectively.
Polarity. For this reason, for example, in FIG.
Looking at the voltage applied to the pixel A in chronological order,
Even if the same information signal is continuously applied to the signal electrodes of
In this case, the voltage applied to the pixel A is V _th The following voltages alternate
At the time of voltage application to the threshold voltage in FLC
The dependency between com1 and com1
Information (in this case, "bright") is written next
There is no reversal before. The two examples of the driving waveforms described above are conceptual for explanation.
In an embodiment to be described later, in the display screen 102,
Driving in the effective display area 104 or the frame 106 or actual driving
Depending on the mode of access and temperature
An appropriate driving waveform is used. Also the waveform described above
Has a positive / negative symmetry, but is not necessarily
Not a name. (3.3) Driving voltage of display element The FLC display element according to this example has a liquid crystal
So that the dipole has its dipole moment in the direction of the electric field
Orientation and even when the electric field is removed,
The feature is to keep it. By the way, two stable states realized as described above
A state change from one state to the other is applied to the display element.
The mode differs depending on the voltage value. That is, FIGS. 7A and 7B show the driving voltage.
(Applied voltage) and FLC transmittance over time
It was done. FIG. 7A shows that the drive voltage is equal to the threshold voltage −V.
_th When the transmittance is in one state.
Change from the other state (for example, “bright” to “dark”).
FIG. 13B shows a case where the drive voltage does not exceed the threshold value.
In this case, the liquid crystal molecules react, but the orientation is reversed.
And the transmittance returns to the original state. In addition, the threshold varies with the type of FLC, and
It fluctuates with the dynamic temperature. This will be described later with reference to FIG.
You. Next, as described above with reference to FIGS.
The dynamic voltage values include the sign of the scanning signal, the sign of the information signal,
And five values of the reference potential are required.
Is controlled by an appropriate power supply according to the apparatus of the present embodiment described later.
Is generated. As is clear from the above, when setting the drive voltage,
Therefore, appropriate temperature compensation considering the threshold etc. must be performed.
No. (3.4) Temperature compensation Regarding the FLC display control of this embodiment, special consideration should be given to temperature compensation.
What we need to consider is SmC ^* Phase FL
C is the pulse width (voltage application time), drive voltage value, etc.
The driving conditions related to
These driving conditions
FLC drive, because the range of cases is narrow
In this case, fine temperature compensation is required. This temperature compensation detects the temperature of the FLC.
Detection of ambient temperature in 02 and drive voltage corresponding to detected temperature
Value setting, pulse width, that is, setting of one horizontal scanning period,
It is done by. The movement of the display screen 102
Considering the operation speed, etc., manual compensation is extremely difficult.
It is difficult. Therefore, temperature compensation is an important factor in FLC display element control.
Specific requirements. The FLC drive parameters, such as the pulse width and drive voltage
A description will be given of how the conditions change with temperature fluctuation. FIG. 4 shows the relationship between the drive voltage value and the pulse width as described above.
According to this figure, the pulse width ΔT is short.
It can be seen that a larger driving voltage V is required as the voltage becomes lower. The pulse width ΔT includes an upper limit ΔTmax and a lower limit ΔTmin
Exists for the following reasons. That is, the so-called
At the time of fresh driving, the frequency f (= 1 /
If ΔT) is less than about 30Hz, it will cause flicker
Therefore, there is a lower limit, that is, ΔTmax, at the frequency f.
If the frequency f is higher than the video rate,
If the speed is higher than the speed of data transfer from
Communication between display screen 102 and word processor 1 is not possible
Frequency f has an upper limit, that is, ΔTmin.
Exist. Further, similarly, the driving voltage V has an upper limit Vmax and a lower limit Vmax.
Vmin exists. This is mainly due to the functions of the drive unit.
It is a cause. FIG. 8 shows the temperature Temp on the horizontal axis and the logarithm of the drive voltage V on the vertical axis.
Shows the relationship between drive voltage and temperature when
The figure shows the change in temperature when the pulse width ΔT is fixed.
Threshold voltage value V _th Is shown. As is clear from the figure,
It is understood that the drive voltage value decreases as the temperature increases.
You. From what was described with reference to FIG. 4 and FIG.
If it rises, the drive voltage value will drop or the pulse width will be short
It turns out that it will be. FIG. 9 shows the relationship between the driving conditions as described above,
FIG. 5 is a diagram for driving. The figure is a look described later
This is an analog representation of the uptable,
The backup table is detected by the temperature sensor 400.
Drive condition data is stored in accordance with the
You. FIG. 9 shows the temperature Temp on the horizontal axis, the drive voltage V on the vertical axis, and
FIG. 4 is a diagram showing a frequency f (= 1 / ΔT), and a temperature range;
When the frequency f is fixed in (A), the temperature Temp increases.
Then, the driving voltage value V drops and exceeds Vmin. Follow
At the temperature point (D), the larger frequency f is set to a fixed value,
The corresponding drive voltage value V is also determined. Below, temperature range
(B) and (C), each of which is similar at temperature point (E)
The operation is repeated. Curve shape formed as above
Depends on the characteristics of the liquid crystal, etc.
The number of sawtooth waves can be determined as appropriate. Further, the following is considered in the embodiment. The FLC element has its characteristics even in the temperature range normally used.
Characteristics vary greatly, and a single drive waveform
It is not enough to simply adjust the pulse width and voltage
There is something wrong. For example, even in the range of 45 ° C. to 5 ° C.
The operating speed may be different on the order of several times,
In such cases, the environmental conditions such as the time zone and season
The difference also causes a sense of incongruity in operation. Therefore, in the embodiment described later, the temperature which is usually used is described.
Divide the temperature range, and
To define appropriate drive waveforms and
Adjust pulse width and voltage according to temperature for waveforms
The average of the operating characteristics.
You. (3.5) Display drive system In this example, data access to the display screen 102
The aspect corresponds to the horizontal scanning line (corresponding to the common side transparent electrode 114).
Line access for each line) and one unit for several lines
Block access for each block
Then, an access is made by any of the preset settings. Ma
In addition, the real address from the word processor main body 1 as the host device is used.
Block or line related to access by dress data
To be able to recognize Here, FIG. 10 shows that the effective display area 104 is a predetermined number of lines.
, BLKl,..., BLKm (1 ≦ l ≦
m). In this example, vertical scanning
400 common-side transparent electrodes 114 in the direction (400 lines)
With 20 blocks in units of 20 lines.
The effective display area 104 is divided into blocks (m = 20). And
Data access for each block divided in this way
When doing this, first, all the lines included in the block
After clearing the display of,
Write data sequentially up to the last line. On the other hand, the display 100 is structured as shown in FIGS.
If done, does the FLC element have memory?
Data that is not updated on the display screen is refreshed.
There is no need to access only the data related to the change on the display screen.
Will be sufficient. In this example, a word processor which is a host device
Depending on the function of the main unit 1, the first line of the effective display area 104
Riff that constantly refreshes the display from the last line to the last line
Driving drive, that is, driving a display without memory
Refreshing equivalent to so-called refreshing drive
And the block or
Partial rewrite driving for rewriting only lines is enabled.
That is, the word processor main body 1 has no memory.
Refresh in the same way as refreshing
Refresh operation when sending data
The block or line when a change occurs.
Partial rewrite operation is possible when image data is transmitted
Noh. When erasing blocks or writing to lines,
Drive based on the temperature compensation data described in (3.4)
U. The temperature compensation data is updated in the refresh drive mode.
In the case of
During the period until access, that is, during the vertical flyback period
And On the other hand, when performing partial rewriting,
Can be performed at regular intervals. In addition, considering the driving conditions described in (3-2), 1
When a positive / negative asymmetric drive waveform is given to a line,
Lines have more positive or negative energy than others.
In this state, the stable state of the FLC element changes.
Adversely affects the control focusing on the memory characteristics of the FLC element
Can be considered. Therefore, in the embodiment, one line
During the driving period, the waveform determined appropriately and the waveform are inverted.
(Hereinafter referred to as the line
Inversion), the total drive energy in one line
Is set to 0 so that the stable state of the FLC element does not change.
I do. In addition, when driving the display 100 for writing, the scanning
Scan while sequentially selecting pole 114 (common line)
Supplying signals to signal electrodes 124 at the same time at the time of selection
The same waveform is applied to the common line.
When added, the elements are uniformly shifted on the time axis for each line.
One optical response characteristic, which allows the operator to
You will feel flicker on 102. Therefore, this implementation
In the example, every line (every one horizontal scan) or every few lines
The driving waveform is also inverted, that is, every adjacent line
Alternatively, a waveform of opposite phase should be given every few lines.
This is called MH reversal below). This means that humans can see the optical response
One line or several lines next to each other
If they are driven in opposite phases, you will feel swell on the display screen
It is based on being able to prevent kinking. In addition, in the embodiment, in the refresh driving mode,
1 unit from the first line to the last line (1 frame
Each line) or every N frames.
Process to invert the drive waveform for the
Inversion). That is, there is one frame
As a result of performing in-line inversion for a line, the line
Shows an appropriate waveform (hereinafter referred to as “no
I ′ and its inverted waveform I in this order.
If given, next frame or N frames
During the subsequent drive, the inverted waveform I and the normal waveform I '
Be given in order. The descent of this frame inversion
It will be described later. (3.6) Clearing the display screen In this example, the FLC element has
Maintains first or second stable state without pressure application
Things. In other words, unless a voltage is applied,
Is held. Therefore, when the power is turned off, the display screen 102, at least
It is desirable to clear the effect display area 104. For example, the table
Power-off can be recognized depending on the status of the display screen 102.
is there. Also, when the power is shut off for some reason,
The clear state of the display screen changes and meaningless data is displayed
It is possible that the actual
To prevent the mixture of display data and meaningless data
Clearing the effective display area 104 when turning on the power
desirable. Focusing on this point, in this example, when power is turned on,
To clear the effective display area 104 and form the frame 106
And clear them even when the power is turned off.
You. When clearing the effective display area 106,
Block erasure as described in (3.5) is performed for all blocks.
About to do. Furthermore, in such a clearing, the host device
Screen erase data from the main word processor 1
Even if it is not supplied with all-white data),
So that the burden on the word processor 1 can be reduced.
High speed of clearing by reducing and eliminating transfer
Plan. (4) Configuration of each part of the display control device The functions described in “(3) Overview of display control” are realized.
Of the display control device 50 for the purpose will be described in detail. (4.1) Main symbols First of all, signals or data exchanged between parts
Summarize about. (4.2) Control Unit FIG. 11 shows a configuration example of the control unit 500. Where 501 is
Each part is controlled according to the control procedure shown in FIG.
Microprocessor-type CPU 503 is the third CPU executed by CPU 501.
41 In addition to the programs corresponding to the control procedures shown in Fig. 12, Fig. 12
It is a ROM in which various tables shown are developed. 505 CPU 501
RAM used for work and the like in the process of executing the control procedure.
You. In this example, this RAM 505 is used for frame inversion.
Counter, i.e., how many frames
Area FC that stores a value N indicating whether
Counter for NT and MH inversion, that is, every number of lines
Stores a value that indicates whether to give a waveform in reverse phase and uses it as a counter.
When setting the waveform according to the area LCNT used and the temperature
Used to recognize the waveform used at that time.
And a register CX. PORT1 to PORT6 are ports that can set the input / output direction
Yes, respectively, ports P10-P17, P20-P27, P30-P3
7, with P40-P47, P50-P57 and P60-P67. P
ORT7 is an output port and has P70 to P74. DDR1
DDR6 is the input / output method of the port section PORT1 to PORT6, respectively.
Input / output setting register (data
Direction register). In this example,
There are ports P13-P17 (signals A3-A
7), ports P21 to P25 and P2 of port PORT2
7, P40 and P41 of port section PORT4 (signals A8 and
And A9), Ports P53-P57, Port
Port P62 of port PORT6 and port P72 of port PORT7
~ P74, and each terminal MP0, MP1 and STBY of CPU501 are not used.
It is for. 507 and 509 reset the CPU 501, respectively.
Reset section and the operation reference clock (4M
Hz). TMR1, TMR2 and SCI are the reference clock source and registers.
The reference clock in accordance with the setting in the register.
This is a timer capable of frequency division and the like. First, timer TMR2
Divide the reference clock according to the register setting and output data
A signal Tout serving as a system clock of the unit 600 is generated.
In the data output unit 600, based on the signal Tout,
Generates a clock signal that defines one horizontal scanning period (1H)
You. The timer TMR1 determines the operating time on the program and the display screen 10
2 to adjust 1H, and use that adjustment
It is realized according to the set value to the star. These timers TMR1 and TMR2 are set based on the set value.
When the set time expires, or
Signal IR as an internal interrupt at the start of the next timing operation
Q3 is supplied to the CPU 501, and the CPU 501
I can. Note that timer SCI is not used in this example.
It is. In FIG. 11, AB and DB are CP
Internal address bus and data connecting U501 and each part
Tabus, 511 is a hand between port parts PORT5, PORT6 and CPU501.
Shake controller. (4.3) ROM memory space (4.3.1) Configuration of memory space Fig. 12 shows an example of the configuration of the memory space allocated to the ROM 503.
Show. Here, each area of A000H to A3FFH and A400H to A7FFH
The A / D converter 950 and the D / A converter 900 respectively
When accessing, store the data to specify them.
It is. For A800H to ABFFH, access the data output unit 600.
The display drive register (see Fig. 16).
The data for specifying (see) is expanded. The area C000H to E7FFH is the area from the word processor 1
This area is referred to in response to the transmission of address data RA / D.
Address transmitted during block access.
Data is related to the first line of the block
Jumping table to determine the
Common side to be driven for real address data RA / D
And a line table for specifying a line. Regions E800H to EFFFH are shown in FIGS. 42 and 45 to 47.
Stores various parameter groups used for control described later
Area that stores the number of blocks (20 in this example)
Block related data area (E800H ~), according to temperature
D / A converter 900 for variable setting of drive voltage of transparent electrode
D / A converter related data area (E
900H ~), display 100 in block access mode
Clock To which is the reference for setting one horizontal scanning period (1H) above
The setting data to the register TCONR in the timer TMR2 that outputs ut
Block access timer TMR that stores data (TCONR)
2 Setting data area (EA00H ~), operating time on display 100
Delay tie to adjust the time for control
Register setting data (CNTB) of timer TMR1
Timer TMR1 setting data storing (CNTL) and (CNTBB)
Regions (EB00H ~, EC00H ~, ED00H ~ respectively). In addition, in the line access mode,
Timer TMR that outputs clock Tout, which is the reference for setting H
Setting data (TCONRL) stored in register TCONR of 2
Line access timer TMR2 setting data area (EE00H
~), And temperature in line access mode
Line for starting a program that drives with a different waveform
Set jumping table area for access (EF00H ~)
There is. The area E000H ~ is shown in FIGS. 41 to 42 and FIGS. 45 to 4.
7 A program corresponding to the processing procedure
This is the program area that was loaded. (4.3.2) Jumping card in block access mode
Cable (C000H ~) In this example, the word
Real address data RA sent from the processor body 1
Process depending on whether / D is related to the first line of the block
The route is different. This corresponds to the first line of the block.
The table in that block when address data is supplied
After clearing the indication,
This is based on the fact that sequential writing is performed. Therefore, the actual data transmitted from the word processor 1 is
Address data RA / D corresponds to the first line of the block
It is necessary to recognize whether or not it is
First, each address for the first line of each block
Data every time real address data is input
It is conceivable to make a comparison judgment. However, according to such successive approximation, the comparison
Differences in processing time occur as the number of targets to be increased increases
Become. That is, in the program of the comparison judgment processing step
This is because the number of comparison processes increases / decreases depending on the order. Therefore, in this example, a jumping table is used.
The following judgment process is performed to make the judgment time uniform.
So that For example, as shown in FIG.
The actual address data from 1 is "03" H (in the license
"3"), this data is shifted one bit to the left,
Set the two least significant bits to “1” and the least significant bit to “0”.
Then, data “C006” H after offset is obtained. this
Data is an address in the memory space, and this memory space
The code at the top address indicates whether it is the first line of the block.
If stored, all real address data
It is possible to identify whether it is the first line of a block in the same execution time
It works. Furthermore, the CPU 501 used is an index register (IX)
And the address indicated by the index register
Instructions that can jump to (for example, "JUMPIX" can be processed
If it is, store the offset data in IX and
Write the jump destination address in the jumping table
By executing the above instruction, the appropriate
Processing can be started. In this example, the index register is used as the CPU 501.
And those that allow the use of the above instructions, shown in Figure 14.
In accordance with the line number (0 to 399),
Set up ping table (C000H to C31EH) and jump
The procedure to be started (specifically,
Stores the start address on the program area for that procedure)
Keep it. Note that BLOCK, LINE and FLINE in FIG.
Each block erase operation at the time of block access
Order, line writing procedure, and the end of the effective display area 104
Procedure for updating temperature compensation data with line writing
These are shown in FIGS. 45 (A) to (D).
Will be described later. During line access, the temperature compensation data
Whether or not the last line to determine whether to perform the update procedure
Only one object needs to be compared.
And the line number
The judgment using the dress is not performed. (4.3.3) Line table The actual address data RA / D is the configuration of the common side drive unit 300.
Some require conversion. For example, in this example, drive
The part 300 consists of five common drive elements 310,
Each outputs 80 bits, and 4 outputs every 20 bits.
Construct block and scan 400 lines as common side line
Lines are provided. To select one of these scanning lines
(1) Select one of the five common drive elements 310
Select. (2) Four blocks assigned to the element 310
Select one from the list. (3) Select one line from the 20 lines in the block
You. Is performed. In this example, as shown in FIG.
Using the alternative address, the 12th to 8th bits are
Bit 310 and the sixth and fifth bits are used to select a block.
Alternately, the 4th to 0th bits are assigned for line selection.
From actual address data to line selection address data
The conversion is based on the jumping table of FIG.
Processing can be performed almost in the same way as the
The data may be expanded in a line table. In FIG. 15, reference numeral 680 denotes the selection of the element 310 (E).
A decoder chip for selecting the chip).
Depending on the configuration, and for chip select
Since 5 bits of 8 bits are allocated, 2 ^Five = 32
Up to a maximum of 310 elements 310 can be added. At this time
Can select 2560 lines as scanning lines.
You. (4.3.4) About various parameter storage areas In this example, the display 100 is driven according to the temperature condition.
Conditions such as drive voltage, one horizontal scan period, delay
Data, and in line access mode,
It also changes the shape data to achieve optimal drive control.
is there. Therefore, based on the temperature measurement data from the temperature sensor 400,
When driving, the driving conditions must be corrected.
No. Areas E900H to EFFH are areas where this correction data is stored.
Read out various parameters according to temperature as described later
In this example, the following storage is used to improve the efficiency of
I will go. That is, for one or a range of single-step temperatures,
Then, for example, each one D / A conversion section related data,
(TCONR), (CNTB), (CNTL) or (CNTBB),
(TCONRL) should correspond to the temperature
A group of parameters is an area where the lower 2 bytes have the same value.
To be stored. And almost as described in Figure 13
Similarly, the temperature data obtained from the A / D converter 950 or
The temperature data obtained by appropriately processing this is added to the lower 2 bytes.
And the upper 2 bytes can be rewritten sequentially and read
A group of parameters corresponding to the temperature
Become. For example, if the temperature data is "0080" H,
By accessing “E980” H address with “E900” H added
The data related to the D / A converter corresponding to the temperature (drive
Dynamic voltage), and then added “0100” H to “E980” H
By accessing address “EA80” H, timer TMR2
Setting data (TCONR) (1 horizontal scan on the display screen)
Data for generating the basic clock that defines the period)
Is obtained. Hereinafter, addition and access are performed in the same manner.
As a result, CNTB, CNTL, and CNTBB corresponding to the temperature are sequentially obtained.
Will be done. Also, especially in the line access mode,
The waveform is changed in accordance with
Data in block access mode (TCONR).
Since it cannot be used as is,
Range EE00H ~ Data according to temperature and waveform (TCONRL)
Read out and set. The jumper used in the line access mode
The driving table area EF00H ~
To launch a program to perform the
The start address of the program is stored for block access.
Startup processing similar to the jumping table (see Fig. 14)
I do. In this example, an operating temperature range of 45 ° C to 5 ° C is assumed.
This range is divided into three parts, and the line is
The waveform described below with reference to FIG.
In the temperature range of 35 ° C to 15 ° C.
The waveforms to be described later with reference to FIG.
N-waveform) in the temperature range of 15 ° C to 5 ° C.
The waveform described below with reference to FIG.
It is called a waveform. ) Is set to perform control. this
For this reason, in this example, a special program
Are activated, and output of A waveform, N waveform and C waveform
Routines LSTRA0, LSTRN0 and LSTRC0 related to force
The top address of the area corresponding to temperature
It has been converted. (4.4) Data Output Unit (4.4.1) Configuration FIG. 16 shows a configuration example of the data output unit 600. here
601 is connected to the word processor 1 and the signal D and
And a data input unit for receiving the transfer clock CLK.
The signal D is a word obtained by adding the image signal and the horizontal synchronization signal.
Is transmitted by the main processor 1 and is not
The horizontal synchronization signal or horizontal blanking period,
Data is superimposed and supplied. Thus, the data
The input unit 601 detects the horizontal synchronizing signal or horizontal blanking period.
The data output path is switched according to the presence or absence of the
The signal component superimposed at that time is the actual address data
And outputs as real address data RA / D.
At the time of detection, the signal components during that period are recognized as image data.
Output as 4-bit parallel image data D0 to D3.
You. The data input unit 601 is used to input real address data.
When recognized, activates the address / data identification signal A /
This signal A / is output from the ▲ ▼ generator 603 and DACT
It is guided to the generating unit 605. ▲ ▼ In the generator 603,
Outputs interrupt signal ▲ ▼ in response to signal A /
This is the interrupt command according to the setting of the switch 520.
Supplied to the control unit 500 as ▼ or ▲ ▼
Line access mode or block access mode.
Operation is performed. On the other hand, the DACT generator 605
The presence or absence of access to the display unit 100 in response to the arrival of signal A /
A DACT signal for performing another is output, and this is
▲ ▼ Lead to the generator 611 and the gate array 680. The generation unit 611 detects when the DACT signal is activated.
▲ ▼ For input of trigger signal from trigger generator 613
Activates the gate array 680 in response to the signal ▲ ▼
The control unit 500 performs A / D conversion on the generated ▲ ▼ trigger generator.
Instructs unit 950 to take in temperature information from temperature sensor 400.
Trigger signal is generated by write command ▲ ▼
I do. At this time, the ▲ ▼ trigger generator 61
3 is the chip select signal generated by the device selector 621.
The selection is made by the number ▲ ▼. That is,
In order for the control unit 500 to read the temperature data,
When performing select, ▲ ▼ trigger generator 613
Is also selected, and frame drive is also performed according to the line signal ▲ ▼
Will be activated. 619 is displayed according to the busy signal IBUSY from the control unit 500.
Signal BUSY for notifying the busy state of the
This is a busy gate to be sent to the processor body 1. 621 receives the signals A10 to A15 from the control unit 500, and
A / D converter 950, D / A converter 900 and data output according to
Signals for performing chip select of unit 600
Output ▲ ▼. 623 responds to the signal ▲ ▼
Is activated, and at this time, based on the signals A0 to A4 from the control unit 500,
Then, the latch pulse gate array 625 is set. La
The switch pulse gate array 625 is
This register is used to select a register.
The number of bits corresponds to the number of stars. In this example
Therefore, the register section 630 has 22 areas of 1 byte each.
The latch pulse gate array 625 has one bit for each area.
In a 22-bit configuration. That is, Regis
Selector 623 is the bit of the latch pulse gate array 625
When set, the area corresponding to the bit is selected.
Selected, and latch pulse gate
Read signal ▲ ▼ or write signal ▲ to ray 625
The system for the selected register is
Data reading or data writing via the system data bus
Is performed. In the register section 630, RA / DL and RA / DU
Lower and upper 1 byte of address data RA / D
This is the real address data register that stores and stores
Is performed by the real address storage control unit 641. DC L and DC U are the number of dots in the horizontal scanning line direction of the display.
(800 dots in this example)
Horizontal dot count for storing the upper 1 byte
Data register. Transfer of image data D0 to D3 starts
The number of horizontal dots that are activated at the time and count the appropriate clock
Counter 643 is stored in registers DCL and DCU.
The latch signal ▲
The generation unit 645 is caused to perform the generation. DM is a drive mode register, which is used for line access.
Or mode data corresponding to block access is written
I will. DL L and DL U are common line selection address data.
Register, 16-bit data shown in Fig. 15
Store the lower and upper 1 byte for each
You. Then, the data stored in the register DLL is
Address data CA6, CA5 for specifying the
And 5th bit) and address for line designation
Data CA4 to CA0 (corresponding to the 4th to 0th bits in FIG. 15) and
And output. The data stored in the register DLU
Is supplied to the decoder section 650, and the common drive element is supplied to the decoder section 650.
Chip select signal ▲ ▼ to ▲
Output as ▼. CL1 and CL2 are used in block access mode.
When driving the line on the mon side (line writing), the common side
1-byte data for storing drive data to be supplied to the drive unit 300
Regions SL1 and SL2 are also segment line
Drive data to be supplied to the segment side
This is a 1-byte area for storing data. CB1 and CB2 are blocks in block access mode
When driving the common side line during erasing, the common side
1-byte data for storing drive data to be supplied to the drive unit 300
Regions SB1 and SB2 are also
This is a 1-byte area for storing drive data to be supplied. CC1 and CC2 are line write in line access mode
When driving the common line at the time of
1-byte area for storing data to be supplied to the moving unit 300, S
C1 and SC2 are also supplied to the segment side drive unit 200
This is a 1-byte area for storing drive data. The next three 1-byte areas are the switching of the frame driver 700
Area for storing data to perform
Registers FV1, FVCc, FV2, FV3, FSVc, FV4
There is. Reference numeral 661 denotes a multiplier, which is a pulse signal Tout from the control unit 500.
Is doubled, for example. 663A, 663B, 663C and 663D
3-phase, 4-phase, 6-phase, and 12-phase ring couplers at the output of the multiplier 661
Counter, block access mode, or line
When N waveforms in the access mode are selected, one horizontal scanning period (1
H) is divided into 4 divisions, 3 divisions, 2 divisions and no divisions respectively
Used for This divided period is hereinafter referred to as ΔT.
For example, in the case of three divisions, 1H is formed by 3ΔT. In the line access mode, the normal waveform
In-line inversion control using a combination of I 'and inversion waveform I
When selecting the A waveform and the C waveform according to
I 'output period (hereinafter referred to as 1H ^* Called period, 1H ^* Period
1H is constituted by a plurality of combinations. Also the line
1H = 1H when inversion is not performed ^* It is. ) Ring
4 division, 3 division, 2 division or no division by counter
It is. At this time, for example, in the case of three divisions, 1H at 3ΔT
^* , And ΔT in this case causes in-line inversion.
It is set to a value that is substantially smaller than ΔT when not performed. 665 is the ring counter from any of 663A to 663D output
Is a multiplexer for selecting the drive mode
Drive 1H according to the contents of register DM, i.e.
This is set according to data indicating whether or not to perform an action. For example,
In case of 3 division, select the output of 4-phase ring counter 663B
I do. 667 is a four-phase link for each output of the ring counter 663A to 663D.
Counter 669 is set similarly to multiplexer 665.
Multiplexer. FIG. 17 shows the clock Tout, the output waveform of the multiplier 661,
15 shows output waveforms of the counters 663A to 663D and 667. You
That is, the ring counter 663A is provided by the multiplexer 665.
When any of the ~ 663D outputs are selected, 4ΔT / 1H, 3Δ
T / 1H, 2ΔT / 1H or ΔT / 1H (or 4ΔT / 1H ^* , 3ΔT
/ 1H ^* , 2ΔT / 1H ^* Or ΔT / 1H ^* ) Is selected and its output
The waveform is sent to the shift register
And output of ON / OFF data for each ΔT
It is. The output of the 4-phase ring counter 667 is
The output waveform is selected by Lexer 669.
Supplied to the shift register 673 as a shift / load signal.
The operation is set for the selected number of divisions.
You. Referring again to FIG.
For the areas CL1, CB1 and CC1,
Clear signal ▲ ▼ and enable signal CEN
ON / OFF data for each ΔT is stored in areas CL2, CB2 and CC2
Similarly, the drive waveform defining signals CM1 and CM2 are turned off every ΔT.
On / off data. Also, the areas SL1, SB1 and S
C1 is the clear signal sent to the segment side drive unit 200
▲ ▼ and enable signal SEN on every ΔT
/ OFF data is similarly transmitted to the areas SL2, SB2 and SC2.
ON / OFF data for each ΔT of the shape specification signals SM1 and SM2
Store. In this example, the storage area for each signal data is 4 bits.
1 bit for 1ΔT ON / OFF data
Let me respond. That is, in this example, 1H or 1H ^* The largest of
The number of divisions is four. Reference numeral 671 denotes a multiplexer unit coupled to the areas CL1 to SC2.
Block operation according to the contents of the drive mode register DM.
Access mode when writing a line or when erasing a block.
Drive during line writing in line access mode
Select one from the signal data at the time of operation. This circle
In the multiplexor section 671, MPX1 has regions CL1, CB1 and CC.
4-bit data from 1 to any signal ▲ ▼
The multiplexer to select the MPX2 is also for the signal CEN
Multiplexer for selecting 4-bit data, MPX3 is area
4 bits for any signal CM1 from CL2, CB2 and CC2
A multiplexer for selecting data, MPX4 is also a signal CM
A multiplexer for selecting 4-bit data for 2
You. In addition, MPX5 is any one of areas SL1, SB1 and SC1.
Multi to select 4-bit data for signal ▲ ▼
Plexa and MPX6 also use 4-bit data for signal SEN
The multiplexer to select, MPX7 is the area SL2, SB2 and SC2
Select 4-bit data for any signal SM1 from
The multiplexer, MPX3, is also a 4-bit data for signal SM2.
This is a multiplexer for selecting data. 673 are connected to MPX1 to MPX8 of the multiplexer 671 respectively.
Shift register for combined parallel / serial (P / S) conversion
This is a shift register unit having P / S1 to P / S8
The output of the multiplexer 665 is given as a shift clock signal.
And the output period ΔT of 1-bit on / off data is regulated.
Is determined. Also, the output of multiplexer 669 is set.
As a preset signal for performing operations with the
available. 675 coupled to shift registers P / S1 to P / S8 respectively
Multiplexer unit having multiplexers MPX11 to MPX18
And 4 bits of each signal stored in registers CL1 to SC2.
Bit on / off data bit selection data (register DM
On / off data based on P / S conversion
677 is above for registers FV1, FCVc, FV2, FV3, FSVc, FV4
Same as shift register 673 and multiplexer 675
The output section that performs the same processing, 680 is the signal DACT and ▲
Opened in response to ▼, switch signal ▲ to frame drive unit 700
▼ to ▲ ▼, ▲ ▼ and ▲ ▼
It is a port array. 690 is used to activate the chip select signal DS1 of the D / A converter 900.
Accordingly, that is, when the D / A converter 900
Sends MR to the control unit 500, and generates a clock E generated by the CPU 501.
This is an MR generator for changing the pulse width of the pulse. (4.5) A / D converter FIG. 18 shows an example of the configuration of the A / D converter 950. Where 95
1 is an A / D converter and 953 is an A / D converter for the detection signal of the temperature sensor 400.
This is an amplifier that amplifies to a level suitable for the converter 951. When detecting the temperature, the control unit 500
Chip select signal via device selector 621
▼ and write signal WR (here ▲
(Shown as ▼). A / D conversion accordingly
The converter 951 is obtained from the temperature sensor 400 via the amplifier 953.
Conversion of the temperature detection signal of the analog
At the end of the operation, activate the signal ▲ ▼ to change the A / D
The control unit 500 is notified of the end of the switching. The control 500 responds to this by sending a read signal to the A / D converter 951.
Supply ▲ ▼ (shown here as ▲ ▼)
In conjunction with this, the A / D converter 951 converts the digital temperature
Controller 50 as signals DD0 to DD7 via the system bus.
Send to 0. The temperature detection timing is based on the first line of the effective display area 104.
Constantly refresh the display from the in to the last line
The last line drive when performing refresh drive
To be performed during the vertical flyback period from the start of the first line drive
Can be. Also, when the display data changes,
Partial rewrite drive that rewrites only blocks or lines
When it is performed, it is performed periodically, for example, by a timer interrupt.
You can do so. (4.6) D / A converter and power supply controller Figure 19 shows the D / A converter 900 and power supply controller 800.
One configuration example is shown. In the D / A converter 900, 901 is a D / A converter, and 903 is
This is an amplifier that amplifies the output so as to be suitable for the next stage. In the power supply controller 800, 810,820,825,830 and
And 840 respectively generate voltage signals V1, V2, VC, V3 and V4.
Variable gain amplifier for generating voltage V1
By guiding the output of 903 to the amplifier 810, the voltages V2, VC, V3
And V4 output the output of amplifier 810 to amplifiers 820, 825, 8
Generated by leading to 30 and 840. 821 is an amplifier 81
Inverter inserted between 0 and 820, 841
This is an inverter interposed between 840 and 840. Here, the voltages V1 and V2 are supplied to the common driver 300.
Supply positive and negative drive voltages, voltages V3 and V4 respectively
Are positive and negative, respectively, supplied to the segment side drive unit 200.
And the negative drive voltage and voltage VC are applied to the drive units 200 and 300, respectively.
It is a quasi-potential. These voltage signals are sent to the frame driver 700.
Also supply. In this example, VC is fixed, and V1, V
2, The ratio of the difference between VC, V3, and V4 is set to 2: -2: 0: 1: -1.
Adjust the gain of amplifiers 810, 820, 825, 830 and 840 in advance.
I will keep it. When changing the drive voltage according to the temperature,
500 is via the device selector 621 of the data output unit 600
Supply chip select signal ▲ ▼ and D / A converter 901
Make a selection. Here, the basic clock of the operation of D / A converter 901
Signal is different from the control unit 500, the signal ▲
▼ is also supplied to the MR generator 690 located in the data output unit 600.
Signal MR is generated, and the control unit 500
The signal E is supplied to the D / A converter 901. Thus, the control unit 500
Is the light signal ▲ ▼ (here ▲ ▼
)) And digital data for change setting
Are supplied to the D / A converter 901 via the system bus as DD0 to DD7.
Pay. In response, D / A converter 901 analyzes the data.
The signal is converted into a log signal and output via the amplifier 903. This causes the amplifier 810 to generate the voltage V1 and
In addition, voltages V2, VC, V3 and V4 having the above ratio with respect to V1 are
Generated. In the example of FIG. 19, the voltage V2 and the like are generated in accordance with FIG.
However, the output of the amplifier 903 can be
As leading to variable gain amplifiers 810,820,825,830 and 840
May be. In addition, programmable gain adjustment
A variable gain amplifier that can be used may be used. Ma
In addition, the configuration of the power supply controller 800 is such that each drive unit 200, 300, etc.
Can generate multi-valued voltages according to the driving mode of
If there is, it is not limited to the above configuration and various things
It goes without saying that you can do it. (4.7) Frame Drive Unit FIG. 20 shows a configuration example of the frame drive unit 700. Where 71
0,715,720,730,735 and 740 are respectively the voltage signal V
1, VC, V2, V3, VC and V4
From the gate array 680 of the data output unit 600.
Supplied via inverters 711,716,721,731,736 and 741
Switch signals ▲ ▼, ▲ ▼, ▲ ▼, ▲
It is controlled by ▼, ▲ ▼ and ▲ ▼. When driving the frame, the register unit 630 of the data output unit 600
According to the contents of registers FV1, FCVc and FV2
The signals ▲ ▼, ▲ ▼ and ▲ ▼
Switches 710, 715 and 720 are switched according to the state of
And a signal with a waveform that takes three values, V1, VC, and V2, is sent to the common line.
It can be applied to the parallel frame transparent electrodes 151. Ma
In addition, depending on the contents of registers FV3, FSVc and FV4,
Depending on the status of the signal ▲ ▼, ▲ ▼ and 4
Switches 730, 735 and 740 are switched to V3, VC and
And V4 tri-level signal parallel to segment line
It can be applied to the transparent electrode for frame 150. (4.8) Display drive unit (4.8.1) Segment side drive unit Fig. 21 shows the segments constituting the segment side drive unit 200.
4 shows a schematic configuration example of a driving element 210. Where 220
Sequentially inputs 4-bit parallel image data D0 to D3,
4x20-bit aligned to 80-bit parallel data
A shift register that responds to the input of the shift clock SCLK.
Work. 230 is an 80-bit latch,
Data D0 to D3 are stored in the segment drive element 210 of the next stage.
Guided by shift register 220, 10 elements 2
All 10 shift registers 220 have 80-bit parallel data
When the data is aligned,
▼ Latch signal ▲ ▼ is applied from generator 645
Latches 80-bit parallel data when
You. 240 is the signal ▲ ▼, ▲ from the data output unit 600
▼, accept SM1 and SM2 and perform predetermined logical operation
Input logic circuit, 250
Each segment according to the content of each bit data of the latch unit 230
Control logic that generates the specified data
You. 260 is a level shift of data generated by the control logic unit 250.
Switch having level shifter and buffer for performing switching
Signal output 270 receives voltage signals V3, VC and V4 and switches
Switching is performed according to the output of the switch signal output unit 260.
Lead V3, VC or V4 to segment lines S80-S1
Iva. FIG. 22 shows the segment drive element 210 shown in FIG.
A detailed configuration example is shown. In the shift register 220, 221
Is a D type corresponding to one bit, that is, one segment line.
231 is a latch in the flip-flop and the latch unit 230.
Circuit. In the switch signal output unit 260, 261
Are level shifters, 275, 273 and 27 in driver 270
4 according to the switch signal from the switch signal output unit 260
To turn on / off the supply paths of voltages VC, V3 and V4, respectively.
A switch to turn off. (4.8.2) Common-side drive unit FIGS. 23 and 24 show the configuration of the common-side drive unit 300.
Schematic configuration example of the common drive element 310
Configuration examples are shown below. Where 340 is an input logic circuit
Yes, the chip selection from the decoder section 650 of the data output section 600
Signal CA5, CA6, CE
In addition to performing block selection by N, line selection signals CA0 to
Accepts CA4, signal ▲ ▼, CM1 and CM2
Logical adjustment. 345 corresponds to the signals CA0 to CA4 supplied from the input logic circuit 340.
Selection of a common line to be driven based on the line data
Is a decoder unit that performs
80 lines can be selected. In this example, 20 lines
One element is one block, and one element 310 has four
Blocks are allocated, and in Fig. 24 the decoder section
345 is surrounded by a broken line for each part for decoding 20 lines
It is. 350 is a control logic unit, which is supplied by the input logic circuit 340
Drive data for signals CM1, CM2 and ▲ ▼
Then, the block selected by the input logic circuit 340 or
In addition, the drive waveform definition data of the line selected by the decoder unit 345
Data. 360 converts the level of data generated by the control logic 250
Switch with level converter and buffer to do
Signal output, 370, receives voltage signals V1, VC and V2 and
Switched according to the output of switch signal output section 360
V1, VC or V4 is selectively supplied to common lines C1 to C80.
The driver to supply. In this example, the common-side element 310 having such a configuration is used.
Are provided, that is, 400 lines are provided in the effective display area 104.
Correspond to the common line. In FIG. 24, reference numeral 361 denotes a level converter, and 375, 3
71 and 372 are switches from the switch signal output section 360
Supply voltage VC, V1 and V2 according to the signal
A switch for turning on / off the road. (4.9) Drive waveform (4.9.1) Outline of display FIG. 25 schematically shows the display 100. Where com and
And seg are the common side transparent provided on the upper substrate 110, respectively.
The common line corresponding to the electrode 114 and the lower substrate 120
The segment line corresponding to the digit segment side transparent electrode 124
The FLC is provided between them. Fcom
And Fseg, respectively, are the installation range of common line com
Common line for frame provided parallel to common line com on both sides of
In, and on both sides of the installation range of the segment line seg
Segment line for frame provided in parallel with segment line seg
Inn. Thus, common line com and segmenter
Display corresponding to the set of crossover parts on Fig. 25 with in-seg
The area on the screen 102 forms the effective display area 104, and the frame common
Line Fcom and frame segment line Fseg and segment
Intersection with the line seg, and the frame segment line
The set of intersections between Fseg and common line com is an effective table
A frame 106 outside the display area 104 is formed. In FIG. 25, common lines are used for simplification.
4 for each com and segment line seg
Monline Fcom and segment line for frame are both Fseg
Each one is shown on the side, but in this embodiment, the common
400 line com and 800 segment line seg
Can be driven one by one.
And 16 segment lines Fseg are arranged on both sides.
Is driven collectively as described above. (4.9.2) Display Driving Mode In this embodiment, the display 100 is driven as follows.
You. The effective display area 104 is described in (3.5) above.
As mentioned, in block access mode,
A block erase is performed, and then a line-by-line write is performed.
It is. In the line access mode, the line
Only writing is performed every time. In this example, the area 104
During block erase in block access mode
Line writing in the same mode
Drives with different waveforms when writing in line mode
I do. In the line access mode, the temperature range 45
According to ℃ ~ 35 ℃, 35 ℃ ~ 15 ℃ and 15 ℃ ~ 5 ℃,
Write in three waveforms, A waveform, N waveform and C waveform, respectively
Do just that. The correspondence between these modes and the reference drawings is as follows
It is. At block erase in block access mode → FIG. 26 (A), (B) and FIG. 27 At line writing in block access mode → FIG. 28 (A), (B) and FIG. 29 45 ° C. in line access mode ~ 35 ℃ range → Fig. 34 Range of 35 ℃ ~ 15 ℃ in line access mode → Fig. 30 (A), (B), Fig. 31, Fig. 32, Fig. 33
(A) and (B) Range of 15 ° C. to 5 ° C. in the line access mode → FIG. 35 The frame 106 is located along the frame common line Fcom.
Frame (hereinafter referred to as horizontal frame) and frame segment line Fseg
At a different time from the frame along the
Drive with different waveforms. That is, it is effective for the horizontal frame
When the display area is not accessed (for example, during refresh driving)
In the vertical blanking period, the timer is used for partial rewriting
Line Fcom and lines Fseg and seg at interrupt)
The vertical frame is formed by driving
Common line com when writing lines
Frame segment line Fseg with a waveform that matches the drive waveform of
By driving, formed in cooperation with common line com
To be done. (4.9.3) 1H = 1H ^* In this embodiment, the drive waveform of the effective display area
When erasing a block, writing a line in the same mode,
1 when N waveform in access mode is selected (in the range of 35 ° C to 15 ° C)
The horizontal scanning period (1H) is divided into three, and each ΔT period
V1, VC or V2 are on the common line com
So that V3, VC or V4 is supplied to the printer line seg.
Drive. Table 1 shows the data in the register section 630 of the data output section 600.
An example of data set in the register areas CL1 to SC2 is shown. table
In this example, “x” indicates an unused bit.
When starting the procedure described later with reference to the figure, the register
6th to 4th bits and 2nd to 0th bits in the range CL1 to SB2
The specified data shown in Table 1 is expanded to
To And on the other hand, in the process of executing the procedure
Block access to register area DM in drive mode as appropriate
Block erase in mode and write in mode
Line writing and line writing in line access mode
The multiplexer 671 discriminates between the registers CB1 to SB
2.Select register CL1 ~ SL2 or register CC1 ~ SC2
And multiplexers 665 and 669
Switching, bit 6 to 4 or bit 2 to 0 is selected.
To output one bit sequentially for ΔT.
Data. Tables 2 and 3 show the common drive elements, respectively.
Table 310 and the segment drive element truth table.
Show. In these tables, “x” means “1” or “0”.
If the selected drive voltage V is not affected by the deviation,
It is. In Table 3, Q is a 1-bit image data.
Data, ie, the latch 231 of the latch section 230 (see FIG. 22).
Is the image data output from
However, it is assumed that black data is output when Q = 1. FIG. 26A shows the contents of the registers CB1 and CB2 (first
Table C) and the waveforms of signals CEN, ▲ ▼, CM1, CM2
In the logic of the common drive element 310 (see Table 2)
Therefore, the waveform of the voltage signal V applied to the common line com
And FIG. 4B shows registers SB1 and SB2.
SEN, ▲ ▼, SM according to the contents of (see Table 1)
1, SM2 waveform and segment drive element 210 logic
(See Table 3) Apply to segment line seg
And the waveform of the applied voltage signal V. Therefore, when erasing a block in the block access mode,
Is the element selected by the chip select signal ▲ ▼.
In accordance with the signals CA5 and CA6 for driving the
Common line com and segment line seg in lock
Where the difference between the applied voltage to each line
Minute, that is, the composite waveform of the voltage signal as shown in FIG.
Will be added. And over the period ΔT
The information of the corresponding block is determined by the value of the applied voltage 3V0.
All are cleared to white data. At this time, ΔT or 1H and the voltages V1 to V4, VC
The correction according to the temperature is as described above. FIG. 28 (A) shows the contents of registers CL1 and CL2.
The waveform of each signal CEN etc. and the logic of the common drive element 310
Voltage signal V applied to the common line com by the
And the waveform of FIG. FIG. 3B shows the registers SL1 and SL2.
The waveform of each signal SEN etc. according to the contents of
Logic of element 210 and contents of image data (Q)
Shows the waveform applied to the segment line seg
You. Therefore, when writing a line in the block access mode
Corresponds to the chip select signal ▲ ▼ and signals CA5 and CA6.
The signal C at the more selected block of element 310
Common line com and segment selected by A1 to CA4
At the intersection with the line seg, see Fig. 29 (A) or (B)
Will be added. This
Here, at the point where the waveform shown in FIG.
Does not change the display data. That is,
A state in which white data was obtained by the previous block erase
Hold. On the other hand, a waveform as shown in FIG.
In that it is applied over the first period ΔT
White data can be obtained by the voltage value of 3V0.
Indication by voltage -3V0 applied over period ΔT
The data is inverted and becomes black. FIG. 30 (A) shows a line write in a line access mode.
At the temperature of 35 ° C to 15 ° C.
Each signal CEN output based on the content and setting of CC2 and CC2
Of the common drive element 310
Voltage signal applied to common line com by logic
5 shows a waveform (N waveform) of signal V. FIG.
Each signal output based on the contents of the registers SC1 and CS2
Waveforms such as SEN and the segment drive element
Logic 210 and the content (Q) of the image data.
Shows the waveform applied to the segment line seg. Note that these are normal waveforms in the temperature range.
And every one line or every few lines
When driving with inverted waveforms, the registers CC1 and CC2
Fig. 30 according to the signal CEN etc.
Wave obtained by inverting the waveform to the common line com shown in (A)
What is necessary is just to output a shape. In addition, segment
The output waveform to the in-seg may be as shown in FIG. This allows the line access mode line write
The selected common line com and segment line s
At the crossing point with eg, the electric current shown in FIG.
A composite waveform of the pressure signal is added. Here, FIG. 31 (A)
At the point where the voltage signal with the waveform shown in
Applied over the period ΔT and the next period ΔT
The conditions for obtaining white data are determined by the voltages 2V0 and V0
When the voltage exceeds the threshold value and the voltage V4 applied during the last period ΔT is black,
The display is white because it does not exceed the threshold for data acquisition conditions.
You. Also, at the point where the waveform shown in FIG.
The display becomes white in the first 2ΔT period, but the last period ΔΔ
The display is inverted by the voltage -3V0 applied to T, and the black
Data will be displayed. FIGS. 32 and 33 (A) and (B)
The inverted waveform and the composite waveform when Q = 0 and Q = 1
And the composite waveform at the time.
Also obtained white data and black data, respectively. (4.9.4) Drive waveforms including in-line inversion Fig. 34 (A) to (E) show drive waveforms in the temperature range of 45 ° C to 35 ° C.
(A) shows the waveform applied to the common line com.
A waveforms (B) and (C), respectively, have Q = 1
And supplied to the segment line seg according to Q = 0
Waveform. The waveform A is basically shown in Fig. 30 (A).
The combination of the N waveform and the inverted waveform
And the normal waveform I 'and the inverted waveform I are 3
1H at ΔT ^* Is configured. And between these waveforms
Short rest period, for example 1H ^* 3H ^* At 1H, ie 1
A horizontal scanning period is configured. The value of ΔT depends on temperature conditions
The setting data (TCONRL) of timer TMR2 from ROM503
It is set appropriately by reading. FIGS. 3D and 3E correspond to waveform A in FIG.
And (B) and (C) as shown in the segment line seg.
By adding waveforms, black data and white
Indicates that the data is to be displayed.
The part that has been involved in writing. These and Fig. 30 ~
Compared with the case of Fig. 33, segment line waveform and writing
The polarity of the synthesized waveform part that is to be corrected is reversed.
However, this is the case when using the A waveform compared to the N waveform.
Is based on the fact that ΔT is small.
Change the waveform applied to the registers to registers SC1 and SC2
Will be changed accordingly. FIGS. 35 (A) to (E) show the results in a temperature range of 15 ° C. to 5 ° C.
The drive waveforms are shown. In the figure, (A)
The C waveform, (B) and (C), respectively,
= 1 and Q = 0 in addition to the segment line seg
Waveforms (D) and (E) respectively have Q = 1
And composite waveform when Q = 0 (black and white respectively)
Indicates that writing is not performed in the hatched area.
It is. In the C waveform, the normal waveform I 'and the inverted waveform I
Are 2ΔT and 1H respectively ^* Constitute, for example, 1H ^* of
Combined with a pause. As shown in FIGS. 34 and 35, the A waveform and
And C waveform include in-line inversion,
Inversion is performed, and in addition, frame inversion is also performed. Now, as shown in Fig. 36, the screen at a certain point (1F)
At the m-th segment line and the scan direction sc
intersection with the (n-1) th to (n + 2) th common lines on an
"White", "White", "Black", and "Black" are displayed at points
Suppose that it was done. Scroll this on the next screen (2F)
The first line, the segment line and the n + th
Assume that the intersection with the third common line is "white".
Then, on the second floor, the segment line and the (n-1) to (n +) th
The display data at the intersection with the second common line is
They are "white", "black", "black", and "white", respectively. FIG. 37 shows the waveform A shown in FIG.
Drive when displaying as shown in Fig. 36 while performing inversion
It is explanatory drawing for demonstrating an aspect. For simplicity,
Here, inversion is performed for each line and each frame.
Shows the case. During the period of 1F, as shown in the upper left part of the figure,
Monline com n−1, n + 1, n + 2 has A waveform and its inverse
The inverted waveforms are sequentially added for each line. So
At this time, it is added to the segment line segm every 1H
Waveforms (corresponding to “white,” “white,” “black,” and “black,” respectively).
A), as shown in the lower left part of the figure
That a composite waveform in which writing is performed in the
And Next, in the period of 2F, it is shown in the upper right part of the figure
Common line com n−1, n, n + 1, n + 2 on 1F
The waveform applied to the corresponding line is inverted.
The following will be supplied. And at this time the segment line seg 1
Waveform added for each H (Data at 1F is scrolling in 2F
So that they are "white", "black", "black",
(Corresponds to "white") as shown in the lower right part of the figure
The composite waveform that is written in the hatched area is
Will be obtained. (4.9.5) Temperature and ΔT in line access mode
Fig. 38 shows the temperature in line access mode and its relation to V.
FIG. 39 shows an example of the relationship with ΔT selected according to the temperature.
An example of the relationship between the degree and the V value selected according to the degree is shown.
In any case, the waveform is A in the range of 45 ° C to 35 ° C,
N waveform in 15 ℃ range, C waveform in 15 ℃ ～ 5 ℃ range
This is the case where driving is performed. The solid line in FIG. 40 shows the case where the driving is performed in this manner.
FIG. 3 is a diagram illustrating temperature and responsiveness of a screen. Used by the applicant
Display element CS1017 (manufactured by Chisso) has a temperature range of 45 ° C to 5 ° C.
Driving while properly changing ΔT and V with only N waveforms
Is performed over 18 to 3 Hz as shown by the broken line in the figure.
Responsiveness changed, but the waveform, ΔT and
When the V is changed, the response is almost 8H as shown by the solid line in the figure.
could be averaged to z. (4.9.6) Mode of frame drive In this example, as described above, the horizontal frame is
During the flyback or periodically, the same as when the A / D converter
Sometimes, the vertical frame is the line of the effective display area 104
Formed at the time of writing. Also, the frame is behind the effective display area 104.
Same color as scenery, ie white when displaying information in black
To be provided. Table 4 shows the frame formation by switching the frame drive unit 700.
To register FV1, FCVc, FV2, FV3, FSVc and FV4.
Indicates the data to be set. Here, the frame common line Fcom
Is almost independent of the driving of the effective display area 104.
Data ▲ ▼, ▲ ▼ and
And ▲ ▼ are not changed. In this example, the frame
Drive data for common line Fcom for horizontal frame formation
Same as the drive waveform of common line com shown in FIG. 26 (A)
Make settings so that a new waveform is obtained. On the other hand, the frame segment line Fseg
During writing and during line writing in block access mode.
When forming a vertical frame, and in line access mode.
Frame common line Fcom or common line
Since the driving waveform of Incom is different,
Registers FV3, FV4 and FV4 so that white data is displayed.
And FSVc change settings. Specifically, drive data of the frame segment line Fseg
When forming the horizontal frame, the segment shown in FIG.
A waveform equal to the drive waveform of the line seg is
When forming a vertical frame during line writing in
When Q = 0 of the segment line seg shown in FIG.
The waveform equal to the drive waveform is the line access mode line.
At the time of vertical frame formation at the time of writing, FIG.
The segment line se shown in FIG. (C) or FIG. 35 (C)
A waveform equal to the drive waveform when Q = 0 for g is obtained.
Make the change settings as follows. As a result, the horizontal frame is driven by the waveform shown in FIG.
The vertical frame is set to block access mode.
In FIG. 29 (A), the line access mode
In FIG. 31, (A), FIG. 33 (A), and FIG.
(E) or driven by the waveform shown in FIG. 35 (E) to form
Will be done. (5) Display control (5.1) Outline of control procedure There are two main features of the display control according to this example. Into one
From the display control device 50 to the word processor 1
Data transfer and display screen 10 by sending Busy signal
Synchronization with the operation of 2. This is essentially
Is that the display element using FLC makes the operation effective.
1 horizontal scanning period is changed according to temperature
It is due to Two, normal word processor only image data
Sequentially, periodically and continuously (so-called refresh mode).
Word processor in this example,
The body 1 is driven by such data before the image data
The address data to specify the pixel to be
In addition, refreshing these data
Not specific code but specific part by address data
Capable of transferring and driving image data
It is. This is because the display element using FLC has memory
Access only those pixels that need to be updated
It is because it suffices. Note that, in order to enable the above display control,
The word processor 1 has a normal word processor.
In addition to receiving the Busy signal,
Stop transfer, and transfer address data horizontally, for example.
It has a function of transferring the signal on the initial signal. Effective in the above display control, especially the second feature
, The following two display control forms
Will be implemented. That is, block access and line access
You. Block access means that, for example, 20 scan electrode lines
One block, one block of the effective display area 104
Erase the surface at once, and call this block all white, for example.
In the following, information access is sequentially performed for each scanning line of a block.
And write characters and the like. In contrast
In line access, access is performed for each scanning line,
And write all the information in advance.
And not. These display control modes are shown in the program flow.
FIG. 41.Hereinafter, referring to FIG. 41, in the present example,
The outline of the display control will be described. In FIG. 41, first, the power of the word processor 1 is turned on.
When the power source is turned “ON”, the INIT routine is automatically started (step S10).
1). Here, set the Busy signal to “ON” and turn on the power.
Drive the respective frames 106, erase the effective display area 104, and
And the temperature compensation for it is performed.
Interrupt request ▲ ▼ or ▲ ▼ as F "
Wait until comes. This interrupt request ▲ ▼ or ▲
▼ indicates address data from the word processor 1
Data is transferred,
If the address data does not come, the program will not be executed,
It remains on the display screen 102. Next, address data is transferred and an interrupt request is
Then, this internal interrupt request is ▲ ▼ or there is
Or ▲ ▼, according to the procedure of step S102.
If ▲ ▼, go to the LSTR routine, ▲
If it is ▼, proceed to the BSTART routine. This branch
Depending on the block access or line access described above
Or break up. In other words, if you proceed to the LSTR routine,
Access to the BSTART routine and block access
Becomes By the way, ▲ ▼ or ▲ ▼ setting
In this example, the appropriate parts of the display control device body 50
Is manually performed in advance by the switching means 520 disposed in
You. The switching means 520 switches to the line access mode.
When ▲ ▼ occurs, the following program is executed to proceed to the LSTR routine.
Is performed. First, before proceeding to the LSTR routine, step S103
Based on the temperature compensation data obtained in the INIT routine,
Line access mode of the lookup table shown in Fig. 12
Data, and write to the register TCONR of the timer TMR2.
Set system clock data for access. Next, in step S104, the frame counter FCNT, line
Set the counter LCNT and the waveform recognition register CX.
Here, the frame counter FCNT and the line counter LC
NT is drive waveform every N frames and every M lines
Is a counter provided to invert the
Shape recognition register CX changes drive waveform according to FLC temperature
This is a register provided for That is, this book
In the step, the drive waveform for every frame and every line
Is set to be inverted, and temperature compensation at INIT
Which of the three waveforms described below
Is calculated, and the data is set in the register CX.
The data setting in the register CX is based on the temperature data
It may be performed by referring to a table. Steps
In S105, based on the temperature data, the line actuator shown in FIG.
Refer to the jumping table for Set
Routine LSTRA0, LST corresponding to shape, N waveform, C waveform
It is determined whether to proceed to RN0 or LSTRC0. Hereafter, one of the above three routines, followed by
Line write by executing the following routine
Do. This line writing is performed frame by frame and line by line.
Further, the waveforms A and C are driven within one horizontal scanning period.
This is performed by inverting the polarity of the dynamic waveform. Program execution is the last line access of the frame.
To the routine, write the last line,
Next, update the frame drive and temperature compensation data, and
Signal to “OFF” and wait for an interrupt request ▲ ▼. Percent
Whether to change the drive waveform when there is a
Judgment is made and the LSTR routine corresponding to the waveform is started again
Is done. On the other hand, the block access is performed by the switching means 520 described above.
Address mode, the address data transfer
Then, when ▲ ▼ occurs, the BSTART routine is started. Here, the Busy signal
Turn “ON”, read the transferred address data, and start
If the data is the first line of the block or
Judge whether it is the last line or a line other than the above
(Steps S107 and S108). Here, the address data
If the data is the first line and not the last line, branch to the LINE routine. Here, the transferred image
Line writing for one line is performed based on the data. Next
Then, set the Busy signal to “OFF” and wait for an interrupt request (
Step S109). Here, the internal interrupt request ▲ ▼
If there is, the BSTART routine is started again. In step S108, the address data is
If it is the last line, execution branches to the FLINE routine. Here, one line
Line writing is performed. Next, frame drive and temperature
Update the compensation data, set the Busy signal to “OFF”,
Wait for an interrupt request (step S110). Where the interrupt
BSTART routine starts again when there is a request ▲ ▼
Is done. In step S108, the address data is
If in, execution branches to the BLOCK routine. Here, the address
Erase all blocks to which the line specified by the
The area of such a block is set to “white” (step S11)
1). Next, proceed to the LINE routine (step S109), and
The same processing is performed. Follow the procedure described above to
Perform display control in lock access mode and write information.
Perform Also, the word processor 1 outputs a power down signal ▲
When ▼ is sent to the control unit 500,
The non-maskable interrupt request NMI is generated and PWOFF
Is started. Here, set the Busy signal to “ON” to enable
The display area 104 is erased and all areas are set to “white”.
You. Next, the power status signal and the Busy signal are
F ", which shuts off the power of the word processor 1
It is turned off (step S112). As is clear from the above, two types of display control
Configuration, i.e., block access and line access
Address data, no matter what form of
Are sequentially, periodically and continuously over the entire effective display area.
When it is transferred to
Also, address data of a certain predetermined part is intermittently transferred.
If so, the partial rewriting drive is performed. Note that the details of the control procedure described below
Address data and image data are read from the body 1 side.
The explanation is based on the premise that data is transferred in the refresh mode.
Do. (5.2) Details of control procedure (5.2.1) Power on (initial) When the power of the word processor 1 is turned on,
42 and 43 for automatically started processing
This will be described with reference to FIG. FIG. 42 shows a flowchart of a process to be started,
This is the INIT routine described above with reference to FIG. Fig. 43
Is the type of the INIT routine and the PWOFF routine described later.
A control chart is shown below for each step.
The processing performed by 0 will be described. S201: Set the power status (P ON / OFF) signal to “ON”, and
The signal Light is set to “OFF”, and at the same time,
The Busy signal to “ON” and output to the word processor 1
Power. While this Busy signal is being output, the word processing
No address data is transferred from the processor body 1. this
Is one horizontal scan to drive the FLC display element effectively
This is because the period is changed depending on the temperature. You
That is, the FLC display element driving time in the effective display area 104,
Data transfer time from the word processor 1, in other words
Synchronization with the VRAM operating time in the word processor 1
Cannot be completely removed, so the display control device
By synchronizing by outputting a signal
There is (Fig. 43, time point: only numbers are shown below). S203: A predetermined area in the register section 630 of the data output section 600 is
Drive waveform generation system for period frame drive and effective display area drive
Set control data. This is stored in the ROM 503 in the control unit 500.
Table 1 and Table 4 are used to store the stored waveform generation control data.
Set in the register section 630 of the data output section 600 as shown in
It is. S205: Drive voltage value for initial frame drive and one horizontal scan period
The data of each of the basic system clocks of D /
Registers in timer TMR2 of A conversion unit 900 and control unit 500
Set to star TCONR. In addition, block access and line
Access and block on power on / off
Set basic time data for each access. S207: The control unit 500 sends the frame from the data output unit 600 to the frame drive unit 700.
The drive control data is transferred, and based on this, the frame drive unit 700
Frame drive is performed. With this drive, the image quality of the frame 106 is reduced.
Good, and keep the display screen 102 in good condition at all times.
One. This is because while driving the effective display area 104,
The voltage is also applied to 06, the light transmittance changes, and the
This is to prevent the image quality from deteriorating due to partial turbidity.
You. In the present example, the frame 106 is “white (from the light source FL).
), The effective display area 104 is set to “white”.
(Light transmitting state) "and character information etc. in" black "
Shall be displayed. Note that "black" in these displays
And the definition by "white" is not limited to the above example,
The display in which “black” and “white” are inverted, or the frame 106
The display for distinguishing between the display area and the effective display area 104 is also provided according to the present embodiment.
It is possible depending on the location. The frame driving in step S207 is performed during one horizontal scanning period.
In the meantime, in FIG. 2,
A frame transparent electrode 150 disposed on the lower glass substrate 120 and
The segment electrode 124 and the upper glass substrate 110
Voltage signal to the common electrode 114 and the parallel transparent electrode 151 for the frame.
Signal is applied to drive. Therefore, the drive of all the frame parts
The remaining frame (vertical frame) is not
The operation is performed by clearing the effective display area 104 described later in step S213.
This is done by using a common electrode at the same time. In this step, the A / D
Conversion is performed. Such A / D conversion is detected by the temperature sensor 400.
Ambient temperature information of the displayed display screen 102, that is, FLC temperature
The information is read by the A / D converter 950 and converted to display data.
To convert (time and). S209: Perform temperature compensation. That is, the A / D conversion obtained above
Reads the data and reads the data stored in the ROM 503 in the control unit 500.
Refer to the backup table (Fig. 12) and perform temperature compensation.
Drive voltage V, system clock and delay data
Can be The above process is described in detail below with reference to FIG.
I do. Fig. 44 shows A / D conversion data with drive voltage V, 1 horizontal scanning period
Between the basic system clock and each delay time
Algorithm and look-ahead for each conversion
Table, for example, the temperature data shown in FIG.
It is assumed that the data 80H is obtained. This 80H is in the table
This indicates the lower bits of the address.
In conversion, analog temperature data is
Scan to convert to digital temperature data corresponding to
Is going. Here, the arithmetic unit ALU of the control unit 500 stores the data 0080H
The drive voltage data table area (data related to the D / A converter)
E9 equivalent to the address upper bit data of
Offset 00H. This allows the index cash register
The content of the star IX is E980H, and the data corresponding to this address is
Data. D / A conversion of this temperature compensated drive voltage value
Output to the power controller 800 via the
You. Next, the arithmetic unit ALU operates under the index register IX.
The high-order bit data is 1, leaving the high-order bit data unchanged
Incremented and the content is set to EA80H. this
Is the address of the system clock table in the table
, Thereby obtaining temperature-compensated data.
The system clock data that is the basis of this one horizontal scanning period
Data to the timer TMR2 time constant register TCONR.
Set. By the same processing, block access and write
Access and block access at power on / off
Each delay time data in the
Set the TMR1 registers CNTB, CNTL, and CNTBB.
You. S211: The drive start time of the effective display area 104 is synchronized. sand
In other words, the access start on the program and the actual effective display area
In order to completely synchronize the start of
For example, the rise of the clock output pulse Tout of the TMR2
When the edge comes, the CPU internal interrupt of the control unit 500
Apply request IRQ3. This allows the actual display area to be
Driving starts (time). S213: Deletion of the effective display area 104, that is, the entire area is
In this case, it is all “white”. This is compatible with the previous frame drive.
The display screen 102 at power-on
And Erasure of the effective display area 104 is performed for each block.
For example, 20 scanning lines are driven as one block.
Therefore, one block is erased in one horizontal scanning period. In addition, this driving is performed by the
Receives image data that sets the effective display area 104 to “white”
It is not performed by a predetermined block erase waveform,
As described above, by automatically setting
Is performed. This allows power-on
/ Erase the effective display area when off. S215 One horizontal scanning period is adjusted. That is, register CN
Set the TBB delay data in the counter, and
Timer TMR1 counts its own clock pulse based on
You. This enables the effective display area 104 and
Adjusted one horizontal scanning period between the specified time and the specified time
At this point, an internal interrupt request IRQ3 is generated. That is, the timer TMR1 is based on the base set in step S205.
Based on this time data and the temperature compensation obtained in step S209,
A predetermined time from the delay time data
When counting the time taken from a certain point in time,
This generates a section interrupt request. S216: The above steps S211, S213, and S215 are performed for each block.
, That is, each time one horizontal scan is performed. Follow
Therefore, in this step, all blocks in the effective display area 104 are
To determine whether the lock has been completed.
Returning to step S211, the above process is repeated until all the blocks are completed.
(Time). S217: All blocks (effective display area) end in step S216
The Busy signal is turned off and the word processing
The signal D can be transferred from the processor body 1. At the same time,
Signal Light is set to “ON”. At this time, a word processor book
The operator of the body 1 turns on the power of the body 1 and then displays the display image.
The power was turned on by displaying the surface 102
However, before that,
Steps S201 to S215, especially the frame 106 and the
And the driving of the effective display area 104 are already set as initial display control.
(At the time). S219: Wait for interrupt request ▲ ▼ or ▲ ▼
One. These ▲ ▼ or ▲ ▼
Address data is transferred from the processor 1
Occurs when the
The execution of the program starts. Therefore, the address data
Run a standby program until the
Mon line and segment line are kept at the same potential,
Or it is grounded. At this time, the display screen 102
It remains stopped. Instead of this, the display device 100
Stop the power supply to the
Even if the power supply to the body is turned off and the voltage signal is turned off
Good. By the way, as mentioned above, ▲ ▼ or ▲
▼
These settings are, for example,
Word processor operator usage, word processor
Optional, performed by the operator depending on the data to be handled
It is. (5.2.2) Block access After the above-mentioned predetermined initial control (INIT routine),
Block request activated by the
The access display control is described in FIGS. 45 (A) to (D), FIG.
This will be described with reference to FIGS. FIGS. 45 (A) to 45 (D) show the ROM of the control unit 500, respectively.
503, display control stored in the form shown in FIG.
This is a flowchart of the program
It is activated at each stage of the display control. FIGS. 48 (A) and (B) show the tie of such display control.
3 shows a time chart. Set the Busy signal to "OFF" (at the time of Fig. 48:
Only), the control unit 500 in the standby state has the address
Occurs when data is transferred (at the time)
Interrupt request ▲ ▼ input (time)
Initiate the BSTART routine shown in FIG.
). Hereinafter, the BSTART routine will be described with reference to FIG.
The display control will be described. S301: Read address data. Transferred to the data output unit 600
The read address data RA / D is read into the control unit 500. S303: Based on the read address data,
After performing the address translation as described above, the jumper shown in FIG.
Of the program to be executed with reference to the ping table
Set the address. S305: The Busy signal is turned “ON” (time), and the next address data is
Reject data transfer. S307: Execute to the program at the address set in step S303
Branch (time). Here, address data RA / D
Is the block line address if the
If the last line address of the effective display area is FL
To the INE routine, if the address is other than the above,
Execution will be branched to the chin. When the BLOCK routine shown in FIG. 45 (B) is started
Performs the following processing. S309: Perform address conversion and setting. That is, data output
To registers RA / DL and RA / DU in register section 630 of force section 600
Read the transferred address data RA / D, and
As described in (4.3.3) above, based on the
Address conversion to select the line to be driven
I do. A line shown in FIG. 12 with this translated address
The address data is obtained by referring to the table. this
Registers data in the register section 630 of the data output section 600
Set to DL L and DL U. S311: The drive mode is block access. That is,
Block in the register DM in the register section 630 of the data output section 600.
Set data indicating block erase in access mode
You. S313: Synchronize the operation start time. That is, as described above
Time between the effective display area 104 and program execution
Timer TMR2 of the control unit 500 for complete synchronization of
For example, the rising edge of the clock output pulse Tout
Wait for such an edge, and an internal interrupt occurs when such an edge occurs.
Generates only request IRQ3. As a result, the output pulse Tout and the
Synchronization with program execution timing and therefore output pulse
Tout is one horizontal scanning period in the effective display area 104 and
Since it is the basis of operation timing,
Synchronization of the operation timing with the effective display area 104
Will be taken. S315: Adjust the time until the end of the image data transfer. Sand
As shown in the time chart of FIG.
Data transfer is performed immediately after address data transfer.
Waits for the transfer of the
Start Seth. Here, the image data transfer time is a word processor
From the main body 1, for example, 800 bits of image data for one scan
Assuming that the data is transferred at 4 MHz in 4-bit parallel, this transfer
40 μsec.
The time stored in the drive unit 200 is adjusted. This routine BLOCK mainly performs block erase.
Block erasure requires image data.
Transfer of image data with this routine
What we are doing is transferring data for the next line access
Because it is going. Alternatively, the image data here
Don't run the program for the same amount of time without transferring
You may do it. S317: Block erase is started (time point). This makes one water
One block in the horizontal scanning period (1H), that is, for example, scanning
Access 20 lines and mark all such blocks as “white”
You. As described above, these driving operations are performed for all “white” image data.
Instead of receiving the data
This is performed by setting an erase waveform. Also, as is apparent from FIG.
At the start of the erase operation (time), in the effective display area 104,
The last line of the previous block has been written, or
Either the vertical retrace period has expired. S319: Adjustment on a program for one horizontal scanning period. sand
That is, as described above, the access in the effective display area 104 is performed.
The flash time changes with the temperature fluctuation of the FLC display element.
The effective display area 104
When executing the program according to the length of one horizontal scanning period
Make adjustments between them. As a specific method, the timer TMR1 in the control unit 500
With its own clock, for example, address data is transferred
Time is counted from the time when the program is started (time)
When the predetermined time has elapsed, the CPU 50
An internal interrupt request IRQ3 is generated at 1 and the next program
It branches to the routine. Here, the method of determining the predetermined time is as described in the above (5.2.1).
As described in step S209, the temperature compensation
The table area CNTB shown shows the program execution time and data.
The data combined with the relay time is used as the count data.
Timer TMR1 counts its own clock.
The number of events and the contents of CNTB were compared, and a predetermined value was counted.
To generate an internal interrupt request IRQ3
You. When a predetermined time has elapsed, the IRQ3
The program execution branches to the LINE routine (time). FIG. 45 (C) shows a flowchart of the LINE routine.
This routine is a continuation of the BLOCK routine.
Or directly as a continuation of the BSTART routine
Things. The following is a continuation of the BLOCK routine.
And in the explanation of each step,
The detailed description of the same processing as that described above is omitted. S321: When the LINE routine is started by IRQ3
), And perform address conversion and setting. S323: Drive mode line write in block access mode
And That is, in the register section 630 of the data output section 600,
Is set in the register DM. S325: Synchronize the operation start time. S327: Adjust the time until the end of the image data transfer. here
The image data was transferred in the previous BLOCK routine.
If there is, there is no need to perform data transfer and it is equivalent in program
May be passed without execution. S329: Start line access (time). At this point
Lock erasure ends. Image data for one transferred scan line
Data for one scanning line of the block top line
Is written, that is, displayed. S331: One horizontal scanning time is adjusted (time point). S333, S335 Busy is set to “OFF” (at the time), and an interrupt request ▲
Wait for ▼ to come, and during this time,
Not done. When address data is transferred (at the time),
Request (▲ ▼) occurs (time) and the BSTART
The chin is started (time point). Below, the BSTART routine
Next, the LINE routine is executed, and the second scan line of the block is executed.
Is written. As described above, the BSTART routine and
And LINE routines
Finish writing all scan lines and erase the next block.
And write the line. After the above processing, the last line of the effective display area 104
When the address data shown is transferred,
(D) flowchart and FIG. 48 (B) time chart
A process as indicated by the chart is started. That is, it is determined that the last line of the effective display area 104 is present.
When the indicated address data is transferred (FIG. 48 (B)
At the time of: only the numbers below), interrupt request ▲
▼ occurs (time), and the BSTART routine
Is activated (time). Here, the address data is
Because it shows the last line of the effect display area 104,
After the routine, the FLINE routine shown in Fig. 45 (D)
Is started (time point). Hereinafter, mainly referring to FIG. 45 (D) and FIG. 48 (B).
A description will be given for each step of the FLINE routine. What
The details of the same processing as described above are omitted.
Good. S336, S337, S339, S341, S343: Set Busy to “ON”, perform address conversion and setting,
Drive mode is set to line access in block access mode.
And synchronize the operation start time. In addition, image data transfer
Adjust the time until the end of transmission. S345: Start writing the last line (time). at the time
Write the second to last line in the effective display area 104
Ends. S347: Whether or not the last line writing of the effective display area 104 has been completed
Judge. If completed, proceed to the next step S349
No. This judgment is to access the last line of the effective display area 104.
This is done only when the
In the case of access, the time of access start is monitored
Only. S349: In this step, the frame drive performed in the next step
Register 630 of the data output unit 600
Set to and update the data. In addition, the frame drive system etc.
When set independently, frame drive is performed without updating data
Is also possible. However, the INIT loop shown in FIG.
For the chin, the frame drive voltage
The value is set, but vertical retrace as in this step
In frame drive performed during the period, temperature compensation is performed first in the INIT routine.
The compensated drive voltage value is used as a reference.
You. S351, S353 Driving of the frame 106 and A / D conversion are started (time). This
The vertical flyback period starts at the point of. A / D conversion ends
At the same time, based on the A / D converted temperature data,
Get value, system clock, and delay time data.
That is, the temperature compensation data is updated. In the frame driving of step S351, only a part of the frame 106 is used.
(Horizontal frame) is driven to become all "white"
(Vertical frame), the effective display area to be performed later
When driving 104, it should be performed in parallel
Is what has already been described in the description of the INIT routine.
You. However, the drive system of these frames 106 is
Assuming that the drive system is independent of the drive system of
It is also possible to do it every time. In addition, the frame 106 is formed by electric drive.
Therefore, the image quality outside the effective display area 104 is improved.
Frame 106 mechanically or painted
By covering the area outside the effective display area 104.
Of course, it is not necessary to consider the image quality.
And S355, S357: Set the Busy signal to “OFF” and request an interrupt ▲ ▼
Wait (time). As described above, the final scanning line of the effective display area 104
Write, and frame drive and temperature during the vertical retrace period immediately after
Perform degree compensation. Thereafter, the address data, that is, the effective display area 104
When the address data of the highest scanning line of
(Time), an interrupt request ▲ ▼ is generated (time
), The execution of the BSTART routine is started (time).
Hereinafter, erasure and line writing for each block are sequentially performed.
Done. (5.2.3) Line access On the other hand, the above-mentioned predetermined initial control (INIT routine)
At a later time, the
About in-access display control, FIG.
(L) and FIG. 49 (A) to (D). 46 (A) to 46 (L) show the ROM 50 of the control unit 500, respectively.
3 relates to the display control stored in the form shown in FIG.
It is a flowchart of a program, and a line access table.
It is started at each stage of the indication control. FIGS. 49 (A) to (D) show the timing chart of such display control.
Indicates a chart. In this example, the line access is
Is that there is no block erase.
The information is updated for each scanning line without erasing lines,
That is, the display is performed. Also, line access line
Writing is done line by line and frame by frame, and by 1 horizontal line
This is performed by inverting the polarity of the driving waveform within the scanning period. Less than,
The same as the processing in the previous block access display control
This will be described with a detailed description omitted. Set the Busy signal to "OFF" (Fig. 49 (A) or
At the time of (C): only the following numbers are written)
The control unit 500 receives the address data from the
Point) interrupt request generated by
Depending on (time), the LSTR0 route shown in FIG. 46 (A)
Start the application (time). This LSTR0 routine
LSTRA0 corresponding to the shape, LSTRN0 corresponding to the N waveform or
One of LSTRC0 corresponding to the C waveform,
Is selected according to the temperature of the FLC. Of these, LSTRA0
And FLC drive executed by the LSTRC0 routine and later
Indicates that the drive waveform is inverted during one horizontal scanning period.
Waveform and the normal waveform and the drive pause between them
Thus, an A waveform or a C waveform is formed. In the following description, it is inserted into the routine name corresponding to the waveform.
Characters A, N, or C may be omitted.
You. Hereinafter, referring to FIG. 46 (A), the LSTR0 routine
Display control will be described. S401: Read address data. S402: The read address data is
It is determined whether or not it is the last scan line. Last scan line data
If so, the process branches to the FLN0 routine of step S404,
For other data, branch to the LLN0 routine. The display control for the LLN0 routine is described below.
For the case of 0 or LLNC0, FIG. 46 (C) and FIG.
This will be described with reference to FIG. S410, S411, S413: Set the Busy signal to “ON” (time point),
And make settings. The drive mode is set to line access.
I do. S414, S415: Synchronization of operation start time and until image data transfer ends
Time adjustment. S416: Here, the inverted waveform of the first half is set. That is,
Inverted wave of A waveform or C waveform in Monline driving
The shape data is the contents of the register. S417: The waveform data of the register REG2 is
Output to the star CC1 and CC2 and SC1 and SC2,
Line access using the inverted waveform in the first half of one horizontal scanning period
Start (time). S418: Time adjustment for one horizontal scanning period is performed (time point). here
Indicates the line access by the inverted waveform in the first half of one horizontal scanning period.
And the line access by the normal waveform in the latter half described later.
And a drive suspension period set between them. this
Is the timer TMR1 register CNTB and CNTL delay time.
In this example, one
Using the CNTB and four CNTL delay time data
To form a rest period. S419, S421, S422, S423: Here, steps S411, S413, S414, S415 and
A similar process is executed, but the time adjustment process of step S423 is performed.
Indicates that the data transfer has already been completed,
No execution for the same time as the management. S424: Similar to the process of step S416, the second half
Set the normal waveform. That is, A waveform or C
Let the normal waveform data of the waveform be the contents of register REG2.
You. S425: After one horizontal scanning period as in the process of step S417
Start line access with half normal waveform (time
point). By the processing in step S417 and this step,
Writing with a waveform interposes a pause in one horizontal scanning period
It is done in either the first half or the second half. S426: Wait for a predetermined time to adjust one horizontal scanning period
When an internal interrupt request IRQ3 occurs (time),
LINVA0 or LINVC0
Proceed to routine. Hereinafter, referring to FIG. 46 (I) and FIG. 49 (A), LI
The NVA0 and LINVC0 routines will be described. S430, S431: Set Busy signal to “OFF” (time), interrupt request ▲
Wait for ▼. S432, S433, S434: Address data is transferred (at time), interrupt is required.
When the request ▲ ▼ occurs (time), the line count
Data LCNT is 0 or not, and if affirmative, step
Proceed to S433 to reset the line counter LCNT, and
Or go to LSTRC1 routine. If a negative determination is made, the process proceeds to step S434 and the line count
Decrement the contents of the LCNT by 1 and set it to LSTRA0 or LSTR
Return to C0. In step S402 of the LSTR0 routine, the transferred address is
Is the last scan line of the effective display area 104
When it is determined that the process is complete, the process branches to the FLLN0 routine. Hereinafter, referring to FIG. 46 (E) and FIG. 49 (B),
The display control of the FLLN0 routine will be described. S440, S441, S443: Turn the Busy signal “ON” (at the time of Fig. 49 (B):
Only) and address conversion and setting are performed. Ma
Also, the drive mode is line-accessed. S444, S445: Synchronization of operation start time and until image data transfer ends
Time adjustment. S446: Inverted waveform of the first half as in step S416 described above
Set. S447: One horizontal scanning period before as in step S417 described above.
Start line access with half inverted waveform (at time
). S448: Time adjustment for one horizontal scanning period is performed (time point). here
Forms a drive suspension period as described above in step S418
I do. S449, S451, S452, S453: Perform the same processing as steps S441, S443, S444, S445S described above.
To be executed, but the time adjustment
Data transfer has been completed, so it is the same as step S445
It is not executed for a while. S454: Similar to the process in step S446, here
Set the normal waveform. S455: After one horizontal scanning period as in the process of step S447
Start line access with half normal waveform (time
point). S456: Writing of the last line of the effective display area 104 has been completed
It is determined whether or not. If completed, proceed to the next step S457
Proceed to. S457: In this step, the frame drive performed in the next step
Set the waveform control data for S458, S459: Driving of the frame 106 and A / D conversion are started (time). This
At the time of writing of the last scanning line of the effective display area 104
Finished. At the same time as the end of A / D conversion, temperature compensation data
Update. When the processing in step S459 is completed, the program
Proceed to NVA0 or FINVC0 routine. Hereinafter, referring to FIG. 46 (K) and FIG. 49 (B), the FI
The NVA0 or FINVC0 routine will be described. S460, S461: Set Busy signal to “OFF”, interrupt request ▲ ▼
Wait (time). S462: Address data transferred (at time), interrupt request
When ▲ ▼ occurs (time), the control routine is changed.
It is determined whether or not to change. That is, the last final scan line
Waveform recognition based on temperature data of temperature compensation performed after access
Calculates the contents of the knowledge register CX and compares it with the previous contents of CX.
Compare. If the comparison shows a difference, change the control routine.
Returning to step S104 described above with reference to FIG.
One of the routines according to the new waveform in step S105
select. If not, the process proceeds to step S463. Thus, in the FLC display control by line access,
When the temperature condition of the LC is detected, the temperature range
If the drive waveform has been changed,
It is intended to perform appropriate display control. S463, S464, S465: Here, it is determined whether or not the frame counter FCNT is 0
You. If the determination is affirmative, the process proceeds to step S464, where the frame cow
Resets the line and line counters and the LSTR1 routine
Proceed to. This LSTR1 routine and subsequent routines
As shown in FIG. 46 (B) in its entirety,
The LSTR0 routine and its entirety shown in FIG.
And a routine almost similar to the routine that follows.
The difference is that line access by the LSTR0 routine is
Inverted waveform in the first half of line access, normal wave in the second half
The first half is a normal waveform and the second half is
Accessing the half with an inverted waveform. LSTR1 luch
The routines LLN1, FLLN1, LINV1 and FINV1 that follow
46 (G), 46 (H), 46 (J) and 46.
Each of them is shown in FIG. As described above, for example, the frame counter FCNT
And if the value of line counter LCNT is set to 1,
If the value of the line counter LCNT is set to 1,
Writing is performed in the first half of one horizontal scanning period.
If so, the next scan line is written in the first half,
In the following, writing is performed alternately in the first half or the second half.
Go to the last scan line. And in the next cycle,
The scan line written in the first half of the cycle is the second half
Scans that were written in the second half of the previous cycle
The lines are respectively written in the first half. In line access using N waveforms, one horizontal scanning period
The polarity inversion of the waveform is not performed within the interval. But I mentioned above
Frame counter FCNT and line counter LCNT
By setting the value appropriately, the frame corresponding to that value
The polarity of the waveform is inverted for each system and for each line. Hereinafter, the display control according to the N waveform will be described with reference to FIG.
(F) and explanation with reference to FIGS. 49 (C) and (D).
I do. Routines different from the routines described so far
Are LLNN0 and 1, LLNN0 and FLLNN1, and LLNN0 and
And one routine are as follows: S470, S471, S474, S475: These processes are the same as those described above.
That is, the Busy signal is turned “ON” (at the time), and the address conversion and the
And make settings. Next, change the drive mode to line access.
And synchronize the operation start time. End of image data transfer
Adjust the time until completion. S475-1: Here, the waveform is set. That is, N waveform data
Register contents. However, in the LLNN0 routine
The waveform data to be set is normal waveform data,
In the LLNN1 routine, it is inverted waveform data. S476: Register waveform data in register C of data output unit 600
By outputting to C1 and 2, SC1 and 2,
Start line access with full waveform or inverted waveform
(Time). S477: One horizontal scanning period is adjusted. After the processing described above, the program execution is LINVN0 or
Goes to the LINVN1 routine. These routines are described above
Since it is the same as LINVA0 or LINVA1, its explanation is omitted.
You. According to the above routine, the operation using one line of N waveform
Access and repeat line access sequentially for the last line
Going to, the FLLNN0 or FLLNN1 routine is started. Hereinafter, referring to FIG. 46 (F) and FIG. 49 (D)
The routine will be described. S480, S481, S483, S484, S485: These processes are the same as those described above.
That is, the Busy signal is turned “ON” (at the time), and the address conversion and the
And make settings. Next, change the drive mode to line access.
And synchronize the operation start time. End of image data transfer
Adjust the time until completion. S485-1: Waveform setting as described above in step S475-1
I do. However, the waveform to be set in the FLLNN0 routine
The data is normal waveform data, and the FLLNN1 routine
Is inverted waveform data. S486: Normal waveform as described above in step S476
Alternatively, start line access with the inverted waveform (at time
). S487, S488, S489, S490: In these steps, first of all,
Judge whether line writing is completed or not, and
Set waveform control data for frame drive in the next step
You. Next, driving of the frame 106 and A / D conversion are started (at the time
). Update the temperature compensation data at the same time as the end of A / D conversion.
And proceed to the FINVN0 or FINVN1 routine. The FINVN0 and FINVN1 routines are shown in FIG.
Since it is the same as the routine described above with reference to FIG.
Description is omitted. (5.2.4) Power off The operator of the word processor 1 operates the key
If you perform an operation to turn off the power,
The PWOFF routine related to the time display control is started. The following is a time chart shown in FIG. 43 and FIG.
Referring to the flowchart, the display control will be described.
I will tell. When the operator operates the keys etc. to turn off the power
From the word processor 1 to the control unit 500
▼ A signal is sent out, which causes the CPU 501 of the control unit 500
Receives a non-maskable interrupt request NMI and PWOFF
The routine is activated. This interrupt request NMI is unconditional
This is an interrupt and what kind of processing the control unit 500
Even if there is, the following processing is immediately started. You
That is, S501: Set the Busy signal to “ON” and set the Light signal to “OFF” at the same time.
(At the time of Fig. 43: only the numbers below). S503: Synchronize the operation start time. This is the same as described above
This is the process. S505: Driving of the effective display area 104 is started (time). this
Driving is performed by one horizontal scan as in the INIT routine.
In the period, one block of the effective display area 104 is erased.
It is. By such driving, the entire area of the area 104 is
Set to "White" and improve its image quality to prepare for the next display
Things. S507: One horizontal scanning period is adjusted. This processing has already been described
It is the same as S509: The above steps S503, S505 and S507 correspond to one block.
Since this process is performed every time the data is deleted,
All blocks, that is, all of the effective display area 104
It is determined whether the erasure has been completed. S511: When it is determined that the processing has been completed in step S509 (at the time
), The power status (P ON / OFF) signal to “OFF”
At the same time, the Busy signal is also turned "OFF" (time). P above
Word processor main unit 1 by ON / OFF signal “OFF”
The power supply of the entire display device including is shut off (time point). (6) Effects of Embodiment According to the above embodiment, the following effects can be obtained.
It is. (6.1) Effect of frame formation When a display device is composed of FLC elements,
That the frame 106 is provided outside the effective display area 104 on the surface 102.
Of the FLC element corresponding to the area outside the effective display area 104
Appearance of display screen 102 caused by instability
Of the effective display area 104
In some cases, it is difficult to show, or the operator may have an illusion.
Can be prevented. Particularly, as in the present example, the electrodes for the frame are
When the frame is arranged and electrically formed, the display screen 10
(2) Place a mechanical member such as metal or plastic on the frame as a frame
Or by applying paint, etc.
Compared to the case where the effective display area 104 is mechanically divided
This eliminates the need for mechanical adjustment of the position,
Depending on the handling position of the device, it may occur due to the placement of mechanical members.
No blind spots occur. Furthermore, on the effective display area 104
Performs frame formation in the same or different color as the background color of the display data.
Flexibility when forming the frame.
Up. (6.2) Effect of temperature compensation FLC elements corresponding to the effective display area 104 and the frame 106
Drive energy (voltage and pulse width)
Compensation is made according to the temperature just before
Stable driving is possible regardless of the degree
The display reliability of the display device used can be improved. In particular, as in this example, the compensation data is updated
To perform efficient display processing.
At the same time, the temperature data detection command, that is, the A / D converter 950
The horizontal frame is driven according to the drive command.
Therefore, the display processing efficiency can be further improved. (6.3) Effect of control in response to image data input Means for waiting for pixel data input from the host device
And start the operation according to the input.
In the case of a display using a display element without memory,
Similar to the above, continuous lines are displayed regardless of whether the display contents have changed.
Not only refresh driving is possible, but also
Update the display data only when a change occurs
Discontinuous driving is also possible. Refresh drive is possible
As a result, the specification of existing host equipment needs to be almost updated.
Will not be. In addition, as a result of enabling discontinuous driving,
Power consumption can be reduced, and it can be used as a host device.
Send data only when the screen needs to be updated
It is sufficient to use the software or hardware on the host side.
The burden on the hardware can be reduced. In addition, one unit (for example, one line) of image data is input.
Send a busy signal to the host device according to the force
After that, various settings can be made after this.
Swell. In this case, the host device receives a busy signal
Only need to be added to the function that waits for image data transfer.
You. Further, in this example, the word processing as the host device is performed.
Real ad that is supplied from the
Starts / stops operation according to the presence / absence of address data.
And access based on the actual address data
Part by recognizing the block or line to be
Rewriting is also possible, and furthermore,
Temperature compensation data can be updated during the vertical flyback period.
You. (6.4) Effect of disposing display drive unit Electrodes (common co) provided on display 100 composed of FLC elements
m, segment line seg, frame common line Fcom, frame
Multiple voltage supply lines and
And a switch to connect / disconnect each supply line and electrode
Switch, and switch setting
Means (Common side drive unit 300, Seg
The element-side drive unit 200 and the frame drive unit 700)
Drive the electrodes appropriately with various drive waveforms depending on the contents of the data.
Will be able to move. In the embodiment, the waveform data is appropriately set in the control process.
Can be changed and supplied.
Driving in frame formation, frame formation, screen clear, etc. to an appropriate waveform
And the image quality can be improved. (6.5) Effect of forced screen clear A table composed of FLC elements when turning on and off the power
Since the display screen 102 of the indicator 100 has been cleared,
Open the display screen 102 with the display screen 102
Start or power cut off can be easily recognized. In particular, in the embodiment, the host device side
Clear data (for example, all white data)
I was able to do it without myself
Reduces the load on the host device and speeds up clearing.
Can be achieved. In addition, the configuration that allows you to clear the screen yourself,
For example, when clearing the screen during operation,
Instead of receiving all white data from the
Control to receive only the order and clear it in accordance with this
Can also be applied effectively. (6.6) Effect of Power Supply Controller Arrangement The electrodes (line co
m, seg, Fcom, Fseg)
Therefore, an optimal voltage value should be selected according to the temperature and driving conditions.
It can be supplied to the electrodes. In particular, in the embodiment, the common side lines com and Fcom
The three voltages of +,-and the reference potential
Three-valued voltage can be applied to lines seg and Fseg
And can generate a total of five different voltage values
And Also, one value (VC) is fixed, and the other values are
Relative ratio can be set in advance, and some output
Voltage is used to determine other output voltages.
And a total of five values are generated in response to changes in some output voltages.
It is possible to adjust the voltage value appropriately according to the temperature conditions, etc.
It will be easier. In addition, the IC used for the common side drive element
Pressure is required, but the segment side drive element
Although high operating speeds are required for ICs used in
One voltage is fixed, and the relative ratio to it is maintained.
If you change the voltage as it is, the specifications of both
And the manufacturing process can be simplified. (6.7) Effects of waveform change and inversion drive Temperatures normally used in line access mode
Divide the range and for each divided temperature range
Define appropriate drive waveforms, and
Adjust pulse width and voltage according to temperature for shape
Operation, so that the operating characteristics can be averaged.
Came. In addition, as a result of performing in-line inversion, the
Since the total driving energy can be set to 0, the FLC element is stable
The state can be secured. In addition, as a result of performing MH inversion,
Or, several lines will be driven out of phase,
The author was able to prevent the swell from being felt on the display screen. In addition, as a result of performing frame inversion,
The same color data is written at the intersection of the segment lines
The timing of the insertion will be shifted. For example, in FIG.
Comparing FIG. 33 (A) with (A), the former shows a white day.
Is written in the middle part of the first half, in the latter half,
Focusing on the point of segm + comn-1 in FIG.
Data is written in the first half, and in the second half in the second half. This result
As a result, the threshold characteristics of the FLC element when written in the first half and the second half
Are combined with the threshold characteristics when written in
-The operating point on the -ΔT curve can be expanded and a margin can be obtained.
And (7) Modification (7.1) Configuration of Frame 106 In the embodiment, the frame 106 is electrically formed.
However, the present invention is not limited to this.
The part corresponding to the frame 106 of 2 is a mechanical hand made of plastic etc.
Effective without covering by steps or painting
It is not necessary to consider the image quality of the part outside the display area 104
It is also possible. In addition, frame drive is performed by electrical drive.
If the frame drive system is provided independently, the frame drive
It is also possible to take action. In addition, electrical drive
When forming a frame, use the same color as the background color as in the above example.
As well as the same color as the data color.
No. Further, in the above example, the frame transparent electrodes 150, 151 are connected to the drive units 200, 3
It is driven by the frame drive unit 700 provided independently of 00.
However, for both or one of them, the element
Drive elements similar or identical to
Drive control as part of the drive control of the drive units 200 and 300.
It may be performed. (7.2) Timing of temperature compensation and partial rewriting In the above embodiment, temperature compensation is performed during the vertical blanking period.
It was a thing. This includes address data and image data.
Data is periodically and continuously (in refresh mode)
It is possible because it was assumed to be sent
there were. However, the timing of temperature compensation is
It can be set at an appropriate time without limitation, for example,
Address data intermittently (partial rewrite mode
), The vertical blanking period
It does not exist, so temperature compensation is performed in the display control in the above example.
And the display control may be inappropriate.
is there. Therefore, when driving in the partial rewriting mode,
It is desirable to perform the temperature compensation at regular intervals. So
For example, for example, the clock with the timer of the control unit 500
Measure and apply an internal interrupt request at fixed intervals
Is set to "ON", and then temperature compensation may be performed. Note that in order to enable driving in the partial rewrite mode,
Is, in addition to the function of the word processor in the above embodiment,
Transfer specific part of address data and image data
What is necessary is just to have a function. Or address data
Data in the refresh mode as in the above embodiment.
Even if there is image data after address data,
To determine whether to activate the display control
Therefore, it is also possible. Further, the temperature compensation is in a table system as in the above example.
Instead, it may be performed by an appropriate calculation. (7.3) One horizontal scanning period and drive voltage value The temperature range as shown in FIG.
Between the wave number (that is, one horizontal scanning period) and the driving voltage value
The relationship is not limited to this, for example,
The enclosure must be narrower and the frequency and drive
Fine temperature compensation is possible by appropriately setting the dynamic voltage value.
It will work. (7.4) Waveform setting In the above embodiment, in the block access mode,
Image formation waveform data is set once in register 630
Did not update the waveform data.
Depending on the device configuration, waveforms and
It is clear that control data of 1H division number can be updated.
You. This makes it possible to generate drive waveforms corresponding to various drive conditions.
Can occur. Also in the block access mode,
In addition to selecting waveform data according to drive conditions,
Change the waveform data according to the degree and obtain the appropriate waveform.
It is also possible to In this case, for example, FIG.
In the area EA00H ~ in the same way as EE00H ~ other setting data
And store the specified data of ΔT corresponding to the temperature,
In the same manner as in the line access mode described above,
Then, the change setting of the waveform data may be performed. Waveform data
Data can be changed arbitrarily to determine the optimal waveform.
This device can also be used to perform Furthermore, in the above example, the change of the waveform data is used according to the temperature.
Is set in the program that
Set by reading using the ping table
You may. In addition, in the above example, the waveform including in-line inversion is 1H
^* A period of inactivity, but this period of
Can be set and there is no such pause
In this case, the normal waveform and the inverted waveform
Shapes can be generated. For example, in the example of FIG.
If no pause period is provided in the first 2ΔT period
V1, a wave that takes V2 in the next 3ΔT and V1 in the last 1ΔT
Can generate shapes. That is, the optical response is
Other arbitrary waveforms having different responsiveness can be generated. Sa
In addition, the drive waveforms are not limited to those in the above example.
Arbitrary waveform can be set even if it contains in-inversion
Needless to say. (7.5) Block access or line access
Select Select block access or line access
That is, interrupt request ▲ ▼ or ▲ ▼
Is selected by the operator in the above embodiment.
What is done according to the usage form and the form of the data to be written
And This is, for example, one block on the display screen 102
Is equivalent to the size of the displayed character string.
Yes, and the data to be written was only letters, numbers, etc.
Then, because it can handle each character string,
Lock access will be effective. On the other hand, the displayed image may be of various sizes.
Number, figure pattern, etc., exceeds the block size
Since display and rewriting must be performed,
Access will be more appropriate. (7.6) Number of scanning lines In the above embodiment, the number of scanning lines per block is 20
400 in the entire effective display area, but is not limited to this
In this example using an FLC display element, the number of scanning lines
Selection time / line cannot be reduced by increasing
The number of scanning lines to increase the resolution and size of the display screen.
Screening is also possible. (7.7) Erasing the effective display area 104 To reset the display screen to the initial state,
Is automatically cleared when the power is turned on / off,
Without receiving all "white" data from the processor 1
Was to do. However, screen clear is on or off.
Needless to say, either one of them may be performed. Also bro
Access control and line access display control.
When it is necessary to erase the entire
Can be erased regardless of the data
You. For this purpose, for example, the word processor 1 has
Control signals such as unconditional interrupts
Is transmitted, whereby the control unit 500 sends the effective display area 104
Erase may be performed. (7.8) Position of the temperature sensor 400 The temperature sensor 400 is used to determine the FLC temperature
Based on the cloth, properly position the distribution temperature
It is set, but more accurate temperature detection
To use multiple temperature sensors.
No. (7.9) Display 100, display controller 50, and word processor
Sessa body 1 Transfer between word processor body 1 and controller 50
Signal form, for example, signal D (signal A /, image data
Data and real address data) are limited to the above examples
Of course, it may be an appropriate one. In the above embodiment, the display related to the word processor is used.
The explanation has been given using the display and display control system as an example.
The description is not limited to the above example.
Of course, it can be applied to play and television. In addition, FLC display transmission has the property of having memory.
On existing television
Display device using a larger screen
Noh. Furthermore, the present invention provides a method for updating still images and / or screen updates.
Effective when displaying images with relatively few
is there. For example, text broadcasting and information services
Receivers, clock faces, and various device messages
When applied to a 7-segment display in the display
In this case, drive should be performed when the screen changes.
Therefore, it is a large process that contributes to power saving. In these cases, all screens may be updated when changed.
When there is a partial change, similar to the partial rewrite described above,
Then, only that part may be updated. In addition, these places
In this case, the temperature compensation can be performed by a periodic interrupt.
The screen that is updated next is the one after drive correction
Becomes If the screen update cycle is long or partial rewriting is performed
In the case of a device, it is displayed when temperature compensation is performed.
Rewrite the entire data inside by re-outputting it from, for example, VRAM
You may get. This ensures that the screen is always even
A good and good display state can be maintained. [Effect of the Invention] As described above, according to the present invention, within one driving period
The waveform applied to the scan electrode is inverted at
The waveform is inverted every drive period, and is further applied to the same scan electrode.
The supplied nth waveform and the (n + 1) th waveform are inverted.
You. Thereby, when driving the scanning electrodes and the signal electrodes,
The influence of the voltage application time on the threshold voltage of the display element
Sound can be reduced, so
Drive control can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an example of a configuration of a display device and a control system according to an embodiment of the present invention, and FIGS. 2 and 3 are display devices according to the embodiment, respectively. FIG. 4 is an exploded perspective view and a cross-sectional view showing one configuration example, FIG. 4 is a diagram for explaining a relationship between a driving voltage and an application time, and FIGS. 5 (A), (B) and FIG. 7A and 7B are diagrams showing the relationship between the driving voltage and the transmittance of the FLC element, and FIG. 8 is a diagram showing the temperature and the driving voltage of the FLC element. FIG. 9 is a diagram showing an example of a relationship between temperature, drive voltage, and frequency stored as data in a storage area of a control unit according to the present embodiment; FIG. 11 is an explanatory diagram showing block divisions of an effective display area according to the present embodiment. FIG. FIG. 12 is a block diagram showing a configuration example of a memory space in the control unit shown in FIG. 11, FIG. 13 is an explanatory diagram for explaining address conversion according to this embodiment, FIG. FIG. 15 is an explanatory diagram showing an example of correspondence between line numbers and jumping tables according to this embodiment. FIG. 15 is a block diagram for explaining a method of selecting a scanning line in this embodiment. FIG. 17 is a block diagram showing an example of a configuration of a data output unit according to an example. FIG. 17 is a waveform diagram showing signals of each unit for setting drive waveform generation in the data output unit shown in FIG. 16, and FIG. FIG. 19 is a block diagram illustrating a configuration example of an A / D conversion unit according to an example. FIG. 19 is a block diagram illustrating a configuration example of a D / A conversion unit and a power supply controller according to the embodiment. FIG. 21 is a block diagram showing an example of the configuration of a frame driving unit according to the present invention. FIG. 22 is a block diagram showing a schematic configuration example of the segment side drive element, FIG. 22 is a circuit diagram showing a detailed configuration example of the segment side drive element shown in FIG. 21, and FIG. 23 is a diagram showing a common side drive element according to the present embodiment. FIG. 24 is a block diagram showing a schematic configuration example, FIG. 24 is a circuit diagram showing a detailed configuration example of the common-side drive element shown in FIG. 23, and FIG. 25 is a simplified view of the display for explaining a drive mode of the display. 26 (A) and (B) are waveform diagrams for explaining an example of driving waveforms of common lines and segment lines at the time of block erasure, and FIG. 27 is FIGS. 26 (A) and (B). FIG. 28 (A) and FIG. 28 (B) are waveform diagrams showing combined waveforms of driving waveforms of the common line and the segment line shown in FIG. 28). Waveform diagram for explaining an example of driving waveforms of Ntorain, view the 29 (A) and (B) FIG. 28 (A) and (B)
30 (A) and (B) are drive waveforms (N waveforms) of the common line and the segment line during line writing in the line access mode. FIGS. 31 (A) and (B) are explanatory diagrams for explaining an example of FIGS. 30 (A) and (B).
32 is a waveform diagram showing a composite waveform of the driving waveforms of the common line and the segment line shown in FIG. 32, FIG. 32 is a waveform diagram showing an inverted waveform of the N waveform, and FIGS. 33 (A) and (B) are waveform diagrams showing the 32nd waveform. FIGS. 34 (A) to (E) are waveform diagrams showing composite waveforms when output, and FIGS. 34 (A) to (E) are waveform diagrams for explaining the A waveform used in a high-temperature region in the line access mode; FIGS. 35 (A) to (E). Is a waveform diagram for explaining a C waveform used in a low-temperature region of the line access mode, FIG. 36 is an explanatory diagram for explaining a display state when performing MH inversion and frame inversion, and FIG. 36 is a waveform diagram for explaining the mode of performing the driving shown in FIGS. 38 and 39, FIG. 38 and FIG. 39 are explanatory diagrams showing the relationship between temperature, pulse width, and voltage, respectively. FIG. 41 is an explanatory diagram for explaining the relationship of FIG. 42 is a flowchart showing a schematic configuration of a display control procedure according to an example, FIG. 42 is a flowchart showing an example of an initial processing procedure of the display control procedure according to the present embodiment, and FIG. 43 is an initial processing and power-off shown in FIG. FIG. 44 is a time chart for explaining the operation of the present embodiment in the processing at the time, and FIG. 44 is an explanatory diagram for explaining an algorithm for converting temperature data into drive voltage data and time data according to the present embodiment; Figures (A)-(D) and Figures 46 (A)-(L)
A flowchart showing an example of a detailed display control procedure in the block access mode and the line access mode according to the present embodiment, respectively. FIG. 47 is a flowchart showing an example of a detailed display control procedure when the power is turned off according to the present embodiment. 48 (A), (B) and FIGS. 49 (A)-(D)
FIGS. 45 (A)-(D) and 46 (A)-
FIG. 50 is a time chart for explaining the operation of this embodiment according to the display control procedure shown in (L). FIG. 50 is a schematic diagram for explaining a TN liquid crystal. FIG. 51 is a schematic diagram for explaining an SmC ^* liquid crystal. FIG. 52, FIG. 52 is a schematic diagram for explaining SmH ^* liquid crystal, FIG. 53 is a schematic diagram for explaining the structure of FLC molecules, FIG. 54 is a schematic diagram showing an example of a display element using FLC, FIG. 55 is a schematic diagram showing an example of an FLC display element applicable to the present invention, FIG. 56 is a schematic diagram showing an example of a cell having a matrix electrode structure applicable to the present invention, FIG. 57 (A) to FIG. (D) and FIGS. 58 (A) to (D) show FL.
FIG. 4 is a waveform diagram showing a waveform of a voltage applied to a C element. 1 Word processor, 50 Display control unit, 10
0 ... display, 102 ... display screen, 104 ... effective display area, 106 ... frame, 110 ... upper glass substrate, 112 ... wiring part, 114, 124 ... transparent electrode, 115, 125 ... extraction electrode, 11
6,126 ... insulating film, 120 ... lower glass substrate, 122 ... wiring part, 128 ... metal layer, 130 ... FLC sealing part, 132 ... FL
C, 134: spacer, 136: alignment film, 140: sealing material, 142: filling port, 144: sealing member, 150, 151 ... transparent electrode for frame, 200: segment side driving section, 210 ... Segment drive element, 220 shift register, 230
... Latch section, 240 ... Input logic circuit, 250 ... Control logic section, 260 ... Switch signal output section, 270 ... Driver, 30
0: Common drive unit, 310: Common drive element
340: Input logic circuit, 345: Decoder, 350: Control logic unit, 360: Switch signal output unit, 370: Driver, 380: Board, 382: Flexible cable, 384
…… conductive member, 400 …… Temperature sensor, 500 …… Control unit, 50
1 CPU CPU 503 ROM ROM 507 Reset unit 509 Clock generation unit 511 Handshake controller 600 Data output unit 601 Data input unit 603 … IRQ generator, 605 …… DACT generator, 611 …… ▲
▼ Generator, 613… FEN trigger, 619… Busy gate, 621… Device selector, 623… Register selector, 625… 22 bit latch pulse gate array, 630…
... Register part, 641 ... Real address storage control part, 643 ...
Horizontal dot counter, 645 …… ▲ ▼ Generating part, 6
50 Decoder unit, 661 Multiplier, 663A to 663D Ring counter, 665,669 Multiplexer, 667 4
Phase ring counter, 671,675 …… Multiplexer, 673
… Shift register section, 677… Output section, 680… Gate array, 690… MR generation section, 700… Frame drive section, 710,715,
720,730,735,740… Switch, 800… Power supply controller, 810,820,825,830,840 …… Variable gain amplifier, 900…
… D / A converter, 901… D / A converter, 950… A / D converter, 9
51 A / D converter, FL Light source, PORT1 to PORT6 Port part, DDR1 to DDR6 I / O setting register, TMR1, TMR2
… Timer, AB… Address bus, DB… Data bus,
com …… Common line, seg …… Segment line, Fcom
…… Frame common line, Fseg …… Frame segment line.

Claims (1)

(57) [Claims] A driving signal supplied to the scanning electrode group, which is combined with a display device having a scanning electrode group and a signal electrode group, and a ferroelectric liquid crystal display element disposed between the scanning electrode group and the signal electrode group; Supplies a drive signal having an inverted waveform within one drive period, and a drive signal having an inverted relationship every drive period and a drive signal having an inverted relationship between the nth (n is a natural number) and (n + 1) th waveforms on the same scan electrode. A display control device comprising: