JP2554104C - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]   The present invention relates to a display control device, and more particularly, to an electric field such as a ferroelectric liquid crystal element.
Display control device suitable for a display device using a display element having bistability
It is related to the location. [Conventional technology]   Conventionally, in a display device, as a liquid crystal display element using a liquid crystal compound, a scanning electrode is used.
The electrode group and the signal electrode group are configured in a matrix, and a liquid crystal compound is filled between the electrodes.
In addition, there is known a device that forms a large number of pixels to display image information.   As a method of driving this display element, a voltage signal is sequentially and periodically applied to the scanning electrode group.
In addition, a predetermined information signal is applied to the signal electrode group in parallel with the signal of the scanning electrode group.
, A time-sharing drive is applied. Such display element and driving method thereof
The problem is that it is difficult to increase the pixel density or the screen
Had a point.   That is, the response speed is relatively high and the power consumption is low among the conventional liquid crystals.
Therefore, most TN (twisted nematic) type display devices are practically used.
As shown in FIG. 50 (A), this type of liquid crystal has a positive
Nematic liquid crystal molecules with dielectric anisotropy twisted in the thickness direction of the liquid crystal layer (helical structure)
Structure), and between the two electrodes, the molecules of the liquid crystal are formed on each layer and each other and on the electrode surface.
It forms a parallel and twisted (twisted) structure. On the other hand, in FIG.
As shown in the figure, when an electric field is applied, nematic liquid crystal molecules having positive dielectric anisotropy
They are arranged in the direction of the field, so that optical modulation can occur. Using such a liquid crystal
When the display element is configured with a matrix electrode structure, the scanning electrodes and signal electrodes
The liquid crystal molecules are arranged perpendicular to the electrode surface in the region (selection point) where both poles are selected.
Is applied, and the scanning electrode and signal electrode are not selected.
No voltage is applied to the region (non-selection point), so that the liquid crystal molecules are parallel to the electrode surface.
Maintains a twisted (twisted) stable arrangement. Above and below such a liquid crystal cell
By arranging linear polarizers in a crossed Nicols relationship with each other,
Light is not transmitted, and light is transmitted at non-selected points due to the twisted structure and optical rotation of the liquid crystal. Therefore, it is possible to form an image element.   However, when a matrix electrode structure is configured, a scan electrode is selected,
Region where signal electrode is not selected, or scan electrode is not selected and signal electrode is selected
A finite electric field is also applied to the region (the so-called “half-selected point”). Selection point
The difference between the voltage applied to the half-selection point and the voltage applied to the
If the voltage threshold required to arrange perpendicular to the plane is set to this intermediate voltage value
Thus, the display element operates normally.   However, in this method, when the number of scanning lines (N) is increased, the entire screen (
The time during which an effective electric field is applied to one selected point while scanning one frame (dut)
y ratio) decreases at a rate of 1 / N. For this reason, if repeated scanning is performed,
The voltage difference as the effective value between the selected point and the non-selected point in
The smaller the number, the less image contrast and crosstalk are avoided.
It is a difficult problem.   Such a phenomenon is caused by the fact that liquid crystals used in conventional display elements do not have a bistable state.
(The liquid crystal molecules are oriented horizontally with respect to the electrode surface in a stable state, and there is an electric field.
(Vertical orientation only while applied to the effect) is driven using the time accumulation effect
(Ie, scanning repeatedly)
is there. In order to improve such problems, a voltage averaging method, a two-frequency driving method,
The matrix method has already been proposed, but none of these methods is sufficient.
Larger screens and higher densities of display elements have reached a peak due to the inability to increase the number of scanning lines.
It was a situation that was in the middle.   On the other hand, as a method for solving the above-mentioned problem, for example, Japanese Patent Laid-Open No. 59-193
In Japanese Patent Publication No. 426 or Japanese Patent Laid-Open No. 33535/1985, the present applicant
We have proposed a method for driving a liquid crystal having a bistable state. Use with above driving method
The liquid crystal that can be used is a chiral smectic liquid crystal having ferroelectricity.
Are most preferred, and among them, chiral smectic C phase (SmC^*) Or H phase (SmH
^*) Liquid crystal is suitable.   SmC^*As shown in Fig. 51, the liquid crystal molecules take a layer structure in parallel,
Has an inclination to the layer. These liquid crystal molecules tilt in different directions for each layer, The result is a helical structure.   SmH^*As shown in Fig. 52, the molecules have a layer structure in parallel,
And has a hexagonal packing structure in a plane perpendicular to the long axis of the molecule.   SmC^*And SmH^*Has a helical structure of liquid crystal molecules.
The figure is shown.   In the figure, e3 is the liquid crystal molecule, e4 is the electric dipole moment, and e5 is the layer interface.
Each is shown. Here, each liquid crystal molecule e3 is bidirectional in a direction orthogonal to its long axis direction.
Having a pole moment and maintaining a constant angle θ with the Z axis orthogonal to the layer boundary surface e5
Exercise makes up a helical structure. This figure shows that no voltage is applied.
If a voltage higher than a certain threshold value is applied in the X-axis direction,
The crystal molecule e3 is oriented such that the electric dipole moment e4 is parallel to the X axis.   SmC^*Phase or SmH^*Is the phase realized as one phase of a phase transition due to temperature conditions?
Furthermore, when these liquid crystal compounds are used, depending on the temperature range in which the display device is used,
It is preferred to select the elements.   Fig. 54 shows the above-mentioned ferroelectric liquid crystal (hereinafter referred to as FLC: Ferroelectric Liquid Crystal).
FIG. 1 schematically illustrates an example of a cell using the same. e1 and e1 ′ are In_TwoO_Two, SnO_Two
Or a substrate (glass plate) coated with a transparent electrode such as ITO (Indium-Tin Oxide)
SmC in which the liquid crystal molecular layer e2 is oriented so as to be perpendicular to the glass surface.^*Phase liquid
Crystals are enclosed. The liquid crystal molecule e3 indicated by the bold line is oriented in a direction orthogonal to the molecule e3.
It has a dipole moment e4. A certain threshold or more between the electrodes on the substrates e1 and e1 '
When a voltage is applied, the helical structure of the liquid crystal molecule e3 is released, and the dipole moment e4 is reduced.
The alignment direction of the liquid crystal molecules e3 can be changed so that they all face the electric field direction. Liquid crystal
Element e3 has an elongated shape, and exhibits refractive index anisotropy in the major axis direction and the minor axis direction.
Therefore, for example, it is arranged above and below the glass surface in a positional relationship between the orientation direction and the crossed Nicols.
Liquid crystal optical modulation element whose optical characteristics change depending on the polarity of the applied voltage when a polarized polarizer is placed
Is easily understood.   Further, when the thickness of the liquid crystal cell is made sufficiently thin (for example, 1 μm), FIG.
As shown in the figure, the helical structure of the liquid crystal molecules is released even when no electric field is applied.
Dipole moment P or P 'is either upward or downward in the figure Take. In such a cell, as shown in FIG.
When a given electric field E or E 'is applied for a predetermined time, the dipole moment is
Or the direction changes to upward or downward according to the electric field vector of E ', and
Accordingly, the liquid crystal molecules are in either the first stable state f3 or the second stable state f3 '.
Orientation.   There are two advantages of using such an FLC as an optical modulation element. First,
Second, the response speed is extremely high (1 μsec to 100 μsec).
Is to have a stable state.   The second point will be described with reference to FIG. 55, for example. When an electric field E is applied, the liquid crystal molecules e3
Is oriented to a first stable state f3, which is stable even when the electric field is turned off. Also
When the electric field E 'in the opposite direction is applied, the liquid crystal molecules e3 are oriented to the second stable state f3'.
Although the direction of the molecule is changed, it remains in this state even after the electric field is turned off. You
That is, the liquid crystal molecules e3 have a memory property. Further, the applied electric field E is constant.
As long as the threshold is not exceeded, each alignment state is maintained.   In order to achieve such high response speed and effective memory,
As thin a method as possible is preferred, generally from 0.5 μm to 20 μm, in particular from 1 μm to 5 μm.
μm is suitable.   Next, the outline of the FLC driving method will be described with reference to FIGS. 47 to 49.   FIG. 56 shows a matrix electrode structure in which an FLC compound (not shown) is interposed in the middle.
FIG. com is a scanning electrode group, and seg is a signal electrode group. Most
First, the case where the scan electrode com1 is selected will be described.   FIG. 57 (A) and FIG. 57 (B) show an example of the scanning signal, and each of the selected scanning is shown.
The electric signal applied to the scanning electrode com1 and the other scanning electrodes (scanning electrodes not selected)
Pole) shows electric signals applied to com2, com3, com4... FIG. 57 (C) and FIG.
FIG. 7 (D) is an example of an information signal, and each of the selected signal electrodes seg1, seg3,
It shows the electrical signals applied to seg5 and unselected signal electrodes seg2, seg4
.   57 and 58, the horizontal axis represents time, and the vertical axis represents voltage.
For example, when displaying a moving image, the scanning electrode group com is sequentially and periodically selected. Is done. Now, a predetermined voltage application time Δt₁Or Δt_TwoLiquid crystal having bistability against
The threshold voltage for providing a first stable state of the cell is -V_th1And the second stable state
Threshold voltage to give_th2Gives the selected scan electrode com (com1)
The obtained electrode signal has a phase (time) Δt as shown in FIG. 57 (A).₁Then 2V,
Phase (time) Δt_TwoIn this case, the alternating voltage is −2V. Selected in this way
When electric signals having a plurality of phase intervals with different voltages are applied to the scanning electrodes
The first or second liquid crystal corresponding to the optical "dark" (black) or "bright" (white) state
A state change between the second stable states can be quickly caused.   On the other hand, the other scan electrodes com2 to com5... Are applied to the cell as shown in FIG.
, That is, the reference potential (for example, the ground state). Also selected
The electrical signals supplied to the signal electrodes seg1, seg3, and seg5 are as shown in FIG. 57 (C).
V, and the electrical signals applied to the unselected signal electrodes seg2, seg4
57 -V as shown in FIG. In the above, each voltage value has the following relationship
Is set to a desired value that satisfies               V <V_th2<3V             −3V <−V_th1<-V   Among the pixels when such an electric signal is given, for example, the pixel in FIG. 56
Voltage waveforms applied to A and B are shown in FIGS. 58 (A) and (B). That is,
As apparent from FIGS. 58 (A) and (B), the pixel A on the selected scanning line
Δt_TwoAt the threshold V_th2A voltage exceeding 3 V is applied. Also, if they exist on the same scan line,
In the existing pixel B, the phase Δt₁At -V_th1Is applied.
Therefore, depending on whether the signal electrode is selected on the selected scanning electrode line or not.
When selected, the liquid crystal molecules are oriented in the first stable state, and when not selected,
In this case, it is oriented to the second stable state.   On the other hand, as shown in FIGS. 58 (C) and (D), all of
The voltage applied to all the pixels is V or -V, neither of which exceeds the threshold voltage.
No. Therefore, the liquid crystal molecules in each pixel other than on the selected scanning line change their alignment state.
The orientation corresponding to the signal state of the last scan without change is maintained
doing. That is, when a scanning electrode is selected, a signal for one line is written. The signal is output from the end of one frame until the next selection is made.
You can keep your state. Therefore, even if the number of scanning electrodes increases, the actual selection time
/ Line does not change, and no decrease in contrast occurs.   As described above, the problems with the display device using the conventional TN type liquid crystal are described.
The solution is to have bistability with respect to the electric field, and if no electric field is applied,
However, there has been a proposal for an FLC that realizes a display element that can maintain its stable state.
This has been done for the specific drive control of the display element using this FLC.
There are various characteristics to consider. [Problems to be solved by the invention]   An object of the present invention is to provide, for example, a ferroelectric liquid having bistability against such an electric field.
When a display device is configured using an optical modulation element (FLC element) such as a crystal element
, Display control device that can perform appropriate drive control while effectively utilizing its characteristics
Is to provide. [Means to solve the problem]   In order to achieve such an object, the present invention provides a matrix for forming a pixel group.
Having a scanning electrode group and a signal electrode group arranged, wherein the scanning electrode group and the signal electrode group
A display control device for driving a display device having a liquid crystal display element disposed between the
Driving means for driving the scanning electrode group and the signal electrode group, respectively,
Scan electrode driving signal for one line scanning period for driving the scan electrode group output from the stage.
Signal has at least two phases, the first of said two phases having different polarities
A plurality of pulse signals having a plurality of pulse signals, and a plurality of pulses having a polarity that is in an inverse relation to the polarity of the second phase signal;
Characterized in that it has a loose signal. [Action]   According to the above configuration, during one line scanning period for driving the scanning electrodes,
Since the electrode drive signal has two phases that are in an inverting relationship with each other, one-line scanning is performed.
The sum of the driving energies in consideration of the polarity in the period can be set to substantially zero. This
At the same time, the scan electrode drive signal has a different polarity in each of the two phases.
Having a plurality of pulses, for example, together with the signal electrode drive signal,
Writing after erasing the display in the predetermined area (line writing in block access mode) Erasing and writing the display information up to that point along with writing)
Various writing (display) modes such as line writing in line access mode)
It works. [Example]   Hereinafter, the present invention will be described in detail with reference to the drawings.   The description will be made in the following procedure.     (1) Outline of device     (2) Display configuration     (3) Overview of display control           (3.1) Display frame           (3.2) Display element drive waveform           (3.3) Display element drive voltage           (3.4) Temperature compensation           (3.5) Display drive system           (3.6) Clear display screen     (4) Configuration of each part of the display control device           (4.1) Main symbols           (4.2) Control unit           (4.3) Memory space           (4.4) Data output section,           (4.5) A / D converter           (4.6) D / A converter and power supply controller           (4.7) Frame drive           (4.8) Display driver                 (4.8.1) Segment side drive unit                 (4.8.2) Common side drive unit           (4.9) Drive waveform     (5) Display control           (5.1) Outline of control procedure           (5.2) Details of control procedure                 (5.2.1) Power on (initial)                 (5.2.2) Block access                 (5.2.3) Line access                 (5.2.4) Power off     (6) Effects of the embodiment           (6.1) Effect of frame formation           (6.2) Effect of temperature compensation           (6.3) Control effect in response to image data input           (6.4) Effect of display unit drive arrangement           (6.5) Effect of forced screen clear           (6.6) Effects of power supply controller installation           (6.7) Effect of waveform change and inversion drive     (7) Modification           (7.1) Frame configuration           (7.2) Timing of temperature compensation and partial rewriting           (7.3) One horizontal scanning period and drive voltage value           (7.4) Waveform settings           (7.5) Selection of block access or line access           (7.6) Number of scanning lines           (7.7) Deleting effective display area           (7.8) Temperature sensor position           (7.9) Display, display controller and word processor (1) Outline of device   FIG. 1 shows an embodiment of the present invention. Here, 1 is displayed on the display according to this example.
A word processor as a host device serving as a source of image data according to
You. Reference numeral 50 denotes a display control device according to the present embodiment, which is supplied from the word processor 1.
With respect to the display data and the like, drive control of the display device is performed in accordance with various conditions described later. 100
Is an indicator configured using FLC. 200 and 300 are the display controller 50 Each of the signals provided on the display 100 according to the drive data supplied from the
Segment-side drive unit that drives the signal electrodes and common-side drive unit that drives the scan electrodes
It is. 400 is provided at an appropriate position of the indicator 100, for example, at a portion exhibiting an average temperature.
It is a temperature sensor.   In the display device 100, 102 is a display screen, and 104 is an effective display area on the display screen 102.
Reference numerals 106 denote frames provided outside the effective display area 104 on the display screen 102. In this example
For example, an electrode corresponding to the frame portion 106 is arranged on the display 100, and is driven to drive the screen 102.
A frame part is formed on the upper part.   In the display control device 50, reference numeral 500 denotes a control unit described later with reference to FIG.
100 and control of transmission and reception of various data with the word processor 1. 600 is
16 is a data output unit described later with reference to FIG.
Display drive unit corresponding to the set data from the control unit 500 for the display data to be displayed.
It drives 200, 300, etc. and starts the control section 500 for data setting. 700 is a frame drive
And a frame on the display screen 102 based on the output data from the data output unit 600.
A part 106 is formed.   Reference numeral 800 denotes a power supply controller, and a word processor is controlled by the control unit 500.
The voltage signal from the main body 1 is appropriately transformed, and the display driving units 200 and 300 apply the voltage applied to the electrodes.
Generate pressure. 900 is a D / D arranged between the control unit 500 and the power supply controller 800.
A conversion unit, which converts the digital amount setting data of the control unit 500 to the analog amount data.
And supplies it to the power supply controller 800. 950 is the temperature sensor 400 and control unit 50
This is an A / D converter that is located between 0 and 0.
The temperature data is converted into a digital quantity and supplied to the control unit.   The word processor 1 sends the display data to the display device 100 or the display control device 50.
It has a function as a host device that serves as a data supply source.
Although it can be replaced with a host device such as a computer or an image reading device,
In any case, in this example, the following various data can be transmitted and received. sand
That is, first, as data supplied to the display control device 50,   D: image data, address data for specifying the display position of data, horizontal
A signal containing a synchronization signal.   The display address of the image data (corresponding to the display device on the effective display area 104) can be specified.
The address data for enabling the function is stored in a host having a VRAM corresponding to the effective display area 104.
For example, if the address data is output as it is,
Can also be. In this example, the word processor 1 converts this signal into a horizontal synchronization signal.
The signal is superimposed on the signal or the blanking signal and supplied to the data output unit 600.   CLK: Transfer clock for the image data PD0 to PD3.   The data is supplied to the data output unit 600.   PDOWN: A signal notifying that the system power is to be shut off.   It is supplied to the control unit 500 as a non-maskable interrupt (NMI). And   Further, as data that the display control device 50 supplies to the word processor body 1,   P ON / OFF: When turning on and off the system,
Status notifying that the display control device 50 has completed startup and shutdown.   Control unit 500 outputs.   Light: A signal for instructing on / off of the light source FL combined with the display device 100.   Control unit 500 outputs.   Busy: The display controller 50 performs various settings during the initial operation and the display operation.
And a synchronization signal for causing the word processor 1 to wait for the transfer of the signal D and the like. sand
In other words, in this example, the word processor 1 can receive the Busy signal.
And   The control unit 500 supplies the data via the data output unit 600. (2) Display configuration   FIG. 2 and FIG. 3 each show one configuration of the display 100 configured using the FLC.
It is the disassembled perspective view and sectional drawing which show an example. In these figures, 110 and 120 are
, The glass plates placed on the top and bottom, respectively, and the direction of orientation of the FLC element
Is provided with a polarizer disposed so as to be in a crossed Nicols state. 122 is the lower glass
A wiring section provided on the substrate 120, for example, a transparent electrode 124 such as ITO and an insulating film. Consists of 126. 128 is gold to be added on the transparent electrode 124 when it is necessary to lower the electrode resistance.
This is a genus layer, and need not be added when the display is small. 112 is the upper glass base
The wiring section provided on the plate 110, and each section 12 in the wiring section 122 of the lower glass substrate 120.
The transparent electrode 114 and the insulating film 116, etc., which are the same as 4 and 126 respectively.   The wiring directions of the wiring portions 112 and 122 are orthogonal to each other. Also, for example
The effective display area 104 has the dimensions of the A5 size, and its long side is used as the horizontal scanning direction.
If a resolution of × 800 dots is to be provided, the wiring section must correspond to the effective display area.
Is provided with 400 or 800 transparent electrode groups. In this example,
The scanning direction is set to the common side, and a group of 400 transparent electrodes 114 is
A group of 800 transparent electrodes 124 is provided in the wiring section 122. In addition, the display screen 102
The portion corresponding to the outside of the inner effective display area 104 has a transparent light for displaying a frame.
The group of poles 150 and 151 has the same or different shape as the transparent electrodes 124 and 114 for data display.
Is provided.   Numeral 130 denotes an enclosing portion of the FLC 132 for adjusting the axis of the FLC element (the Z axis in FIG. 44).
A pair of alignment films 136 and an FLC element with respect to the axis thereof are arranged in the first or second direction as shown in FIG.
Are spacers 13 for defining the distance between the alignment films 136 so as to take the second stable state.
And 4. 140 is a sealing material such as epoxy for sealing the FLC 132, and 142 is the sealing portion 13.
The filling port 144 for filling the FLC 132 into the inside of the hole 0 seals the filling port 142 after the filling.
Sealing member.   210 and 310 are the segments constituting the segment side drive unit 200, respectively.
Element and the common drive element constituting the common side drive section 300
In this example, it is an integrated circuit that drives 80 transparent electrodes.
10 and 5 are provided respectively. 280 and 380 are each segment driven
The substrate on which the element 210 is mounted and the base on which the common drive element 310 is mounted
The plates, 282 and 382, are flexible plates connected to substrates 280 and 380, respectively.
Cable 299 connects the flexible cables 282 and 382 and
This is a connector coupled to the display control device 50.   115 and 125 are the continuous electrodes formed on the transparent electrodes 114 and 124, respectively.
And are driven through film-like conductive members 384 and 284, respectively. Connected to the moving elements 310 and 210.   In this example, the light source FL disposed below the lower glass substrate 120 emits light.
Irradiates the FLC element to the first or second stable state, thereby displaying the display.
Do. (3) Overview of display control   When applying the display as shown in FIGS. 2 and 3, the characteristics of the FLC element
There are the following problems with respect to the nature, and in this example we pay particular attention to them.
Appropriate configuration of the display 100 using FLC elements and realization of appropriate drive control
Aim. (3.1) Display frame   When the display 100 is constructed as shown in FIGS.
A group of poles 114 and a group of transparent electrodes 124 on the segment side are arranged in a matrix.
The area on the display screen 102 corresponding to the range is defined as an area where image data can be actually displayed,
In other words, the effective display area 104 is used.
Outside the matrix arrangement range of the transparent electrode group on the side and at least the inside of the sealing material 140
The effective display area 104 is defined as the display screen 102 including the area corresponding to a part.
Desirable for complete visibility.   However, simply arranging the common side and segment side transparent electrode groups
In such a part, only one side of the electrode group passes, and
Therefore, the FLC of that part floats regardless of the display of the image data. Sand
In such a state, the FLC of that part can take the first or second stable state.
Therefore, an area on the display screen 102 corresponding to that part is a light-transmitting area (white) and a non-light-transmitting area.
Over-area (black) is mixed, which not only impairs the appearance of the display but also
In some cases, it is difficult to clearly indicate the effective display area 104 or an illusion may occur to the operator.
I can do it.   Therefore, in this example, the common side is also provided outside such an effective display area 104.
Or a transparent electrode crossing the segment side transparent electrode (hereinafter referred to as a frame transparent electrode)
151 and 150, and by appropriately driving them, the frame portion 106 is formed.
So that As the transparent electrode for the frame, the transparent electrode on the common side on the upper glass substrate 110 is used. The transparent area on both sides of the bright electrode 114 and the segment side on the lower glass substrate 120
For example, 16 electrodes 151 and 150 are arranged on both sides of the arrangement range of the electrode 124, respectively.
I do. In FIG. 2, for the sake of simplicity, representatives on glass substrates 120 and 110 are shown.
And only one on each side is shown. (3.2) Display element drive waveform   One of the features of the FLC display element is that it has memory characteristics.
Problems related to drive waveforms caused by the application time dependency of the threshold described later
The points and their solutions are described below.   In FIG. 56, formed at intersections of scanning electrodes com1 to com5 and signal electrodes seg1 to seg5.
Of the pixels to be shaded, the shaded pixels are in a “bright” state (white), and the pixels indicated by a white background are “dark”.
"State (black). These states are the first stability of the FLC described above.
This corresponds to the state and the second stable state. Now, the signal electrode seg1 in FIG.
Paying attention to the above display, the pixel A corresponding to the scanning electrode com1 is in the “bright” state,
All other pixels B are in the “dark” state.   FIG. 5 (A) shows a scanning signal and a signal electrode seg1 as an example of a driving waveform in this case.
And the voltage applied to the pixel A in time series.
is there.   For example, when driving is performed as shown in FIG. 5 (A), it is assumed that the scan electrode com1 is scanned.
Time Δt₁In pixel A, threshold V_thVoltage of 3V exceeding
Regardless of prior history, pixel A transitions to one stable state, the "bright" state. So
After that, while com2 to com5... Are scanned, a voltage of -V is applied as shown in FIG.
But this is the threshold -V_thPixel A keeps the “bright” state
obtain.   However, in this way one signal on one signal electrode (in this case "dark"
In the case where information is displayed in such a way as to keep giving
In addition, there is a problem that occurs when high-speed driving is required.   FIG. 4 shows this characteristic characteristically, where the drive voltage value V is plotted on the horizontal axis.
The vertical axis represents the pulse width ΔT (application time). As is clear from FIG.
, Threshold V_th(Drive voltage value) has an application time dependency, and the application time is shorter. It can be seen that the curve becomes steeper. From this, in FIG. 5 (A)
Takes the driving waveform as implemented, and drives it with very large number of scanning lines and at high speed
For example, when the pixel A is applied to a device that performs
Even after the transition, the voltage of -V is always applied after the com2 scan, so the scan electrode
Until com1 is scanned, transition is possible even at a low threshold due to accumulation of application time
It can be seen that there is a risk that the pixel A is inverted to the “dark” state.
.   As a driving waveform to prevent such a phenomenon, for example, a method shown in FIG.
Can be This method does not send scanning and information signals continuously.
A predetermined time interval Δt ′ is provided as an auxiliary signal application period, and during this period, the signal electrode
In which an auxiliary signal is set to the ground state. This auxiliary signal application period
The scanning electrodes are also grounded between them, so the voltage applied between the scanning electrodes and the signal electrodes
The voltage applied is the reference potential, and depends on the voltage application time at the FLC threshold voltage shown in FIG.
Existence can be substantially eliminated. Therefore, the “bright” state generated in the pixel A changes to “
Reversal to the "dark" state can be prevented. The same applies to other pixels.
I can say it.   Further, another example which is more preferable is that the driving waveform shown in FIG.
It can be carried out by applying a voltage to the electrode group.   In FIG. 6, the scanning signal is an alternating pulse signal of ± 2V. The pulse signal
The information signal is sent to the signal electrode group in synchronization with the signal, which is either “bright” or “dark”.
And + V or -V, respectively. Now, scan signals in time series
From the viewpoint, com n (n-th scan electrode) and com n + 1 (n + 1-th scan electrode) are selected.
During this time, a time interval Δt ′ is provided as an auxiliary signal application period. And during this time
When an auxiliary signal with a polarity opposite to that of the signal electrode group during com n scanning is sent to the
The time series signals given to the signal electrodes are, for example, those shown in seg1 to seg3 in FIG.
Becomes That is, the auxiliary signals α ′ to ε ′ in FIG.
The polarity is the reverse of the polarity. Therefore, for example, in FIG.
Looking at the voltage applied to the chronological order, the same information signal is continuously applied to one signal electrode.
, The voltage actually applied to the pixel A is V_thThe following voltages alternate As a result, the dependence of the voltage application time on the threshold voltage in the FLC has been eliminated,
The desired information (in this case, “bright”) formed during com1 scanning is written next.
There is no reversal until it is done.   The two examples of the driving waveforms described above are conceptual for explanation, and will be described later in the embodiments.
In the case of driving in the effective display area 104 and the frame 106 in the display screen 102,
Depends on the actual access mode and even the temperature.
Waveforms are used. In addition, although the above-described waveform is symmetric in the positive and negative directions, it will be described later in the embodiments.
Are not necessarily symmetric. (3.3) Display element drive voltage   As described above, in the FLC display element according to the present example, the liquid crystal molecules
Oriented to have a pole moment, and also when the electric field is removed
The feature is to maintain the orientation.   By the way, the state from one of the two stable states realized as described above to the other
The state changes depending on the voltage value applied to the display element.   That is, FIGS. 7A and 7B show the relationship between the drive voltage (applied voltage) and the transmittance of the FLC.
It shows a change with respect to time. (A) shows that the drive voltage is the threshold voltage −V_thOver
In this case, the transmittance changes from one state to the other state (for example,
To “dark”). FIG. 6B shows a case where the drive voltage does not exceed the threshold value.
Sometimes, the liquid crystal molecules react, but their orientation is not reversed,
Returns to its original state.   Further, the threshold value differs depending on the type of FLC and varies depending on the driving temperature.
This will be described later with reference to FIG.   Next, as described above with reference to FIG. 4 and FIG.
It requires five values: signal positive / negative, information signal positive / negative, and reference potential.
The voltage is generated by an apparatus according to the present embodiment, which will be described later, using an appropriate power supply.   As is clear from the above, when setting the drive voltage, the threshold and the like were considered.
Appropriate temperature compensation must be provided. (3.4) Temperature compensation   Regarding the FLC display control of this embodiment, special consideration must be given to temperature compensation.
Is the SmC^*Phase FLC is determined by pulse width (voltage application time), drive voltage value, etc.
The driving conditions that are related to each other greatly vary depending on the FLC temperature, and
Because the range of these driving conditions allowed in degrees is narrowly limited.
In addition, fine temperature compensation during FLC driving is required.   This temperature compensation detects the temperature of the FLC, and in fact, detects the ambient temperature on the display screen 102.
And setting of a drive voltage value corresponding to the detected temperature, and a pulse width, that is, one horizontal scanning period
This is done by setting. In consideration of the operation speed of the display screen 102, etc.
If so, manual compensation is extremely difficult. Therefore, the temperature compensation is
This is a unique requirement in the display element control.   In the following, the FLC driving conditions such as the pulse width and driving voltage value mentioned above
The transition will be described.   FIG. 4 shows the relationship between the drive voltage value and the pulse width as described above.
According to the figure, it can be seen that a large driving voltage V is required if the pulse width ΔT is short.
Call   The pulse width ΔT has an upper limit ΔTmax and a lower limit ΔTmin for the following reasons.
Exist. That is, during the so-called refresh driving, the frequency f of the applied voltage is
If (= 1 / ΔT) is less than about 30 Hz, flickering occurs, so the frequency f
There is a lower limit, ΔTmax, and the frequency f is equal to or higher than the video rate, ie,
If the speed of the data transfer from the word processor 1 is exceeded, the display screen 102
Communication with the word processor body 1 becomes impossible, so that the upper limit is set to the frequency f.
That is, ΔTmin exists.   Further, the drive voltage V also has an upper limit Vmax and a lower limit Vmin. that is
This is mainly due to various functions on the drive device side.   FIG. 8 shows the drive voltage when the temperature Temp is plotted on the horizontal axis and the logarithm of the drive voltage V is plotted on the vertical axis.
The figure shows the relationship between temperature and temperature when the pulse width ΔT is fixed.
Threshold voltage value V_thIs shown. As is clear from the figure, if the temperature rises
It is understood that the drive voltage value decreases.   As described with reference to FIGS. 4 and 8, when the temperature rises, the drive voltage value becomes
It can be seen that the pulse falls or the pulse width becomes short.   FIG. 9 is a diagram for providing the relationship between the driving conditions as described above for actual driving.
It is. This figure shows the look-up table described later in analog form.
, The look-up table contains values corresponding to the values
And driving condition data.   FIG. 9 shows the temperature Temp on the horizontal axis and the drive voltage V and the frequency f (= 1 / ΔT) on the vertical axis.
When the frequency f is fixed in the temperature range (A), the temperature Temp rises.
Then, the driving voltage value V drops and exceeds Vmin. Therefore, at the temperature point (D),
The fixed frequency f is a fixed value, and the corresponding drive voltage value V is determined. Below, temperature
Similar operations are repeated in the ranges (B) and (C) and the temperature point (E). More than
The shape of the curve thus formed depends on the characteristics of the liquid crystal and the like.
The number of sawtooth waves can be determined as appropriate.   Further, the following is considered in the embodiment.   The characteristics of FLC devices vary extremely even in the normal temperature range.
As described above, only a single drive waveform was defined and the pulse width and voltage were adjusted.
May be inadequate. For example, the operating speed is several times as high even in the range of 45 ° C to 5 ° C.
The order may be different, and in such cases the time zone and season used by the operator
Operational discomfort may also occur due to differences in iso-environmental conditions.   Therefore, in the embodiments described later, the temperature range that is normally used is divided,
In addition to defining appropriate drive waveforms in these divided temperature ranges,
By adjusting the pulse width and voltage according to the temperature for the drive waveform of
In this case, the operation characteristics are averaged. (3.5) Display drive system   In the present example, the mode of data access to the display screen 102 is a horizontal scanning line (CO).
Line access performed on each line (corresponding to the
Block access can be performed for each block as one unit, and a preset
Access by either. In addition, the word processor main body 1 as a host device
Block or line related to access can be recognized by these real address data To do.   Here, FIG. 10 shows that the effective display area 104 is composed of m blocks BL including a predetermined number of lines.
, BLK1,..., BLKm (1 ≦ l ≦ m). In this example,
It has 400 common-side transparent electrodes 114 (400 lines) in the vertical scanning direction,
The effective display area 104 is divided into 20 blocks (m = 20) in units of lines.
You. Then, when accessing data for such divided blocks,
First, after clearing the display of all the lines included in the block,
Is sequentially written from the first line to the last line.   On the other hand, when the display 100 is configured as shown in FIGS. 2 and 3, the FLC element is
Because it has memory, refresh the data that is not updated on the display screen.
It is not necessary to access the display screen with only the data related to the change.
And   In this example, depending on the function of the word processor main body 1 which is the host device,
The display from the first line to the last line of the effect display area 104 is constantly refreshed.
Refresh driving, that is, when driving a display device having no memory,
Refresh drive that is equivalent to the
And partial rewriting drive for rewriting only blocks or lines. That is,
When the processor 1 is refreshed for a display device having no memory
When refresh data is sent in the same way, perform a refresh operation,
When sending image data of the block or line when a change occurs
Enables a partial rewrite operation.   When erasing a block or writing to a line, the temperature compensation described in (3.4) above is used.
Drive based on compensation data. Update of the temperature compensation data is performed in the refresh drive mode.
The period from the end of access of the last line to the access of the first line
That is, it is performed during the vertical flyback period. On the other hand, when performing partial rewriting,
This can be performed at regular intervals by periodic interruption.   In addition, in consideration of the driving conditions described in (3-2), asymmetric driving is performed for one line.
When a dynamic waveform is given, the energy of either positive or negative
In this state, the stable state of the FLC element changes, and the memory of the FLC element changes. It is conceivable that this will adversely affect the control focusing on the characteristics. Therefore, in the embodiment, 1
During the line drive period, an appropriately determined waveform and its inverted waveform are given.
(Hereinafter, this is referred to as in-line inversion), the driving error in one line
The total energy is set to 0 so that the stable state of the FLC element does not change.   Also, when driving the display 100 for writing, the scan electrodes 114 (common lines) are
Scan while sequentially selecting, and at the time of the selection, simultaneously supply signals to the signal electrodes 124
When the same waveform is applied to the common line, the element
Each line exhibits the same optical response characteristic that is uniformly shifted on the time axis.
Will feel flicker on the display screen 102. Therefore, in this embodiment, the line
The drive waveform is inverted every scan (every horizontal scan) or every few lines,
To give a waveform of opposite phase every one line or every several lines
Is called MH inversion). This is because humans perceive the optical response in terms of surface,
If lines or several lines are driven in opposite phases, swell may be felt on the display screen.
It is based on being able to prevent kinking.   In addition, in the embodiment, in the refresh driving mode, the last line is shifted from the first line to the last line.
For each unit (one frame) of driving, or every N frames of driving.
The process of inverting the drive waveform for a line (hereinafter referred to as frame inversion)
Do. That is, as a result of performing in-line inversion for a line in one frame,
The line has an appropriate waveform (hereinafter referred to as a normal waveform) when the frame is driven.
Suppose that I 'and its inverted waveform I are given in this order, there is a next frame.
Or, at the time of driving after N frames, the inverted waveform I and the normal waveform I 'are given in this order.
To be able to The effect of this frame inversion will be described later. (3.6) Clear display screen   In this example, since the FLC element has a memory property, the first element can be used even if no voltage is applied.
Alternatively, the second stable state is maintained. In other words, unless a voltage is applied,
You will retain the previous screen.   Therefore, when the power is turned off, the display screen 102 and at least the effective display area 104 are cleared.
It is desirable to do. For example, power shutdown can be recognized by the state of the display screen 102.
Because. In addition, the display screen is cleared while the power is shut off for some reason. The state may have changed and meaningless data may be displayed.
At power-on to prevent mixing of actual display data and meaningless data in
It is desirable to clear the effective display area 104 in the above.   Focusing on this point, in this example, the effective display area 104 is
Clear and form a frame 106 to clear them even when the power is turned off.
To do. Also, when clearing the effective display area 106, as described in (3.5) above
Such block erasure is performed for all blocks.   Furthermore, in such clearing, the word processor itself as a host device is used.
Even if you do not receive screen erase data (for example, all white data) from
To reduce the load on the word processor 1 and transfer.
Speeding up clearing by eliminating the need for (4) Configuration of each part of the display control device   Each of the display control devices 50 for realizing each function described in “(3) Overview of display control”
The section will be described in detail. (4.1) Main symbols   First, signals or data transmitted and received between the units are summarized. (4.2) Control unit   FIG. 11 shows an example of the configuration of the control section 500. Here, 501 is the control procedure shown in FIG.
Control each unit according to, for example, a microprocessor-type CPU, 503
In addition to the programs corresponding to the control procedures and the like shown in FIG. 41 to be executed, various tables shown in FIG.
This is a ROM that has unpacked 505 is used by the CPU 501 in the process of executing the control procedure
It is a RAM used for such purposes.   In this example, a counter for frame inversion, that is,
A value N indicating whether to perform frame inversion for each frame is stored and used as a counter.
Domain FCNT and MH inversion counter
Area LCNT that stores a value indicating whether the
The register used to recognize the waveform currently used when setting
CX is provided.   PORT1 to PORT6 are port sections for which the input / output direction can be set.
P10-P17, P20-P27, P30-P37, P40-P47, P50-P57 and P60-
Has P67. PORT7 is an output port and has P70 to P74. DDR1
DDR6 sets the switching of the input / output direction of the port units PORT1 to PORT6, respectively.
Input / output setting register (data direction register). Note that
In this example, ports P13 to P17 (corresponding to signals A3 to A7) and
Ports P21 to P25 and P27 of port PORT2, P40 and P41 of port PORT4 (
(Corresponding to signals A8 and A9 respectively), ports P53 to P57 of port PORT5, port
Port P62 of port PORT6, ports P72 to P74 of port PORT7, and CPU 501
The terminals MP0, MP1 and STBY are not used.   507 and 509 are a reset section for resetting the CPU 501 and
And a clock generation unit that supplies an operation reference clock (4 MHz) to the CPU 501.   TMR1, TMR2 and SCI have reference clock sources and registers.
This is a timer that can divide the reference clock and the like in accordance with the setting of. First, the timer TM
R2 divides the reference clock according to the register settings,
A signal Tout serving as a clock signal is generated. The data output unit 600 outputs this signal Tout
Based on this, a clock signal that defines one horizontal scanning period (1H) of the display device 100 is generated. Ta Ima TMR1 is used to adjust the operation time on the program and 1H of the display screen 102.
This adjustment is realized according to the set value in the register.   In addition, these timers TMR1 and TMR2 are used to time out the set time based on the set value.
At the start of the next timing operation due to time-up,
The signal IRQ3 is supplied to the CPU 501, and the CPU 501 receives the signal IRQ3 as necessary.   Note that the timer SCI is not used in this example.   In FIG. 11, AB and DB connect the CPU 501 and each unit, respectively.
Internal address bus and data bus, 511 are connected to port parts PORT5, PORT6 and CPU501.
Is a handshake controller. (4.3) ROM memory space (4.3.1) Memory space configuration   FIG. 12 shows a configuration example of a memory space allocated to the ROM 503. Here, A000H ~
A / D converters 950 and D / F are provided in A3FFH and A400H to A7FFH, respectively.
A Stores data to specify them when accessing the conversion unit 900
. When accessing the data output unit 600, the display drive is used for A800H to ABFFH.
The data for specifying the operation register (see FIG. 16) is expanded.   Areas C000H to E7FFH store actual address data RA / D from word processor 1
This area is referred to in response to transmission and has been transmitted during block access.
To determine whether the address data is related to the first line of the block
Of the real address data RA / D sent out
And a line table for specifying a common side line to be used.   The areas E800H to EFFFH relate to the control described later with reference to FIGS. 42 and 45 to 47.
Area that stores various parameter groups to be used, and the number of blocks (20 in this example)
-Related data area (E800H ~) storing the data and driving the transparent electrode according to the temperature
D / A conversion unit that stores data for adjusting D / A conversion unit 900 for variable voltage setting
Related data area (E900H ~), on the display 100 in block access mode
In the timer TMR2 that outputs the clock Tout which is the reference for setting one horizontal scanning period (1H)
Block access timer TMR that stores setting data (TCONR) to register TCONR
2 Setting data area (EA00H ~), operation time on display 100 and time for control operation Register setting data of the timer TMR1 for setting the delay time (C
NTB), (CNTL), timer TMR1 setting data area storing (CNTBB) (EB00H to
, EC00H ~, ED00H ~).   In addition, in the line access mode, a clock serving as a reference for setting 1H on the display 100 is set.
Store the setting data (TCONRL) to the register TCONR of the timer TMR2 that outputs the lock Tout.
Line access timer TMR2 setting data area (EE00H ~)
To start a program that drives with a waveform corresponding to the temperature in the access mode
Line access jumping table area (EF00H-).   The area F000H ~ is processed as described later with reference to Figs. 41 to 42 and Figs. 45 to 47.
This is a program area that stores programs corresponding to procedures. (4.3.2) Blocking mode jumping table (from C000H)   In this example, at the time of block access, from the word processor main body 1 side
It depends on whether the transmitted real address data RA / D relates to the first line of the block or not.
Processing paths are different. This is because the address data corresponding to the block first line is
After clearing the display in that block when supplied, each line in the block is cleared.
This is based on the fact that sequential writing is performed for   For this reason, the real address data RA / D sent from the word processor 1 is blocked.
It is necessary to recognize whether or not the line corresponds to the first line of the lock.
At the time of processing, first, for each address data related to the first line of each block,
It is conceivable to make a successive comparison judgment every time real address data is input.
It is.   However, according to such successive comparison, as the number of objects to be compared increases,
A difference will occur in the processing time. That is, the program of the comparison determination processing step
This is because the number of comparison processes increases / decreases depending on the order on the RAM.   Therefore, in this example, the following judgment processing using a jumping table is performed.
And make the determination time uniform.   For example, as shown in FIG.
When the data is “03” H (“3” in the license number), this data is shifted one bit to the left.
When the upper two bits are set to "1" and the least significant bit is set to "0", Data "C006" H after setting is obtained. This data is stored in an address in the memory space.
The address in this memory space contains the code indicating whether it is the first line of the block.
If stored, all real address data will be blocked with exactly the same execution time
It is possible to identify whether the line is the first line or not.   Furthermore, the CPU 501 used can use the index register (IX) and
Instruction that can jump to the address indicated by the memory register (for example, processing "JUMP IX"
If possible, store the offset data in IX and jump
By writing the jump destination address in the
It is possible to immediately start an appropriate process.   In this example, the use of the index register and the above instructions is used as the CPU 501.
When possible, use the line numbers (0 to 399) as shown in FIG.
A jumping table (C000H to C31EH) is provided, and each address of the jumping table is
The procedure to be started (specifically, the first address in the program area of that procedure)
) Is stored.   In FIG. 14, BLOCK, LINE and FLINE are block access
Block erase procedure, line write procedure, and effective display area 104
This shows the procedure for updating the temperature compensation data accompanying the writing of the last line.
These will be described later with reference to FIGS. 45 (A) to 45 (D).   At the time of line access, it is determined whether or not to perform the temperature compensation data update procedure.
Since it is only necessary to determine whether or not it is the last line to determine, only one comparison target
And the line number is determined using the jumping address as described above.
Is not performed. (4.3.3) Line table   The actual address data RA / D needs to be converted depending on the configuration of the common-side driver 300.
. For example, in this example, the driving unit 300 is composed of five common driving elements 310.
Output 80 bits each, and further configure 4 blocks every 20 bits
In addition, 400 scanning lines are provided as common side lines. One of these scans
To select a line, (1) One of the five common drive elements 310 is selected. (2) One of the four blocks assigned to the element 310 is selected. (3) One line is selected from the 20 lines in the block. Is performed.   In this example, as shown in FIG. 15, a 2-byte address for line selection is used.
The 12th to 8th bits are used to select element 310, and the 6th and 5th bits are
And bits 4 to 0 are assigned for selecting a line. Real address data
To the address data for line selection is described with reference to the jumping table.
The processing can be performed in substantially the same manner as the solid FIG.
What is necessary is just to expand to a line table.   In FIG. 15, reference numeral 680 denotes the selection of the element 310 (selection of the element chip).
(Decoder), and depending on its configuration and for chip select
Since 5 bits of 12th to 8th bits are allocated, 2^Five= Up to 32 elements
The number of contacts 310 can be increased. At this time, 2560 lines are selected as scanning lines.
It becomes possible. (4.3.4) Parameter storage area   In this example, the driving condition of the display 100, that is, the driving voltage, depends on the temperature condition.
And one horizontal scan period, change delay data, and change line access mode
In other words, optimal drive control is realized by changing the waveform data. Therefore, the temperature
The driving conditions are not corrected based on the temperature measurement data from the
I have to.   Areas E900H to EFFH are areas where the correction data is stored.
In this example, to improve the efficiency of the process of reading parameters according to temperature,
Store such as.   That is, for one or a range of one stage temperature, for example,
D / A converter related data, (TCONR), (CNTB), (CNTL) or (CNTBB), and (
TCONRL), the group of parameters corresponding to temperature is
The data is stored in an area where the two bytes have the same value. And as stated in Figure 13
In almost the same way, temperature data obtained from the A / D converter 950 or
The read temperature data is used as the address of the lower 2 bytes, and the upper 2 bytes are sequentially rewritten and read. By doing so, a group of parameters corresponding to the temperature will be obtained.   For example, if the temperature data is "0080" H, first add "E900" H to this "
By accessing address E980 ”H, the D / A converter section corresponding to the temperature is accessed.
Continuous data (drive voltage) is obtained, and then "EA80" which is obtained by adding "0100" H to "E980" H
By accessing address H, the timer TMR2 setting data (TCONR) (table
Data for generating a basic clock that defines one horizontal scanning period on the display screen)
can get. Hereinafter, by performing addition and access in the same manner, the temperature is sequentially reduced.
The corresponding CNTB, CNTL, and CNTBB are obtained.   Also, especially in the line access mode, the waveform may be changed according to the temperature.
ΔT changes significantly, and the data (TCONR) in the block access mode is
Since it cannot be used as it is, in the same manner as above, the temperature EE00H
Read and set the data (TCONRL) corresponding to the waveform.   The jumping table area EF00H used in the line access mode
~ These programs are used to start a program for driving with a waveform corresponding to the temperature.
The start address of the program is stored in the jumping table for block access.
Start-up processing is performed in the same manner as in the cable (see FIG. 14).   In this example, an operating temperature range of 45 ° C. to 5 ° C. is assumed, and this range is divided into three parts.
In the range of 45 ° C to 35 ° C, the waveform described later with reference to FIG.
Is referred to as A waveform) in the temperature range of 35 ° C to 15 ° C.
(Hereinafter referred to as N waveform) in a temperature range of 15 ° C. to 5 ° C.
The waveform described later with reference to FIG. 35 including in-line inversion (hereinafter referred to as C waveform)
. ) Is set to perform control. For this reason, in this example, in each temperature range,
Each program shall be started, and the output of A waveform, N waveform and C waveform shall be
The first address of each of the routines LSTRA0, LSIRN0 and LSTRC0 is made to correspond to the temperature.
It is tabulated in the area EF00H ~. (4.4) Data output section (4.4.1) Configuration   FIG. 16 shows an example of the configuration of the data output section 600. Where 601 is the word processor
A data input unit for receiving the signal D and the transfer clock CLK, which is connected to the You. The signal D is obtained by adding the image signal and the horizontal synchronizing signal to the word processor 1.
In this example, the horizontal synchronization signal or horizontal blanking period
Is supplied with real address data superimposed thereon. Thus, the data input unit 601
The data output path is switched off according to the detection of the horizontal sync signal or horizontal blanking period.
When detecting, the signal component superimposed at that time is used as real address data.
Recognizes and outputs as real address data RA / D.
Recognized as image data and output as 4-bit parallel image data D0 to D3
You.   When the data input unit 601 recognizes the input of the real address data, it Output a DACT signal to identify whether or not the display unit 100 has been accessed. In the trigger generation section, the control section 500 sends the temperature from the temperature sensor 400 to the A / D conversion section 950.   619 is a busy signal of the display controller 50 in response to the busy signal IBUSY from the controller 500.
A busy gate that sends a signal BUSY for notifying the status to the word processor 1 You.   621 receives the signals A10 to A15 from the control unit 500, and according to the values, the A / D conversion unit
950, a chip select for the D / A conversion unit 900 and the data output unit 600. Set latch pulse gate array 625 based on signals A0 to A4 from 500
. The latch pulse gate array 625 selects each register of the register section 630.
The number of bits is equal to the number of registers in the register section 630.
You. In this example, the register section 630 has 22 areas of 1 byte each,
The pulse gate array 625 has a 22-bit structure with one bit corresponding to each area.
. That is, the register selector 623 sets the bit
When a bit is set, the area corresponding to that bit is selected and the control unit Depending on the supply, the data for the selected register via the system data bus
Data reading or data writing is performed.   In the register section 630, RA / DL and RA / DU are below the real address data RA / D.
This is a real address data register that stores the upper and lower 1 bytes, respectively.
Is stored by the real address storage control unit 641.   DC L and DC U are the number of dots in the horizontal scanning line direction of the display (800 dots in this example)
Horizontal dot that stores the lower and upper 1 byte of data corresponding to the value of
This is a count data register. It is activated when transfer of image data D0 to D3 starts and
The horizontal dot number counter 643, which counts the appropriate clock,Causes 645 to do so.   DM is the drive mode register for line access or block access
Is written.   DL L and DL U are registers for common line selection address data.
For each of the 16-bit data shown for
Store. The data stored in the register DLL is an address for specifying a block. Address data CA6, CA5 (corresponding to the 6th and 5th bits in Fig. 15) and line designation
Are output as address data CA4 to CA0 (corresponding to the fourth to zeroth bits in FIG. 15).
You. The data stored in the register DLU is supplied to the decoder unit 650,
Output as chip select signals CS0 to CS7 for selecting common drive element 310
Is done.   CL1 and CL2 drive the common line in block access mode (
1 for storing drive data to be supplied to the common side drive unit 300 at the time of line writing)
The byte areas, SL1 and SL2, are also
This is a 1-byte area for storing drive data to be supplied to the segment-side drive unit 200.   CB1 and CB2 are common when erasing blocks in block access mode.
1 stores drive data to be supplied to the common side drive unit 300 when driving the side line.
The byte area, SB1 and SB2, are also supplied to the segment side driver 200
This is a 1-byte area for storing data.   CC1 and CC2 are on the common side during line access mode line writing.
1 byte for storing data to be supplied to the common side drive unit 300 when driving the line
And SC1 and SC2 are the drive data supplied to the segment side drive unit 200
Is a 1-byte area for storing.   The following three 1-byte areas store data for switching the frame drive unit 700.
This is the area where the data is stored. Registers are divided into four bits, and registers FV1, FCVc, FV2, FV3, FSVc, F
V4 is provided.   A multiplier 661 multiplies the pulse signal Tout from the control unit 500 by, for example, twice.
You. 663A, 663B, 663C and 663D are the three-phase, four-phase, six-phase and 12-phase outputs of the multiplier 661.
Phase ring counter, block access mode or line access mode.
When selecting the N waveform of the code, one horizontal scanning period (1H) is divided into four, three, and two minutes, respectively.
Used for dividing and non-dividing. This divided period is hereinafter referred to as ΔT, for example,
In the case of three divisions, 1H is formed by 3ΔT.   In the line access mode, the normal waveform I 'and the inverted waveform I are combined. When the A waveform and the C waveform related to the in-line inversion control used together are selected, the waveform I
Or I 'output period (hereinafter referred to as 1H^*Called period, 1H^*1H by combining multiple periods
Will be composed. 1H = 1H when in-line inversion is not performed^*Is
. ) Is divided into four, three, two or no by the ring counter. this
Sometimes, for example, in the case of three divisions, 1H at 3ΔT^*And Δ in this case
T is set to a value that is substantially smaller than ΔT when in-line inversion is not performed.   665 is a multi-function for selecting one from the outputs of ring counters 663A to 663D.
It is a plexer and divides 1H according to the contents of the drive mode register DM.
This is set according to data indicating whether or not to drive. For example, in the case of 3 divisions, 4
Select the output of the phase ring counter 663B.   667 is a four-phase ring counter for each output of the ring counters 663A to 663D, and 669 is a
This is a multiplexer set in the same manner as the multiplexer 665.   FIG. 17 shows the clock Tout, the output waveform of the multiplier 661, the ring counters 663A to 663D, and the like.
And 667 output waveforms. That is, the ring counter is set by the multiplexer 665.
When any one of the outputs of the data 663A to 663D is selected, 4ΔT / 1H, 3ΔT / 1H, 2Δ
T / 1H or ΔT / 1H (or 4ΔT / 1H^*, 3ΔT / 1H^*, 2ΔT / 1H^*Ma
Or ΔT / 1H^*) Is selected, and the output waveform is sent to the shift register
The data is supplied as a shift clock and output of on / off data every ΔT is performed. Ma
One of the outputs of the 4-phase ring counter 667 is selected by the multiplexer 669
The output waveform is supplied to the shift register 673 as a shift / load signal.
Then, the operation is set according to the selected number of divisions.   Referring again to FIG. 16, in the register section 630, the areas CL1, CB1 and CC1 are stored. The ON / OFF data for each ΔT is similarly applied to the drive waveform standard in the areas CL2, CB2 and CC2.
The ON / OFF data of the constant signals CM1 and CM2 for each ΔT is stored. In addition, the area SL1, The ON / OFF data of the enable signal SEN for each ΔT is stored in the areas SL2, SB2 and SC2.
Similarly stores ON / OFF data of the waveform defining signals SM1 and SM2 for each ΔT. You.   In this example, the storage area for each signal data is made up of 4 bits, and 1 bit is
It is made to correspond to ON / OFF data of 1ΔT. That is, in this example, 1H or 1H^*
Is four.   Reference numeral 671 denotes a multiplexer unit coupled to the areas CL1 to SC2, and the drive mode register
When writing a line in the block access mode according to the contents of the
The signal data at the time of driving during erase and line writing in the line access mode
Select one of the data. In this multiplexer section 671, MPX1 is The multiplexer and MPX2 are also multiplexers that select 4-bit data for the signal CEN.
And MPX3 are 4-bit data for any signal CM1 from the areas CL2, CB2 and CC2.
MPX4 also selects 4-bit data for signal CM2
Multiplexer. In addition, MPX5 is assigned to any of areas SL1, SB1 and SC1.Multiplexer for selecting 4-bit data for SEN, MPX7 is the area SL2, SB2 and
Multiplexer to select 4-bit data for any signal SM1 from SC2, MP
X8 is a multiplexer for selecting 4-bit data for the signal SM2.   673 is a parallel / serial connected to MPX1 to MPX8 of the multiplexer 671 respectively.
A shift register section having shift registers P / S1 to P / S8 for A / P (P / S) conversion.
, The output of the multiplexer 665 is given as a shift clock signal to
An output period ΔT of the on / off data is defined. Also, the output of multiplexer 669
The force is given as a preset signal for performing the operation with the set number of divisions.   675 is a multiplexer MPX11-M coupled to shift registers P / S1-P / S8, respectively.
A multiplexer unit having a PX18, and each signal stored in registers CL1 to SC2
4 bits of on / off data bit selection data (stored in register DM)
And outputs P / S converted on / off data.   677 is the above shift register section for registers FV1, FCVc, FV2, FV3, FSVc, FV4. Output section that performs the same processing as 673 and multiplexer section 675, 680 is the signal DACT   690 corresponds to the activation of the chip select signal DS1 of the D / A converter 900, that is, D / A
The signal MR is sent to the control unit 500 when the A conversion unit 900 is accessed, and the CPU 501 generates the signal MR.
This is an MR generator for changing the pulse width of the clock E to be changed. (4.5) A / D converter   FIG. 18 shows an example of the configuration of the A / D converter 950. Where 951 is the A / D converter and 953
Is an amplifier that amplifies the detection signal of the temperature sensor 400 to a level compatible with the A / D converter 951.
It is a vessel.   When detecting the temperature, the control unit 500 operates the device selector 621 of the data output unit 600. Is transmitted). In response, A / D converter 951 increases from temperature sensor 400.
Conversion of analog quantity obtained through width gauge 953 to digital quantity of temperature detection signal You. A / D converter 951 supplies digital temperature data.
As signals DD0 to DD7 to the control unit 500 via the system bus.   The temperature detection timing is from the first line to the last line of the effective display area 104.
When performing a refresh drive that constantly refreshes the display of
This can be performed during the vertical flyback period from the end of the operation to the start of the first line drive. Also,
The part that rewrites only the block or line when the display data changes
When rewriting drive is performed, it is performed periodically, for example, by a timer interrupt.
be able to. (4.6) D / A converter and power supply controller   FIG. 19 shows an example of the configuration of the D / A converter 900 and the power supply controller 800.   In the D / A converter 900, 901 is a D / A converter, and 903 is to adapt its output to the next stage.
Amplifier.   In the power controller 800, 810, 820, 825, 830 and 840 are respectively
A variable gain amplifier for generating voltage signals V1, V2, VC, V3 and V4.
V1 leads the output of the amplifier 903 to the amplifier 810, so that the voltages V2, VC, V3 and V4 are
The output of amplifier 810 is routed to amplifiers 820, 825, 830, and 840, respectively, to produce
To achieve. 821 is an inverter inserted between amplifiers 810 and 820, and 841 is an amplifier 81
This is an inverter inserted between 0 and 840.   Here, the voltages V1 and V2 are positive and negative, respectively, supplied to the common side driving unit 300.
Negative drive voltage, voltages V3 and V4 are supplied to the segment side drive unit 200 respectively.
The positive and negative drive voltages and voltages VC are reference potentials applied to the respective drive units 200 and 300. Ma
These voltage signals are also supplied to the frame driving unit 700.   In this example, VC is fixed, and the ratio of the difference between V1, V2, VC, V3, and V4 to this VC is
Gain of each amplifier 810,820,825,830 and 840 so that 2: -2: 0: 1: -1
Make adjustments in advance.   When changing the drive voltage according to the temperature, the control unit 500 Of the container 901 is selected. Here, the basic clock for the operation of the D / A converter 901 is the control unit 500 The control section 500 supplies the appropriate clock signal E And the digital data for change setting is set to DD0 to DD7.
To the D / A converter 901 via the system bus. In response, the D / A converter 901
Converts the data into an analog signal and outputs it via an amplifier 903.   As a result, the amplifier 810 generates the voltage V1 and has the above ratio with respect to V1.
Generated voltages V2, VC, V3 and V4 are generated.   In the example of FIG. 19, it is assumed that the voltage V2 and the like are generated in accordance with the voltage V1.
Directs the output of the amplifier 903 to each of the variable gain amplifiers 810,820,825,830 and 840
You may do so. In addition, gain adjustment can be performed programmably.
A variable gain amplifier may be used. The configuration of the power supply controller 800
If a multi-valued voltage can be generated according to the driving mode of the units 200 and 300, etc.
It is needless to say that the present invention is not limited to the above-described configuration, but may be various. (4.7) Frame drive   FIG. 20 shows an example of the configuration of the frame driving section 700. Where 710,715,720,730,735 and
And 740 turn on / off the supply paths of the voltage signals V1, VC, V2, V3, VC and V4, respectively.
Switch from the gate array 680 of the data output unit 600 to the inverter 711,   When driving the frame, the register provided in the register section 630 of the data output section 600 Switches 710, 715 and 720 are switched in the same manner, and the signal of the waveform taking three values of V1, VC and V2 is obtained.
The signal can be applied to the frame transparent electrode 151 parallel to the common line. Also, Switches 730, 735 and 740 are switched according to the state, and the three values of V3, VC and V4 are changed.
The signal of the waveform to be taken can be applied to the frame transparent electrode 150 parallel to the segment line.
It becomes possible. (4.8) Display driver (4.8.1) Segment side drive unit   FIG. 21 shows the segment drive element 210 constituting the segment drive section 200.
An example of a schematic configuration is shown. Here, 220 is a 4-bit parallel image data D0 to D3 sequentially.
4x20-bit shift register to input and align to 80-bit parallel data
And operates according to the input of the shift clock SCLK. 230 is an 80-bit latch
And image data D0 to D3 are used to shift the shift data of the next-stage segment drive element 210.
All the shift registers 220 of ten elements 210 are led to the registers 220 When the 80-bit parallel data is aligned in the data output unit 600, Latch. The input logic circuit 250 performs the logical operation of
The specified data of each segment drive waveform according to the content of each bit data of the
The generated control logic. Reference numeral 260 denotes a level level of data generated by the control logic unit 250.
270 is a switch signal output section having a level shifter and a buffer for
Pressure signals V3, VC and V4, and switches in accordance with the output of switch signal output section 260.
Driver that leads V3, VC or V4 to segment lines S80 to S1
.   FIG. 22 shows a detailed configuration example of the segment drive element 210 shown in FIG. Shi
In the shift register 220, 221 corresponds to one bit, that is, one segment line.
In the D-type flip-flop and latch unit 230 described above, 231 is a latch circuit.
In the switch signal output section 260, reference numeral 261 denotes a level shifter;
275, 273 and 274 correspond to the switch signal from the switch signal output section 260.
Are switches for turning on / off the supply paths of the voltages VC, V3 and V4, respectively. (4.8.2) Common side drive unit   FIG. 23 and FIG. 24 show the common drive elements constituting the common side drive section 300.
A schematic configuration example and a detailed configuration example of 310 are shown respectively. Where 340 is the input logicBlock selection by signals CA5, CA6, CEN, and line selection   Reference numeral 345 denotes line data related to the signals CA0 to CA4 supplied from the input logic circuit 340.
A decoder unit that selects a common line to be driven based on one element
At 310, 80 lines can be selected. In this example, 20 lines are one block.
And four blocks are assigned to one element 310, as shown in FIG. In this case, surround the decoder section 345 with a broken line
is there.   Reference numeral 350 denotes a control logic unit, which receives signals CM1, CM2 and Further, the decoder section 345 generates drive waveform defining data for the selected line.   360 is a level converter that performs level conversion of data generated by the control logic unit 250
And a switch signal output section having a buffer, 370 outputs voltage signals V1, VC and V2.
The switching is performed according to the output of the switch signal output unit 360, and the common line
A driver that selectively supplies V1, VC or V4 to the terminals C1 to C80.   In this example, five common-side elements 310 having such a configuration are provided.
That is, the effective display area 104 corresponds to 400 common lines.   In FIG. 24, 361 is a level converter, and 375, 371 and 372 are switches.
According to the switch signal from the switch signal output unit 360, the voltages VC, V1 and
A switch for turning on / off the supply path of V2. (4.9) Drive waveform (4.9.1) Display outline   FIG. 25 schematically shows the display 100. Where com and seg are
The common line corresponding to the common-side transparent electrode 114 provided on the upper substrate 110 and the lower part
This is a segment line corresponding to the segment side transparent electrode 124 provided on the substrate 120.
FLC is provided between them. Fcom and Fseg are common
Common line for frame provided parallel to common line com on both sides of the installation range of INCOM
, And parallel to the segment line seg on both sides of the arrangement range of the segment line seg
Are the frame segment lines provided in. Thus, common line com and segment
There is an area on the display screen 102 corresponding to the set of intersections in FIG. 25 with the line seg.
Effect display area 104, the frame common line Fcom, the frame segment line Fseg and
And segment line seg, and frame segment line Fseg
A set of intersections with the line com forms a frame portion 106 outside the effective display area 104.   In FIG. 25, the common line com and the segment Four lines seg each, frame common line Fcom and frame segment line Fs
eg is shown on each side, but in this embodiment, the common line com is 400
800 segment and segment line seg are arranged and can be driven one by one.
The Monline Fcom and the frame segment line Fseg are arranged 16 on each side and
The collective driving is as described above. (4.9.2) Display drive mode   In this embodiment, the display 100 is driven as follows.   Regarding the effective display area 104, as described in (3.5) above,
In the access mode, block erasing is performed first, and then writing is performed line by line.
Is made. In the line access mode, only writing for each line is performed.
Done. In this example, the area 104 is defined as a block in the block access mode.
When erasing data, when writing lines in the same mode, and in the line access mode.
Drive with a different waveform from the line write operation.   In the line access mode, the temperature range is 45 ° C to 35 ° C, 35 ° C to 15 ° C.
And three types of waveforms, A waveform, N waveform, and C waveform, according to the temperature
Write with.   The correspondence between these modes and the reference drawings is as follows. At block erase in block access mode   → Fig. 26 (A), (B) and Fig. 27 At line writing in block access mode   → Fig. 28 (A), (B) and Fig. 29 45 ° C to 35 ° C range in line access mode   → Fig. 34 35 ° C to 15 ° C range in line access mode   → FIG. 30 (A), (B), FIG. 31, FIG. 32, FIG. 33 (A) and (B) 15 ° C to 5 ° C range in line access mode   → Fig. 35   Regarding the frame 106, a frame along the frame common line Fcom (hereinafter referred to as a horizontal frame)
When the frame section along the frame segment line Fseg (hereinafter referred to as vertical frame) is different And drive with different waveforms. That is, for the horizontal frame, the non-
At the time of access (for example, during the vertical flyback period during refresh driving,
Drives line Fcom and lines Fseg and seg
Line writing in any mode for the vertical frame.
At times, drive the frame segment line Fseg with a waveform that matches the drive waveform of the common line com.
In this way, it is formed in cooperation with the common line com. (4.9.3) 1H = 1H^*Drive waveform of effective display area when   In the present embodiment, when erasing a block in the block access mode,
Line writing and N waveform selection in line access mode (35 ° C to 15 ° C range)
), One horizontal scanning period (1H) is divided into three, and the common line is divided during each ΔT period.
V1, VC or V2 is supplied to incom, and V3, VC or V4 is supplied to segment line seg.
Driving to be supplied is performed.   Table 1 shows the register areas CL1 to SC2 in the register section 630 of the data output section 600.
Shows an example of data to be set in. In the table, “x” indicates unused bits.
In the example, the register areas CL1 to SB2
The predetermined data shown in Table 1 are respectively assigned to the sixth to fourth bits and the second to zeroth bits of
Data to be deployed. On the other hand, in the course of executing the processing procedure,
, Block erase in block access mode in register area DM in drive mode
And line writing in the same mode, and line writing in the line access mode
The multiplexer 671 discriminates between the registers CB1 to SB2 and the registers CL1 to CL2.
Data to select SL2 or registers CC1 to SC2 and a multiplexer
665 and 669 are switched, and 3 bits of bit 6 to 4 or bit 2 to 0 are selected.
And one bit is sequentially output for a period of ΔT.   Tables 2 and 3 show common drive element 310 and segment drive, respectively.
3 shows a truth table of the driving element. In these tables, “x” represents “1” or
This is a case where the selected drive voltage V is not affected by any of “0”.
In Table 3, Q is 1-bit image data, that is, the latch
H 231 (see FIG. 22).
= 1 is assumed to output black data.   FIG. 26 (A) shows the signal CEN, based on the contents of registers CB1 and CB2 (see Table 1). Therefore, the waveform of the voltage signal V applied to the common line com is shown. Also,1, SM2 waveform and segment drive element 210 logic (see Table 3)
Shows the waveform of the voltage signal V applied to the segment line seg.   Therefore, when erasing a block in the block access mode, the chip select signal At the intersection of the common line com and the segment line seg
The difference between the voltages applied to each line, that is, the voltage signal as shown in FIG.
Will be added. Then, the voltage applied over the period ΔT is
With the pressure value 3V0, all information of the block is cleared to white data.   At this time, ΔT or 1H and voltages V1 to V4, VC are corrected according to the temperature.
Is as described above.   FIG. 28 (A) shows waveforms of signals CEN and the like based on the contents of registers CL1 and CL2,
The voltage applied to the common line com by the logic of the common drive element 310
5 shows a waveform of a pressure signal V. FIG. 4B shows each of the contents of the registers SL1 and SL2.
Waveforms such as signal SEN and the logic and image data of segment drive element 210
And the waveform applied to the segment line seg according to the contents (Q) of the data.   Therefore, at the time of line writing in the block access mode, the chip select signal Crossover of common line com selected by CA1 to CA4 with segment line seg At the point, a composite waveform of the voltage signal shown in FIG. 29 (A) or (B) will be added.
. Here, at the point where the waveform as shown in FIG.
Does not occur. That is, the point becomes white data by the block erase performed earlier.
State is maintained. On the other hand, at the point where the waveform as shown in FIG.
A state in which white data is obtained by the voltage value 3V0 applied over the first period ΔT
However, the display data is inverted by the voltage −3V0 applied over the following period ΔT.
Turn to black.   FIG. 30 (A) shows the case where the temperature is 35 ° C. to 15 ° C. during line writing in the line access mode.
Signals output based on the settings of registers CC1 and CC2 in the temperature range of
The waveform of CEN etc. and the logic of the common drive element 310
The waveform (N waveform) of the voltage signal V applied to the common line com is shown. FIG.
And the signals SEN etc. output based on the contents of registers SC1 and SC2.
The shape and, accordingly, the logic and image data of the segment drive element 210
And the waveform applied to the segment line seg according to the contents (Q) of the data.   These show normal waveforms in the temperature range.
When driving with an inverted waveform every line or every few lines, use the registers CC1 and
And CC2 are set appropriately, and the common line shown in Fig. 30 (A) is
What is necessary is just to make it output the waveform which inverted the waveform to Incom. In addition, Seg
The output waveform to the ment line seg may be as shown in FIG.   As a result, during line writing in the line access mode, the selected common
The intersection of the line com and the segment line seg is shown in FIG. 31 (A) or (B).
A composite waveform of the voltage signal is added. Here, a voltage having a waveform as shown in FIG.
At the point where the signal is applied, over the first period ΔT and the next period ΔT,
The applied voltage 2V0 and V0 exceed the threshold value for obtaining white data,
Since the voltage V4 applied during the period ΔT does not exceed the threshold value for obtaining black data,
The display is white. In addition, at the point where the waveform shown in FIG.
The display becomes white during the period of T, but is displayed by the voltage -3V0 applied during the last period ＴT.
The display is reversed, and black data is displayed.   FIGS. 32 and 33 (A) and (B) show the case where the inverted waveform and Q = 0, respectively. And the synthesized waveform when Q = 1, and
However, white data and black data are obtained respectively. (4.9.4) Drive waveform including in-line inversion   FIGS. 34 (A) to (E) show drive waveforms in the temperature range of 45 ° C. to 35 ° C.
A waveform applied to the line com, (B) and (C) are Q = 1 and Q, respectively.
= 0 is a waveform supplied to the segment line seg. A waveform is basic
Shows a combination of the N waveform shown in Fig. 30 (A) and its inverted waveform.
, The normal waveform I 'and the inverted waveform I are 3ΔT and 1H, respectively.^*Is configured. Soshi
Therefore, there is an appropriate pause between these waveforms, for example, 1H^*3H^*At 1H, ie
One horizontal scanning period is configured. The value of ΔT can be set from the ROM 503 according to the temperature conditions, etc.
It is set appropriately by reading the setting data (TCONRL) of TMR2.   (D) and (E) show the segment A as shown in (B) and (C) with respect to the waveform A in FIG.
By adding the waveform of the line seg, the black data and white data are
This indicates that the information is displayed, and the hatched portion is involved in writing. What
The waveforms and writing of the segment lines between these and the cases of FIGS. 30 to 33
The polarity of the part of the composite waveform where the waveform is made is reversed.
Is based on the fact that ΔT is smaller than in the case of N waveforms.
The waveform applied to the print line is changed according to the change setting to the registers SC1 and SC2.   FIGS. 35 (A) to (E) show the drive waveforms in the temperature range of 15 ° C. to 5 ° C.
When applied to Monline com, the C waveform, (B) and (C), respectively, have Q = 1 and Q = 1.
(D) and (E), the waveforms applied to the segment line seg according to
The composite waveforms (black and white, respectively) for Q = 1 and Q = 0 are shown
Therefore, writing is performed in the hatched portion.   In the C waveform, the normal waveform I 'and the inverted waveform I are 1H at 2ΔT, respectively.^*
Constitute, for example, 1H^*Are combined with a rest period.   As shown in FIGS. 34 and 35, the waveforms A and C are inverted in the line.
But also perform MH inversion, and also perform frame inversion.
I do.   Now, as shown in FIG. 36, on the screen (1F) at a certain point, the m-th segment
Intersection of the common line with the (n-1) th to (n + 2) th common lines in the scan direction scan
It is assumed that “white”, “white”, “black”, and “black” are displayed at the points, respectively.
If this is scrolled on the next screen (2F), the segment line and the first
Assuming that the intersection with the n + 3rd common line is “white”,
The display data at the intersection of the ment line and the (n-1) th to (n + 2) th common lines is
They are "white", "black", "black", and "white", respectively.   FIG. 37 shows the waveform A shown in FIG. 36 while performing MH inversion and frame inversion on the waveform A shown in FIG.
FIG. 9 is an explanatory diagram for describing a driving mode when displaying is performed as described above. Simple
Here, the case where the inversion is performed for each line and each frame is shown.
.   During the period of 1F, as shown in the upper left part of the figure, the common line com n-1, n, n +
A waveform and its inverted waveform are sequentially added to 1, n + 2 line by line.
. At this time, the waveform added to the segment line segm every 1H ("
Corresponding to “white”, “white”, “black”, and “black”), as shown in the lower left part of FIG.
As a result, a composite waveform in which writing is performed in the hatched portion is obtained.   Next, during the period of 2F, as shown in the upper right part of the figure, the common line com
In n-1, n, n + 1, n + 2, the waveform that is the inverted waveform added to the corresponding line in 1F is
Supplied sequentially. At this time, the waveform added to the segment line segm every 1H
(In 2F, the data on 1F is scrolled, so "white", "black",
(Corresponds to “black” and “white”), as shown in the lower right part of the figure.
As a result, a synthesized waveform in which writing is performed in the portion where the writing is performed is obtained. (4.9.5) Relationship between temperature and ΔT or V in line access mode   FIG. 38 is a graph showing the relationship between the temperature in the line access mode and ΔT selected accordingly.
FIG. 39 shows an example of the relationship between the temperature and the V value selected accordingly.
Show. In any case, the waveform is A in the range of 45 ° C to 35 ° C, and N in the range of 35 ° C to 15 ° C.
In the range of 15 ° C. to 5 ° C., the driving is performed with the C waveform.   The solid line in FIG. 40 shows the temperature and the responsiveness of the screen when driving is performed in this manner. FIG. The display element CS1017 (manufactured by Chisso Corporation) used by the present applicant has a temperature of 45 ° C to 5 ° C.
In the case where driving is performed while appropriately changing ΔT and V only in the N
As shown by the broken line in the figure, the responsivity changed from 18 to 3 Hz.
, ΔT and V are changed, the response is averaged to almost 8Hz as shown by the solid line in FIG.
We were able to. (4.9.6) Frame drive mode   In this example, as described above, for the horizontal frame,
Are formed at the same time when the A / D converter 950 is started to be driven.
Formed during line writing. The frame is the same color as the background color of the effective display area 104.
That is, when information is displayed in black, it is provided in white.   Table 4 shows a register FV for switching the frame driving unit 700 to form a frame.
Shows the data set in FCVc, FV2, FV3, FSVc and FV4. Where the frame common
The line Fcom is almost independent of the driving of the effective display area 104. As drive data for the common line Fcom, the common data shown in FIG.
The settings are made so that a waveform equal to the drive waveform of line com is obtained.   On the other hand, with regard to the frame segment line Fseg,
When writing a vertical frame during line writing in
Drive wave of the frame common line Fcom or common line com
Since the shape is different, each register so that white data is displayed according to each
Set the change of FV3, FV4 and FSVc.   Specifically, as the driving data of the frame segment line Fseg, when forming the horizontal frame,
A waveform equal to the drive waveform of the segment line seg shown in FIG.
When forming a vertical frame during line writing in the access mode, the segment shown in FIG.
The waveform equal to the drive waveform when Q = 0 of the line seg is
FIG. 30 (B), FIG. 34 (C) or FIG.
A waveform equal to the drive waveform when Q = 0 of the segment line seg shown in FIG.
Make the change settings so that   As a result, the horizontal frame is formed by being driven by the waveform shown in FIG. 27, and the vertical frame is formed.
In the block access mode, the waveform shown in FIG.
In the sleep mode, the wave shown in FIG. 31 (A), FIG. 33 (A), FIG. 34 (E) or FIG. 35 (E) is displayed.
It is formed by being driven in the form. (5) Display control (5.1) Outline of control procedure   There are two main features of the display control according to this example. One is the display controller 50 side.
Sending and receiving data to the word processor 1 by sending a Busy signal
This is to synchronize with the operation of the screen 102. This is essentially using FLC
The display element changes one horizontal scanning period depending on the temperature to make the operation effective.
It is caused by having made it.   Two, a normal word processor sequentially, periodically and continuously processes only image data.
(In the so-called refresh mode), whereas the word processor of this example
The sensor body 1 specifies the pixels driven by such data before the image data
Address data to transfer the data.
Instead of the fresh mode, the image data of only a specific part is determined by the address data.
It is possible to transfer and drive the data. This is a display element using FLC.
Because the child has memory, only the pixels that need to be updated are accessed.
It comes from the fact that it is enough.   In addition, in order to enable the above display control, the word processor main body 1 of the present example includes:
In addition to the functions of a normal word processor, it receives the Busy signal and
Data transfer is stopped, and address data is transferred, for example, on a horizontal synchronization signal.
It has the function of sending.   By making effective use of the features in the above display control, especially the second feature,
The following two display control modes are implemented.   That is, a block access and a line access. What is block access?
For example, 20 scanning electrode lines are defined as one block, and one block of the effective display area 104 is used.
Screen is erased at one time, and such blocks are set to, for example,
Information is accessed for each lock scanning line, and characters and the like are written. This
In contrast, line access is performed for each scanning line, and information writing is performed.
That is, it is not performed to make all "white" in advance.   FIG. 41 shows these display control forms in a program flow.
With reference to FIG. 41, an outline of the display control in this example will be described.   In FIG. 41, first, when the power of the word processor 1 is turned “ON”,   The INIT routine is automatically started (Step S101). Here, the Busy signal
When the power is turned ON, the frame 106 is driven and the effective display area 104 is turned off.
And the temperature compensation for it is performed. Finally, the Busy signal is turned off and interrupted. Generated by the transfer of address data from the
If the address data does not come, the program is not executed and the display screen 102
It stays still.   Next, when the address data is transferred and an interrupt request occurs, this internal interruptThus, the above-mentioned block access or line access is separated. Ie LS
Go to TR routine for line access, go to BSTART routine for block access
Access. This is manually performed in advance by the switching means 520 provided at an appropriate part of the above.   The line access mode is set by the switching means 520, and IRQ1 is generated.
When   The following program is executed to proceed to the LSTR routine. First, LSTR
Before proceeding to the routine, in step S103, based on the temperature compensation data
Refer to the line access mode data in the lookup table shown in FIG.
And the system clock data for line access to the register TCONR of the timer TMR2.
Set.   Next, in step S104, the frame counter FCNT, the line counter LCNT, and the waveform
Set the recognition register CX. Here, the frame counter FCNT and the line cow
In order to invert the drive waveform every N frames and every M lines,
It is a counter provided, and the waveform recognition register CX is driven according to the temperature of FLC.
This is a register provided to change the dynamic waveform. That is, in this step The number of frames and the number of lines for which the drive waveform is inverted are set.
Which of three waveforms to use later, based on the temperature compensation data in INIT,
Is calculated, and the data is set in the register CX. The data to register CX
The setting may be performed by referring to a table based on the temperature data. Step
In step S105, based on the temperature data, a jumper for line access shown in FIG.
Table 3 shows waveforms A, N, and C according to the respective waveforms.
It determines which of LSTRA0, LSTRN0 and LSTRC0 to proceed to.   Thereafter, any one of the above-described three routines and the subsequent routines are executed.
To perform line writing. This line writing is performed frame by frame and line
The polarity of the drive waveform in each horizontal scanning period, and in the case of the waveforms A and C within one horizontal scanning period.
It is done by turning.   Final when program execution shifts to the last line access routine of the frame
Perform line writing of the line, then update the frame drive and temperature compensation data, Judge whether to change the drive waveform or not, and restart the LSTR routine corresponding to the waveform.
It is.   On the other hand, when the block access mode is set by the switching means 520 described above,   The BSTART routine is started. Here, the Busy signal is turned “ON” and the
Read the address data and check if the data is the first line of the block or the effective display area
It is determined whether the current line is the last line or the line other than the above (step S107).
And S108). Here, if the address data is the first line and not the last line,
Come   Branch to the LINE routine. Here, one line is based on the transferred image data.
Line writing. Next, set the Busy signal to “OFF” and wait for an interrupt request. Chin is activated.   If the address data is the last line of the effective display area 104 in step S108,   Execution branches to the FLINE routine. Here, line writing for one line is
Do. Next, update the frame drive and temperature compensation data, and set the Busy signal to “OFF”. Then, the BSTART routine is started again.   In step S108, if the address data is the first line of the block,   Execution branches to the BLOCK routine. Here, the line specified by the address
Erase all the blocks to which it belongs, and set the area of such blocks to “white” (step
S111). Next, proceed to the LINE routine (step S109), and perform the same processing as described above.
Do. Display control in the block access mode is performed by the procedure described above,
Write information. Then, this signal generates a non-maskable interrupt request NMI and PWOFF
Is started. Here, the Busy signal is set to “ON” and the effective display area 104 is erased.
All areas are set to “white”. Next, the power status signal and Busy signal are
“OFF”, thereby turning off the power of the word processor 1 (step
S112).   As is clear from the above, two forms of display control, namely, block
Address and line access, the address
Data is sequentially, periodically and continuously transferred over the entire effective display area.
In this case, refresh driving is performed, and address data of a predetermined portion is
If the transfer is intermittent, the partial rewrite drive is performed.   Note that in the details of the control procedure described below,
Assuming that data and image data are transferred in refresh mode
Give an explanation. (5.2) Details of control procedure (5.2.1) Power on (initial)   Processing automatically started when the power of the word processor 1 is turned on
Will be described with reference to FIGS. 42 and 43.   FIG. 42 shows a flowchart of the process to be started, which is described above with reference to FIG.
INIT routine. FIG. 43 shows the INIT routine and the PWOFF routine to be described later.
The following describes the processing performed by the control unit 500 for each step.
Will be described. S201:   Set the power status (P ON / OFF) signal to “ON” and the signal Light to “OFF”.
At the same time, the Busy signal is turned “ON” via the data output
Output to main unit 1. While this Busy signal is being output, the word processor 1
Address data is not transferred. This is to effectively drive the FLC display element
Another reason is that one horizontal scanning period is changed depending on the temperature. That is,
The driving time of the FLC display element in the effective display area 104 and the
Synchronization with data transfer time, in other words, VRAM operation time in word processor 1
Since the display control device main body 50 outputs a Busy signal,
Therefore, synchronization is achieved (FIG. 43, time point: only numbers are described below). S203:   In the predetermined area in the register section 630 of the data output section 600,
The drive waveform generation control data for driving the display area is set. This is the
The waveform generation control data stored in the ROM 503 is converted into data as shown in Tables 1 and 4.
This is set in the register section 630 of the output section 600. S205:   Driving voltage value for initial frame driving and system clock which is the basis of one horizontal scanning period
Each data of the lock is sent to the timer TMR2 of the D / A converter 900 and the controller 500.
In the register TCONR. Block access, line access and
And basic time data of each block access at power-on / off
Set. S207:   The control unit 500 transfers frame drive control data from the data output unit 600 to the frame drive unit 700.
Then, based on this, the frame driving unit 700 performs frame driving. By such driving, the frame 106
And the display screen 102 is always kept in a good state. This is valid
While driving the display area 104, a voltage is also applied to the frame 106 to change the light transmittance.
This is to prevent the part of the frame 106 from becoming turbid and deteriorating the image quality.   Further, in this example, the frame portion 106 is set to “white (the alignment state transmitting the light from the light source FL).
) ", The effective display area 104 is set to" white (light transmitting state) ", and
Black ”. In addition, “black” and “white” in these displays
The definition is not limited to the above example, and there are also displays in which "black" and "white" are inverted.
Alternatively, a display for distinguishing the frame 106 from the effective display area 104 is also provided by the device according to the present embodiment.
It is possible.   The frame driving in step S207 is performed over one horizontal scanning period.
In the meantime, in the meantime, in FIG. 2, the transparent electrode 15 for the frame disposed on the lower glass substrate 120 is shown.
0 and the segment electrode 124 and the common electrode
Driving is performed by applying a voltage signal to the frame transparent electrode 151 parallel to 114. Therefore, the frame
Driving of the remaining frame (vertical frame) is not performed during this period.
At the time of erasing the effective display area 104 described later in step S213, the common electrode is also used.
This is done by:   In this step, A / D conversion is performed simultaneously with the above-described frame driving. Take
A / D conversion is performed on the ambient temperature information on the display screen 102 detected by the temperature sensor 400, i.e.,
The FLC temperature information is read by the A / D converter 950 and converted to digital data.
(Time and). S209:   Perform temperature compensation. That is, the A / D conversion data obtained above is read, and the
Refer to the look-up table (Fig. 12) stored in the ROM 503 in 0, and perform temperature compensation.
The obtained drive voltage V, system clock, and delay data are obtained.   The above process will be described in detail below with reference to FIG. Fig. 44 shows A / D conversion
The data is represented by a drive voltage V, a system clock which is the basis of one horizontal scanning period, and each delay. Algorithm and look-up table when converting to each time
It is assumed that, for example, temperature data 80H shown in FIG. This 80H is
Indicates the lower bits of the address in the table,
In, the analog temperature data is converted to the digital temperature corresponding to the lower bits of the address.
The operation to convert to degree data is performed.   Here, the arithmetic unit ALU of the control unit 500 stores the drive voltage data in the data 0080H.
Equivalent to upper address bit data in the address area (data area related to D / A converter)
To offset the E900H. This causes the contents of index register IX to be changed to E9
Set to 80H and obtain the data corresponding to this address. This temperature compensated drive voltage
The value is output to the power controller 800 via the D / A converter 900. next
The arithmetic unit ALU keeps the lower bit data of the index register
The order bit data is incremented by 1 and the content is set to EA80H. this is,
Corresponds to the address of the system clock table in the table.
Obtain compensated data. The system clock data which is the basis of this one horizontal scanning period
Data in the time constant register TCONR of the timer TMR2.   By the same processing, hereinafter, block access, line access, and power
-Each delay time data in block access at ON / OFF
Set in registers CNTB, CNTL, and CNTBB for timer TMR1. S211:   The drive start time of the effective display area 104 is synchronized. In other words,
Control unit 500 to completely synchronize access start and actual effective display area drive start.
For example, when the rising edge of the clock output pulse Tout of the timer TMR2 has
At this time, an internal interrupt request IRQ3 of the CPU of the control unit 500 is issued. This enables the active table
The actual driving of the indicated area is started (time point). S213:   The erasure of the effective display area 104, that is, the entire area is all "white" in this example.
. As a result, the display screen 102 at the time of power-on is improved due to dust from the previous frame drive.
Be good.   The erasing of the effective display area 104 is performed by, for example, using 20 scanning lines for each block. It is driven as a lock, so that one block is erased in one horizontal scanning period.
It is.   In addition, this drive causes the entire effective display area 104 to be set to “white” from the word processor main body 1.
Is not performed by receiving image data that is
This is done by automatically setting the shape on the program as described above.
is there. This makes it possible to erase the effective display area at the time of power on / off.
. S215   One horizontal scanning period is adjusted. That is, the delay data of the register CNTBB is
Timer TMR1 counts its own clock pulse based on this data.
To This allows one horizontal scan between the effective display area 104 and the program execution time.
The period is adjusted, and an internal interrupt request IRQ3 is generated when a predetermined time comes.   That is, the timer TMR1 compares the basic time data set in step S205 with the basic time data.
A predetermined time is set based on the temperature compensation delay time data obtained in step S209.
When the time taken from an appropriate point in time is counted, an internal interrupt request is
What happens. S216:   Steps S211, S213, and S215 are performed for each block, that is, for one horizontal scan.
It is performed each time. Therefore, in this step, the entirety of the effective display area 104 is
It is determined whether or not the block has been completed. If the determination is negative, the process returns to step S211 again.
The above process is repeated until the end of all blocks (time). S217:   If it is determined in step S216 that all blocks (effective display areas) have been completed,
The signal D is set to “OFF”, and the signal D can be transferred from the word processor 1. same
At this time, the signal Light is turned “ON”. At this time, the operator of the word processor 1
After the power of the main body 1 is turned on, the display screen 102 is displayed,
The user feels that the source has been turned on.
01 to S215, especially the drive of the frame 106 and the effective display area 104 of the display screen 102. The movement is already performed as the initial display control (time point). S219: This occurs when address data is transferred from the processor body 1,
Thus, execution of each program described later is started. Therefore, the address data
Until the data is transferred, the standby program is executed and the common line and segment are executed.
Both lines are kept at the same potential or grounded. At this time the display screen
102 remains stopped. Instead, the power supply to the display device 100 is stopped.
Stop, for example, cut off the power supply to the power controller 800 itself and generate a voltage signal
May be turned off. Is set in advance, and these settings are, for example, word processing.
Depending on the usage pattern of the operator, the data handled by the word processor, etc.
Performed by the operator. (5.2.2) Block access 45 (A) to (D) and FIG. 48 (A)
This will be described with reference to FIGS.   45 (A) to 45 (D) are stored in the ROM 503 of the control unit 500 in the form shown in FIG.
FIG. 9 is a flowchart of a program related to display control stored therein, in which block access is performed.
It is activated at each stage of the display control.   48 (A) and (B) show time charts of such display control.   Set the Busy signal to "OFF" (at the time of Fig. 48: only numbers below) and wait state
The control unit 500, which was located at Start RT routine (time). Hereinafter, referring to FIG. 45 (A), the BSTART
A description will be given of the display control in the application. S301:   Read address data. The address data RA / D transferred to the data output unit 600 is
Read into the control unit 500. S303:   Address conversion as described in (4.3.2) above based on the read address data
Program to be executed with reference to the jumping table shown in FIG.
Set the address of the system. S305:   The Busy signal is set to “ON” (time), and the next address data transfer is rejected. S307:   Execution branches to the program at the address set in step S303 (time).
If the address data RA / D is the first line address of the block, BLOCK
If the last line address of the effective display area, go to the FLINE routine.
If the address is other than the above, execution branches to the LINE routine.   When the BLOCK routine shown in FIG. 45 (B) is started, the following processing is performed. S309:   Performs address translation and settings. That is, the register section 63 of the data output section 600
Read address data RA / D transferred to registers RA / DL and RA / DU in 0, and
Based on the address data, as described in (4.3.3), the line to be driven
Address conversion for selecting an option. This translated address is shown in Figure 12.
The address data is obtained by referring to the indicated line table. This data is
To the registers DLL and DLU in the register section 630 of the data output section 600. S311:   The drive mode is block access. That is, the register of the data output unit 600
Data indicating block erase in block access mode is stored in the register DM in the data unit 630.
Set. S313:   Synchronize the operation start time. That is, as described above, the effective display area 104 and the
To completely synchronize the operation timing with the program execution, Waiting for, for example, the rising edge of the clock output pulse Tout of the TMR2,
An internal interrupt request IRQ3 is generated when a falling edge occurs. This allows the output
Synchronization between the pulse Tout and the program execution timing, so the output pulse Tout is valid
This is the basis of one horizontal scanning period and operation timing in the display area 104.
Therefore, the operation timing of program execution and the effective display area 104 can be synchronized.
Will be. S315:   Time adjustment until the end of image data transfer is performed. That is, the time chart of FIG.
As shown in the chart, the image data transfer is performed immediately after the address data transfer,
Waiting for this transfer end (time point), access to the effective display area 104 is started.   Here, the image data transfer time means, for example, one run from the word processor main body 1.
Assuming that 800 bits of image data to be scanned are transferred at 5 MHz in 4-bit parallel,
40 μsec is added to this transfer, and further, these image data are
Is the same as the time to be stored.   This routine BLOCK is mainly for erasing blocks.
Deletion of image data does not require image data.
The transfer is performed because the data transfer for the next line access is being performed.
is there. Alternatively, do not transfer the image data here, and
It may not be executed. S317:   Start block erase (time). This allows one horizontal scan period (1H)
Lock, i.e., access 20 scan lines, for example, and make all such "white" blocks
And As described above, these driving operations are performed by receiving all “white” image data.
Instead, a predetermined block erase waveform is set.   Also, as is clear from FIG. 48 (A), this block erase start time (time)
In the valid display area 104, whether the last line of the previous block has been written or
Or the vertical retrace interval has expired. S319:   Adjustment on a program for one horizontal scanning period is performed. That is, as already mentioned
The access time in the effective display area 104 changes with the temperature fluctuation of the FLC display element.
In this case, one horizontal scanning period in these effective display areas 104 is performed.
Adjust the program execution time according to the length of the interval.   As a specific method, the timer TMR1 in the control unit 500 is controlled by its own clock.
For example, from the point in time when the address data is transferred and the program starts (point in time)
Timing is performed, and when a predetermined time has elapsed, an internal interrupt is issued to the CPU 501 in the control unit 500.
A request IRQ3 is generated to branch to the next program routine.   Here, the method of determining the predetermined time is, as described in step S209 of (5.2.1),
Due to the temperature compensation, the program execution time is stored in the table area CNTB shown in FIG.
And the delay time are stored as count data.
Ima TMR1 compares the count number of its own clock with the contents of CNTB, and sets a predetermined value.
When counting, an internal interrupt request IRQ3 is generated.   When a predetermined time has elapsed, the execution of the program will be LINE routine due to the occurrence of IRQ3.
Branch to the point (time).   FIG. 45 (C) shows a flowchart of the LINE routine.
Invoked as a continuation of the CK routine or directly from the BSTART routine
It is what is done. In the following, it is explained as a continuation of the BLOCK routine.
In the description of the steps, detailed descriptions of the same processes as those already described are omitted. S321:   When the LINE routine is started by IRQ3 (at the time), the address conversion and setting are performed.
Perform settings. S323:   The drive mode is assumed to be line writing in the block access mode. That is,
Data indicating this is set in the register DM in the register section 630 of the data output section 600.
. S325:   Synchronize the operation start time. S327:   Time adjustment until the end of image data transfer is performed. Here, in the previous BLOCK routine
If the image data has been transferred, there is no need to transfer the data
The same time may be passed without execution. S329:   Start line access (time). At this point, the block erase ends.
According to the transferred image data of one scanning line, one scanning line of the block top line is used.
Is written, that is, displayed. S331:   Adjustment of one horizontal scanning time is performed (time point “▲ 10 ▼”). S333, S335 During this time, no program is executed. Next, the LINE routine is executed to write the second scan line of the block. Less than
As described above, by repeatedly executing the BSTART routine and the LINE routine,
To complete the writing of the scanning lines of all blocks, erase the next block and
Perform writing.   Through the above processing, the address data indicating the last line of the effective display area 104 is converted.
When sent, the flow chart of FIG. 45 (D) and the time chart of FIG. 48 (B)
The process as indicated by the arrow is started.   That is, address data indicating that this is the last line of the effective display area 104 is transferred.
When it is sent (at the time of Fig. 48 (B): only the following numbers are written), an interrupt request is sent. Here, since the address data indicates the last line of the effective display area 104,
After this routine, the FLINE routine shown in FIG. ).   Hereinafter, each step of the FLINE routine will be mainly described with reference to FIG. 45 (D) and with reference to FIG. 48 (B).
An explanation will be given for each top. Details of the same processing as described above are omitted.
Good. S336, S337, S339, S341, S343:   Set Busy to “ON”, perform address conversion and setting, and set the drive mode to block
Access mode line writing is performed, and the operation start time is synchronized. In addition,
Adjusts the time until the end of data transfer. S345:   The writing of the last line is started (time point). At this point, the effective display area 104
The writing of the penultimate line is completed. S347:   It is determined whether or not the last line writing in the effective display area 104 has been completed. finished
In this case, the process proceeds to the next step S349. This judgment determines the last line of the effective display area 104.
This is done only when accessing, and in the case of other access,
It only monitors the start of access. S349:   In this step, waveform control data for frame driving performed in the next step is decoded.
The data is updated by setting in the register section 630 of the data output section 600. In addition, frame drive
If the system and the like are set independently, frame driving can be performed without updating data.   However, in the INIT routine shown in FIG.
The frame drive voltage value is set along with the data setting.
In frame drive performed during the flyback period, the temperature was previously compensated by the INIT routine.
The drive voltage value is used as a reference. S351, S353   Driving of the frame 106 and A / D conversion are started (time). Vertical retrace from this point
The interval begins. At the same time as the end of A / D conversion, based on the A / D converted temperature data,
The drive voltage value, system clock, and delay time data are obtained. That is, temperature compensation Update the compensation data.   In the frame driving of step S351, only a part (horizontal frame) of the frame 106 is driven to
"White", and the remaining part (vertical frame)
What is done in parallel with the driving of the region 104 is that
That is what I described in Chin's description. However, the drive system of these frames 106 is not
If it is independent of the drive system of the effect display area 104, it is possible to drive the frame 106 all at once.
Both are possible.   Further, by forming the frame 106 by performing electric driving, the effective display area 10 is formed.
4 We have tried to improve the outside image quality, but
, Coating, etc., without considering the image quality outside the effective display area 104
Needless to say, it may be done. S355, S357:   As described above, writing of the last scanning line in the effective display area 104, and immediately thereafter,
Frame drive, temperature compensation, etc. in the vertical retrace period.   Thereafter, the address data, that is, the address of the top scanning line of the effective display area 104 is read. Erase and line write are performed every time. (5.2.3) Line access 46 (A)-(L), FIG. 49
This will be described with reference to (A) to (D).   46 (A) to 46 (L) are stored in the ROM 503 of the control unit 500 in the form shown in FIG.
FIG. 7 is a flowchart of a program related to a displayed display control, and includes a line access table.
It is started at each stage of the indication control.   FIGS. 49 (A) to (D) show time charts of such display control.   The main difference between the line access in this example and the previous block access is No information is deleted beforehand, and information is updated for each scanning line without erasing scanning lines in advance.
That is, display is performed. Also, line writing in line access is
The polarity of the drive waveform is inverted every frame, every frame, and within one horizontal scanning period.
Do it. The following is a description of the same processing as in the previous block access display control.
In the following, a detailed description will be omitted.   Set the Busy signal to “OFF” (at the time of Fig. 49 (A) or (C): Write only the numbers below.
The control unit 500 in the standby state receives the address data (time). Starts the indicated LSTR0 routine (time). This LSTR0 routine operates on the A waveform.
LSTRA0, LSTRN0 corresponding to N waveform, or LSTRC0 corresponding to C waveform
This is selected according to the temperature of the FLC as described above. Of these, LSTRA0
Drive waveform is one horizontal scan in FLC drive executed by LSTRC0 and subsequent routines.
The polarity is inverted within the period, the inverted waveform and the normal waveform, and the drive suspension period between them
As a result, an A waveform or a C waveform is formed.   In the following description, the letters A, N or
C may be omitted in some cases.   Hereinafter, the display control in the LSTR0 routine will be described with reference to FIG. 46 (A). S401:   Read address data. S402:   Whether the read address data is for the last scanning line of the effective display area 104
Judge. If it is the data of the last scan line, the process goes to the FLN0 routine of step S404.
Branch, and if not, branch to the LLN0 routine.   The following shows the display control for the LLN0 routine in the case of LLNA0 or LLNC0.
This will be described with reference to FIGS. 46 (C) and 49 (A). S410, S411, S413:   Address conversion and setting are performed by setting the Busy signal to “ON” (time point). Also,
The drive mode is set to line access. S414, S415:   It synchronizes the operation start time and adjusts the time until the end of image data transfer. S416:   Here, the inverted waveform of the first half is set. That is, in common line driving
Assume that the inverted waveform data of the A waveform or the C waveform is the contents of the register. S417:   The waveform data of the register REG2 is transferred to the registers CC1 and CC2 and SC1 of the data output unit 600.
And 2 to output the line with the inverted waveform in the first half of one horizontal scanning period.
Start access (time). S418:   Time adjustment for one horizontal scanning period is performed (time point). Here, in the first half of one horizontal scanning period
Line access by the inverted waveform of
A drive suspension period is set between the operation and the access. This is the timer TMR1
This is performed using the delay time data of the registers CNTB and CNTL.
In the pause period using the delay time data of one CNTB and four CNTLs
To form S419, S421, S422, S423:   Here, the same processes as those in steps S411, S413, S414, and S415 described above are executed.
In the time adjustment processing of step S423, since the data transfer has already been completed, step S4
No execution is performed for the same time as the processing of 15. S424:   In the same manner as the processing in step S416, the normal waveform in the latter half is set here.
. That is, the normal waveform data of the waveform A or waveform C is stored in the register REG2.
And S425:   In the same manner as in step S417, the normal waveform in the latter half of one horizontal scanning period is used.
Start line access (time).   By the processing in step S417 and this step, writing with the composite waveform is
This is performed in either the first half or the second half of the rest period of the horizontal scanning period. S426:   Wait for a predetermined time to adjust one horizontal scanning period, and wait for internal interrupt request IRQ3
Depending on the occurrence (time point), the program is started again, and execution is executed on LINVA0 or LI
Proceed to NVC0 routine.   Hereinafter, the LINVA0 and LINVC0 routines will be described with reference to FIGS. 46 (I) and 49 (A).
I will tell. S430, S431: S432, S433, S434: Proceed to S433 to reset the line counter LCNT and go to the LSTRA1 or LSTRC1 routine
move on.   If a negative determination is made, the process proceeds to step S434, where the contents of the line counter LCNT are discarded by one digit.
Reset and return to LSTRA0 or LSTRC0.   In step S402 of the LSTR0 routine, the transferred address data is
If the last scan line is determined to be 104, processing branches to the FLLN0 routine.
I do.   Hereinafter, the display control of the FLLN0 routine will be described with reference to FIGS. 46 (E) and 49 (B).
I will tell. S440, S441, S443:   Set the Busy signal to “ON” (at the time of FIG. 49 (B): Write only numbers below) and set the address
Perform conversion and settings. In addition, the drive mode is line-accessed. S444, S445:   It synchronizes the operation start time and adjusts the time until the end of image data transfer. S446:   The inverted waveform of the first half is set in the same manner as in step S416 described above. S447:   In the same manner as in step S417, the write operation using the inverted waveform in the first half of one horizontal scanning period is performed.
Access starts (time). S448:   Time adjustment for one horizontal scanning period is performed (time point). Here, as described in step S418
The drive suspension period is formed as described above. S449, S451, S452, S453:   The same processing as in steps S441, S443, S444, and S445 described above is performed, but
In the time adjustment process of S453, since the data transfer has already been completed, the process of step S445
No execution for the same time. S454:   In the same manner as the process in step S446, the normal waveform in the latter half is set here.
. S455:   In the same manner as the processing in step S447, a normal waveform in the latter half of one horizontal scanning period is used.
Start line access (time). S456:   It is determined whether or not the writing of the last line of the effective display area 104 has been completed. End
If so, the process proceeds to the next step S457. S457:   In this step, waveform control data for frame driving performed in the next step is set.
Set. S458, S459:   Driving of the frame 106 and A / D conversion are started (time). At this point, the active display area
The writing of the last scanning line in the area 104 has been completed. At the same time as the end of A / D conversion,
Update the compensation data.   Upon completion of the process in step S459, the program execution ends in the FINVA0 or FINVC0 loop.
Proceed to Chin.   Hereinafter, the FINVA0 or FINVC0 routine will be described with reference to FIGS. 46 (K) and 49 (B).
explain. S460, S461: S462: Performs the contents of the waveform recognition register CX based on the temperature data of the temperature compensation performed after the access.
Calculate and compare with the contents of CX. If it is different in this comparison, the control routine
Returning to step S104 described above with reference to FIG. 41 to change the
Select one of the routines according to the waveform. If not, step S4
Go to 63.   In this way, in the FLC display control by line access, the temperature state of the FLC is detected.
If the temperature range has changed since then, change the drive waveform.
Thus, more appropriate display control is performed. S463, S464, S465:   Here, it is determined whether or not the frame counter FCNT is 0. If the judgment is affirmative,
Proceed to step S464 to reset the frame counter and line counter and
Proceed to Chin.   The LSTR1 routine and subsequent routines are shown in FIG. 46 (B) in their entirety.
As shown in FIG. 46 (A), the LSTR0 routine
And almost the same routines that follow it, except for LSTR0
In the line access by the routine, the first half of the line access has an inverted waveform and the second half has the inverted waveform.
-Access with the normal waveform, the first half with the normal waveform, and the second half with the inverted waveform
Is to access. Routines LLN1, FLLN1, and LINV1 that follow the LSTR1 routine
And FINV1 are shown in Fig. 46 (G), Fig. 46 (H), Fig. 46 (J) and Fig. 46 (L) respectively.
The description is omitted.   As described above, for example, the frame counter FCNT and the line counter LC
If the value of NT is set to 1, the value of the line counter LCNT is set to 1 first, and
Assume that writing is performed in the first half of one horizontal scanning period for the first scanning line to be accessed. Then, the next scan line is written in the first half, and thereafter, alternately in the first half or the second half.
Writing is performed and goes to the last scanning line. And in the next cycle, the previous cycle
In the first half of the scan line, the write line was
In the scanning lines for which writing has been performed in step (1), writing is performed in the first half.   In the line access using the N waveforms, the polarity of the waveforms is inverted within one horizontal scanning period.
Not performed. However, as described above, the frame counter FCNT and the line counter
By setting the value of LCNT appropriately, every frame and line according to that value
The polarity of the waveform is inverted every time.   Hereinafter, the display control for the N waveform will be described with reference to FIGS. 46 (D) and (F) and FIGS. 49 (C) and (D).
It will be explained while referring to the figures. The routine different from the routine described so far is LLNN0
And 1 and FLLNN0 and FLLNN1; the LLNN0 and 1 routines are S470, S471, S474, S475:   These processes are the same as those described above, that is, when the Busy signal is turned “ON”.
(Time), and perform address conversion and setting. Next, change the drive mode to line access
And synchronize the operation start time. Also, adjust the time until the end of image data transfer.
Do. S475-1:   Here, the waveform is set. That is, the N waveform data is used as the contents of the register.
However, the waveform data set in the LLNN0 routine is normal waveform data.
Yes, it is inverted waveform data in the LLNN1 routine. S476:   The waveform data of the register is transferred to registers CC1 and 2, SC1 and
2 to output the line access with normal waveform or inverted waveform.
Start (time). S477:   One horizontal scanning period is adjusted.   After the processing described above, program execution proceeds to the LINVN0 or LINVN1 routine
. These routines are the same as LINVA0 or LINVA1 described above, so their explanation is omitted.
Abbreviate.   With the above routine, one line of N waveform access is performed, and
When access is repeated and the last line is reached, the FLLNN0 or FLLNN1 routine is started.
It is.   Hereinafter, such a routine will be described with reference to FIGS. 46 (F) and 49 (D).
. S480, S481, S483, S484, S485:   These processes are the same as those described above, that is, when the Busy signal is turned “ON”.
(Time), and perform address conversion and setting. Next, change the drive mode to line access.
And synchronize the operation start time. Also, adjust the time until the end of image data transfer.
Do. S485-1:   In step S475-1, waveform setting is performed in the same manner as described above. However, FLLNN0 le
In the routine, the waveform data to be set is normal waveform data, and the FLLNN1
In the chin, it is inverted waveform data. S486:   In the same manner as described above in step S476, the normal waveform or the inverted waveform
Start in-access (time). S487, S488, S489, S490:   In these steps, first, the writing of the last line of the effective display area 104 is completed.
Is determined, and when it is completed, the waveform control data for frame drive is
Set.   Next, driving of the frame 106 and A / D conversion are started (time point). Same as A / D conversion end
At time, the temperature compensation data is updated, and the process proceeds to the FINVN0 or FINVN1 routine.   The FINVN0 and FINVN1 routines are the same as those described in FIGS. 46 (K) and 46 (L).
Since the description is the same as that of FIG. (5.2.4) Power off   The operator of the word processor 1 performs an operation of turning off the power using a key or the like.
Then, at this time, the PWOFF routine related to the display control when the power is turned off is started.
You.   Hereinafter, referring to the time chart shown in FIG. 43 and the flowchart of FIG. 47.
Next, such display control will be described.   When an operator operates a key or the like to turn off the power, a word processor In this case, a non-maskable interrupt request NMI is issued and the PWOFF routine is started.
This interrupt request NMI is an unconditional interrupt, and the control unit 500
Even if it has been performed, the following process is immediately started. That is, S501:   The Busy signal is turned “ON” and the Light signal is simultaneously turned “OFF” (at the time of FIG. 43:
Only the numbers are shown below). S503:   Synchronize the operation start time. This is the same processing as described above. S505:   Driving of the effective display area 104 is started (time point). This drive is used in the INIT routine.
One block of the effective display area 104 is erased in one horizontal scanning period as in the case of
Is what you do. By such driving, the entire area of the area 104 is set to “white”, and its image quality is
In order to prepare for the next display. S507:   One horizontal scanning period is adjusted. This processing is the same as that described above. S509:   The above steps S503, S505 and S507 are performed each time one block is erased.
Therefore, in this step, all blocks, that is, the effective display area 104
It is determined whether or not all erasures have been completed. S511:   When it is determined in step S509 that the processing has been completed (time “▲ 10 ▼”), the power
ー Set the status (P ON / OFF) signal to “OFF” and also set the Busy signal to “OFF”
(Time (6) Effects of the embodiment   According to the above embodiment, the following effects can be obtained. (6.1) Effect of frame formation   When the display device is composed of FLC elements, the effective display area on the display screen 102
By providing a frame portion 106 outside the FL, the FL corresponding to the area outside the effective display area 104
Prevents the deterioration of the appearance of the display screen 102 caused by the unstable state of the C element
Not only can it be possible, but it is difficult to
It can also prevent a wake-up situation.   In particular, the electrodes for the frame are arranged corresponding to the frame portion 106 as in this example, and the frame is electrically formed.
Is performed, a mechanical member such as metal or plastic is used as a frame on the display screen 102.
It can be mechanically effective by placing it on the surface or applying paint etc.
Compared to the case where the display area 104 is divided, mechanical adjustment of the arrangement position is unnecessary,
Also, depending on the handling position of the display device, the occurrence of blind spots that may occur due to the placement of mechanical members
Does not occur. Further, the same color as the background color of the display data on the effective display area 104 or
Improves flexibility when forming a frame, such as being able to form a frame in a different color
. (6.2) Effect of temperature compensation   The driving energy (voltage and voltage) of the FLC element corresponding to the effective display area 104 and the frame 106
And pulse width) are compensated according to the temperature just before the write timing.
Therefore, stable driving is possible regardless of temperature conditions, and display devices using FLC elements
Display reliability can be improved.   In particular, by updating the compensation data during the vertical retrace period as in this example,
High-speed display processing is possible, and temperature data detection commands, that is, A / D conversion
Display processing is performed by driving the horizontal frame according to the drive command of the unit 950.
Efficiency can be further improved. (6.3) Effect of control in response to image data input   A means for waiting for input of image data from the host device is provided, and in response to the input,
Since the operation is started, a display using a display element without memory
Refresh drive that is performed continuously regardless of whether the display contents have changed Display data only when the display content changes.
New discontinuous driving is also possible. Refresh drive is possible,
There is almost no need to update the specifications of the existing host device. Also discontinuous drive
As a result, power consumption can be reduced, and as a host device,
It is sufficient to send data only when the screen needs to be updated.
The burden on software or hardware can be reduced.   The host device responds to input of one unit (for example, one line) of image data.
On the other hand, since a busy signal is sent out, various settings can be made after this.
I will be able to. In this case, the host device receives the busy signal and transmits the image data.
It is enough to add a function to wait for transfer.   Further, in this example, image data is sent from the word processor main body 1 as a host device.
Start / stop according to the presence or absence of input of real address data supplied in addition to data
And block to be accessed based on the real address data.
Recognition of lines or lines enables partial rewriting, and furthermore, refreshing
Updating of the temperature compensation data at the time of menu driving is also possible during the vertical flyback period. (6.4) Effect of display driver   Electrodes (common com, segment line) provided on the display 100 composed of FLC elements
seg, frame common line Fcom, and frame segment line Fseg).
Supply lines and switches to connect / disconnect each supply line and electrode are provided
Means for performing switch setting according to the supply of waveform data (common
Side drive section 300, segment side drive section 200, and frame drive section 700).
The electrodes can be appropriately driven with various driving waveforms depending on the contents.   In the embodiment, the waveform data can be changed and supplied as needed in the control process.
Therefore, drive such as block erase, image formation, frame formation, screen clear, etc.
This can be performed by using a waveform, and the image quality can be improved. (6.5) Effect of forced screen clear   The display screen 102 of the display 100 composed of FLC elements when turning on and off the power
Has been cleared, so the display screen 102
It is possible to easily recognize the start of use or the power-off.   In particular, in the embodiment, the data for clearing (eg,
(For example, all-white data) so that they can clear themselves.
Therefore, the burden on the host device can be reduced and clearing can be speeded up.   In addition, the configuration in which the screen can be cleared by itself is used, for example, during operation.
When clearing a surface, instead of receiving all white data from the host device, simply
It is also possible to take control only to receive only the
The effect can be applied. (6.6) Effects of power supply controller installation   Mark the electrodes (line com, seg, Fcom, Fseg) provided on the display 100 composed of FLC elements.
Since the value of the applied voltage can be changed, the optimum value can be set according to the temperature and driving conditions.
A voltage can be supplied to the electrodes.   In particular, in the embodiment, +,-and the reference potential are applied to the common side lines com and Fcom.
Similarly, the ternary voltage is also applied to the segment side lines seg and Fseg.
The voltage can be applied, and a total of five different voltages can be generated. Also, 1
One value (VC) is fixed, and the relative ratio of the other values can be set in advance.
Because some output voltages are used to determine other output voltages, some
Since a total of 5 voltages can be generated according to the change of the force voltage, it is appropriate for the temperature condition etc.
It is easy to adjust the voltage value.   In addition, the IC used for the common side driving element requires high withstand voltage
However, high operating speed is required for the IC used for the segment side drive element,
As in this example, one voltage is fixed, and the voltage is changed while maintaining the relative ratio to it.
By doing so, the specifications of both can be unified and the manufacturing process can be simplified. (6.7) Effect of waveform change and inversion drive   In line access mode, the temperature range normally used is divided and
In addition to defining the appropriate drive waveform in the divided temperature range of
Pulse width and voltage are adjusted for drive waveforms according to temperature.
Thus, the operation characteristics could be averaged.   In addition, as a result of performing in-line inversion, the total driving energy in one line is set to 0.
Therefore, a stable state of the FLC element can be secured.   Furthermore, as a result of performing the MH inversion, one or several adjacent lines are inverted.
Phase, which prevents the operator from feeling swelling on the display screen.
Came.   In addition, as a result of performing frame inversion, intersection of common lines and segment lines
The timing at which the same color data is written for a point is shifted. For example,
Comparing FIG. 31 (A) and FIG. 33 (A), in the former, the white data is in the first half and in the latter,
Is written in the second half, and focusing on the point of segm + comn-1 in Fig. 37,
White data is written in the first half, and in the second half in the second half. As a result, I wrote in the first half
The threshold characteristics of the FLC element at the time of
Thus, the operating point on the V-ΔT curve is expanded, and a margin is obtained. (7) Modification (7.1) Composition of frame 106   In the embodiment, the frame 106 is formed electrically.
The portion corresponding to the frame 106 of the display screen 102 is not limited to
It is not covered by mechanical means or by painting, etc.
It is also possible not to consider the image quality of the part. In addition, by electric drive
If the frame drive system is provided independently, the frame drive can be performed all at once.
Both are possible. Furthermore, when the frame is formed by electric drive,
In addition to the same color as the background color, the same color as the data color may be used.   Further, in the above example, the frame drive in which the frame transparent electrodes 150 and 151 are provided independently of the drive units 200 and 300 is provided.
It is driven by the moving part 700, but both or one of them
A drive element similar to or identical to the elements 210, 310 is provided, and the drive units 200,
The drive control may be performed as a part of the drive control of 300. (7.2) Temperature compensation timing and partial rewriting   In the above embodiment, the temperature compensation is performed during the vertical blanking period. this is
, Address data and image data are periodically and continuously (refresh mode
This was possible because it was assumed that they would be forwarded. But
However, the timing of temperature compensation is not limited to the above example, and can be set at an appropriate time. For example, address data of a specific part is intermittently transferred (in partial rewrite mode)
In this case, there is no vertical blanking period, so the display control in the above example
Temperature compensation is not performed, and the display control may be inappropriate.
You.   Therefore, when driving in the partial rewrite mode, temperature compensation is performed at regular intervals.
Is desirable. For this purpose, for example, a timer provided in the control unit 500 is used.
After measuring the clock and applying an internal interrupt request at a fixed cycle, turn the Busy signal “ON”
In this case, the temperature may be compensated for.   In order to enable the drive in the partial rewrite mode, the word in the above-described embodiment is required.
In addition to the functions of the
What is necessary is just to have the function to send. Alternatively, the address data is
Image data after the address data
May be configured to determine whether to activate such display control based on the presence or absence of
Noh.   Furthermore, temperature compensation is not performed in a table system as in the above example, but is performed by appropriate calculation.
It may be performed more. (7.3) One horizontal scanning period and drive voltage value   The temperature range as shown in FIG. 9 and the corresponding frequency (ie, one horizontal scan)
Inspection period) and the relationship with the drive voltage value are not limited to this, for example,
Narrower temperature range and correspondingly appropriate frequency and drive voltage
If it is set, fine temperature compensation becomes possible. (7.4) Waveform setting   In the above embodiment, in the block access mode, the waveform data for image formation is used.
Did not update its waveform data once it was set in register 630,
However, even with the above-described apparatus configuration, the control data of the waveform and the number of 1H divisions can be obtained at an appropriate stage of display control.
It is clear that data can be updated. This allows for various driving conditions
Drive waveform can be generated.   Also, in the block access mode, as in the above example, the waveform
In addition to selecting data, change the waveform data according to the temperature and It is also possible to obtain. In this case, for example, the area EA in FIG.
00H to EE00H to specified data of ΔT corresponding to temperature in the same way as other setting data
Is stored in the same manner as in the line access mode described above.
What is necessary is just to change the shape data. Also, the waveform data can be changed arbitrarily.
Then, the present apparatus can be used to determine the optimum waveform.   Further, in the above example, the change of the waveform data is performed in the program used according to the temperature.
It is set by reading using a jumping table.
You may do it.   In addition, in the above example, the waveform including in-line inversion is 1H^*There was a pause period for
This period can be set at an appropriate time, and such a period can be set.
Otherwise, the normal waveform and the inverted waveform are merged to generate a new waveform.
Can be. For example, if no pause period is provided in the example of FIG.
A waveform can be generated that takes V1 during T, V2 during the next 3ΔT, and V1 during the last 1ΔT.
You. In other words, any arbitrary waveform can be combined to generate another arbitrary waveform with different optical response.
Will be. In addition, the drive waveform is not limited to the above example,
It goes without saying that an arbitrary waveform can be set even in a case including inversion. (7.5) Selection of block access or line access This is performed according to the form of the data to be written. This is, for example, the display screen
The size of one block in 102 is equivalent to the size of the displayed character string.
If the data to be written is only characters, numbers, etc.
Block access becomes effective because it can be performed.   On the other hand, if the displayed image is a symbol, a graphic pattern, etc. of various different sizes,
For example, display or rewriting beyond the block size must be performed.
In-access will be more appropriate. (7.6) Number of scanning lines   In the above embodiment, the number of scanning lines per block is 20 and the entire effective display area is In this example using the FLC display element, the scanning is not limited to 400.
Since the selection time / line cannot be reduced by increasing the number of lines, the number of scan lines
The display screen can be made higher definition and larger. (7.7) Deleting effective display area 104   To reset the display screen to the initial state, the effective display area 104 must be
Automatically receives all "white" data from the word processor 1 when
It was done without. However, screen clear is either on or off.
Of course. Display control of block access and line access
When it is necessary to erase the entire effective display area,
Erasing can be performed without depending on the situation.   For this purpose, for example, by operating a key or the like of the word processor body 1
Control signal such as an unconditional interrupt, and the control unit 500
The area 104 may be erased. (7.8) Position of temperature sensor 400   The temperature sensor 400 determines the distribution temperature based on the FLC temperature distribution obtained in advance through experiments or the like.
Although it is appropriately placed in a position that represents temperature, it can detect temperature more accurately.
For example, a plurality of temperature sensors may be used. (7.9) Display 100, display controller 50, and word processor 1   The form of a signal transmitted and received between the word processor body 1 and the control device 50, for example, However, it is needless to say that an appropriate one may be used.   In the above embodiment, the display and the display control system according to the word processor are taken as examples.
However, the present invention is not limited to the above example.
Of course, it can be applied to a display and a television.   Also, as an effective use of the property that FLC display elements have memory
The structure of a display device using a larger screen than is conceivable in existing television
It is also possible.   Furthermore, the present invention provides a method for displaying a still image or an image with a relatively low screen update frequency. It is effective to be applied to the case where For example, teletext and information services
On the receiver of a screw or the like, or on the clock face or the message display of various devices
When applied to a display such as a seven-segment display, drive is performed when a screen change occurs.
Since it only needs to be performed, it is a large process that contributes to power saving.   In these cases, all screens may be updated when they are changed, and if there is a partial change
Alternatively, only that portion may be updated in the same manner as the above-described partial rewriting. Also these
In this case, the temperature compensation may be performed by a periodic interrupt.
The screen to be driven has been subjected to drive correction. If the screen update cycle is long or partial
In the case of a device that performs replacement, when temperature compensation is performed, all data displayed at that time are displayed.
The body may be rewritten by, for example, outputting it again from VRAM or the like. According to this, the whole screen
Over time, a uniform and favorable display state can always be maintained. [The invention's effect]   As described above, according to the present invention, a certain driving waveform and a
A means for adding a waveform obtained by inverting a line is provided.
Or, frame inversion can be performed, so that the stability of the optical modulation element such as the FLC element can be improved.
State, good display state, or expansion of the operating point on the V-ΔT curve. This
As a result, a display device is configured using an FLC element having bistability against an electric field.
In such a case, appropriate drive control can be performed while effectively utilizing the characteristics.
Become like

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an example of a configuration of a display device and a control system according to an embodiment of the present invention, and FIGS. 2 and 3 are display devices according to the embodiment, respectively. FIG. 4 is an exploded perspective view and a cross-sectional view showing one configuration example, FIG. 4 is a diagram for explaining a relationship between a driving voltage and an application time, and FIGS. 5 (A), (B) and FIG. 7A and 7B are diagrams showing the relationship between the driving voltage and the transmittance of the FLC element, and FIG. 8 is a diagram showing the relationship between the temperature of the FLC element and the driving voltage. FIG. 9 is a diagram showing the relationship between the temperature and the temperature stored as data in the storage area of the control unit according to this embodiment.
FIG. 10 is a diagram illustrating an example of a relationship between a driving voltage and a frequency, FIG. 10 is an explanatory diagram illustrating block divisions of an effective display area according to the present embodiment, and FIG. 11 is a configuration of a control unit according to the present embodiment. FIG. 12 is a block diagram showing an example, FIG. 12 is a diagram showing one configuration example of a memory space in the control unit shown in FIG. 11, FIG. 13 is an explanatory diagram for explaining address conversion according to the present embodiment, FIG. FIG. 15 is an explanatory diagram showing an example of correspondence between line numbers and jumping tables according to the present embodiment. FIG. 15 is a block diagram for explaining a method of selecting a scanning line in the present embodiment. FIG. 17 is a block diagram showing an example of the configuration of a data output unit according to the present invention. FIG. 17 is a waveform diagram showing signals of each unit for setting drive waveform generation in the data output unit shown in FIG. 16, and FIG. 19 is a block diagram showing a configuration example of an A / D conversion unit according to the nineteenth embodiment. Is a block diagram showing a configuration example of a D / A conversion section and a power supply controller according to the present embodiment. FIG. 20 is a block diagram showing a configuration example of a frame drive section according to the present embodiment. FIG. 22 is a block diagram illustrating a schematic configuration example of a segment-side drive element according to an example. FIG. 22 is a circuit diagram illustrating a detailed configuration example of the segment-side drive element illustrated in FIG. 21. FIG. 23 is a common-side drive according to the present embodiment. FIG. 24 is a block diagram showing a schematic configuration example of the element, FIG. 24 is a circuit diagram showing a detailed configuration example of the common-side drive element shown in FIG. 23, and FIG. 25 is a simplified display device for explaining a driving mode of the display device FIGS. 26 (A) and (B) are waveform diagrams for explaining an example of drive waveforms of common lines and segment lines at the time of block erasing, and FIG. 27 is FIGS. 26 (A) and Common line and segment shown in (B) FIGS. 28A and 28B are waveform diagrams showing examples of driving waveforms of common lines and segment lines at the time of line writing in the block access mode. FIGS. 29 (A) and (B) are waveform diagrams showing composite waveforms of the drive waveforms of the common lines and segment lines shown in FIGS. 28 (A) and (B), and FIGS. 30 (A) and (B) are FIGS. 31A and 31B are explanatory diagrams for explaining an example of drive waveforms (N waveforms) of the common line and the segment line at the time of line writing in the line access mode. FIGS. ), A waveform diagram showing a composite waveform of the drive waveforms of the common line and the segment line shown in FIG. 32, FIG. 32 is a waveform diagram showing an inverted waveform of the N waveform, and FIGS. 33 (A) and (B) are waveforms shown in FIG. 34 (A) to 34 (E) are waveform charts showing the composite waveforms when FIG. 35 (A) to (E) are waveform diagrams for explaining a C waveform used in a low temperature region of the line access mode, and FIG. 36 (A) to FIG. 35 (E) are waveform diagrams for explaining a C waveform used in a low temperature region of the line access mode. FIG. 37 is an explanatory diagram for explaining a display state in the case of performing MH inversion and frame inversion, FIG. 37 is a waveform diagram for explaining a mode of performing the driving shown in FIG. 36 from the A waveform, FIGS. 38 and 39. Is an explanatory diagram showing the relationship between temperature, pulse width, and voltage, respectively. FIG. 40 is an explanatory diagram for explaining the relationship between temperature and display responsiveness. FIG. 41 is a display control procedure according to this embodiment. 42 is a flowchart showing an example of an initial processing procedure of a display control procedure according to the present embodiment. FIG. 43 is a flowchart showing an initial processing and a power-off processing shown in FIG. Tasks to explain the operation of the example FIG. 44 is an explanatory diagram for explaining an algorithm for converting temperature data into drive voltage data and time data according to the present embodiment, FIGS. 45 (A) to (D) and FIG. 46 (A). To (L) are flowcharts showing an example of a detailed display control procedure in the block access mode and the line access mode according to the present embodiment, respectively. FIG. 47 is a detailed display control at power-off according to the present embodiment. A flowchart showing an example of the procedure, FIGS.48 (A), (B) and FIGS.49 (A) to (D) show FIGS. 45 (A) to (D) and FIG.
6 (A) to (L) are time charts for explaining the operation of the present embodiment according to the display control procedure, FIG. 50 is a schematic diagram for explaining a TN liquid crystal, FIG. 51 is a SmC ^* liquid crystal 52 is a schematic diagram for explaining SmH ^* liquid crystal, FIG. 53 is a schematic diagram for explaining the structure of FLC molecules, and FIG. 54 is a schematic diagram of a display element using FLC. FIG. 55 is a schematic diagram showing an example of an FLC display element applicable to the present invention, FIG. 56 is a schematic diagram showing an example of a cell having a matrix electrode structure applicable to the present invention, FIG. FIGS. 57 (A) to (D) and FIGS. 58 (A) to (D) are waveform diagrams showing waveforms of voltages applied to the FLC element. DESCRIPTION OF SYMBOLS 1 ... Word processor, 50 ... Display control device body, 100 ... Display, 102 ... Display screen, 104 ... Effective display area, 106 ... Frame, 110 ... Upper glass substrate, 112 ... Wiring part, 114, 124 ... Transparent electrode, 115, 125 ... Extraction Electrodes, 116, 126… Insulating film, 120… Lower glass substrate, 122… Wiring part, 128… Metal layer, 130… FLC sealing part, 132… FLC, 134… Spacer, 136… Orientation film, 140… Sealing material, 142… Mouth, 144 ... Sealing member, 150,151 ... Transparent electrode for frame, 200 ... Segment drive section, 210 ... Segment drive element, 220 ... Shift register, 230 ... Latch section, 240 ... Input logic circuit, 250 ... Control logic section, 260 … Switch signal output section, 270… Driver, 300… Common side drive section, 310… Common drive element, 340… Input logic circuit, 345… Decoder, 350… Control logic section, 360… Switch signal output section, 370… Dry 380: PCB, 382: Flexible cable, 384: Conductive member, 400: Temperature sensor, 500: Control unit, 501: CPU, 503: ROM, 505: RAM, 507: Reset unit, 509: Clock generation unit, 511 ... Handshake controller, 600: Data output unit, 601: Data input unit, 603: IRQ generation unit, 605: DACT generation unit, 613… FEN trigger, 619… Busy gate, 621… Device selector, 623… Register selector, 625… 22 bit latch pulse gate array, 630… Register part, 641… Real address storage control part, 643… Horizontal dot number counter, 650: Decoder unit, 661: Multiplier, 663A to 663D: Ring counter, 665,669: Multiplexer, 667: Four-phase ring counter, 671,675: Multiplexer unit, 673: Shift register unit, 677: Output unit, 680: Gate array, 690 … MR generator, 700… Frame drive, 710,715,720,730,735,740… Switch, 800… Power controller, 810,820,825,830,840… Variable gain amplifier, 900… D / A converter, 901… D / A converter, 950… A / D converter, 951: A / D converter, FL: Light source, PORT1 to PORT6: Port, DDR1 to DDR6: I / O setting register, TMR1, TMR2: Timer, AB: Address bus, DB: Data bus, com: Common line, seg ... Segment line, Fcom ... Common line for frame, Fseg ... Segment line for frame.

Claims (1)

Claims: 1) A scanning electrode group and a signal electrode group arranged in a matrix to form a pixel group, and a liquid crystal display element is arranged between the scanning electrode group and the signal electrode group. A display control device for driving the display device, comprising: a driving unit for driving each of the scanning electrode group and the signal electrode group; and a one-line scanning period for driving the scanning electrode group output from the driving unit. Scan electrode driving signal has at least two phases, a first phase of the two phases has a plurality of pulse signals of different polarities, and a plurality of polarities of a second phase signal and a reversal relationship. A display control device comprising: 2) The display control device according to claim 1, wherein the liquid crystal display element is an optical modulation element having bistability with respect to an electric field. 3) The optical modulation element is a ferroelectric liquid crystal element, and the display device is configured such that the ferroelectric liquid crystal element has a memory property. 3. The display control device according to item 2. 4) The display control device according to any one of claims 1 to 3, wherein the driving means inverts the polarity of the scan electrode driving signal every M (M is a natural number) lines. 5) The display control device according to claim 4, wherein the M is N (N is a natural number) times the number of scanning lines of the display device. 6. The display control device according to claim 1, wherein application times of a plurality of pulse signals having different polarities constituting the first phase are different.