JP2553543B2 - Frequency detection controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frequency analyzer that provides a plurality of bandpass filters having different frequency bands and analyzes the frequency of a radio wave using each of the filter frequencies. Particularly, it relates to improvement of the frequency detection control device.

[Conventional technology]

FIG. 5 shows, for example, Japanese Patent Application No. 61-14 developed by the applicant.
It is a block diagram which shows the conventional frequency detection control apparatus shown by 1682.

In the figure, (1 _m-1 ), (1 _m ), (1 _{m + 1} ), ...
It is a video signal obtained by detecting the outputs of n band pass filters (corresponding to channels) having the pass characteristics shown in the figure. FIG. 5 shows three channels m-1, m, and m + 1 out of all the channels, and the other channels have the same configuration. Reference numeral 2 is an A / D converter that measures the amplitude of the input video signal 1 and outputs it in binary code. Reference numeral 3 is a control circuit that controls each register described later by using the output of the A / D converter 2. is there.

4 is a register for storing the output of the A / D converter 2,
Taking channel m as an example, a PAL register (4m) is used as a register for storing the amplitude information from channel (m-1).
a) shows the PAO register (4mb) as a register for storing the amplitude information from the channel m, and the channel (m + 1)
A PAU register (4mc) is provided as a register for storing the amplitude information from the.

Reference numeral 5 is a reference video signal obtained by detecting the output of the reference bandpass filter having the pass characteristic shown in FIG. Reference numeral 6 is a reference A / D converter which measures the amplitude of the reference video signal 5 and outputs it in a binary code. The output code of the reference A / D converter 6 is input to the comparators 7 provided in the n channels having the n bandpass filters. Since the operation of all channels is the same, channel m will be taken as an example in the following description.

7m is a comparator for comparing the output of the A / D converter 2m with the output of the control A / D converter 6, and 8m is the output of the A / D converter 2 for the control A / D converter 6. This is a channel m effective signal output from the comparator 7m when the output is larger than the output. 9m is PAL register 4
It is a comparison circuit that compares the channel of ma with the channel of PAO register 4mb and the channel of PAU register 4mc.
As the output 10m, only when the channel m effective signal 8m is effective to the frequency operation circuit (not shown) in the subsequent stage,
Output as frequency calculation command signal Fpm. 11m is a control circuit
Output from 3m, PAL register 4ma, PAO register 4mb, PAU
This is a register sampling signal input to the register 4mc. 12 m is an Fcm signal which is detected by the comparison circuit 9 m and indicates a channel which should be the center for calculating the frequency.

Next, the operation will be described with reference to FIG. Here, the description will be focused on the channel m, and the other channels operate in the same manner as the channel m, so the description thereof will be omitted.

Consider the frequency where the passage amount of the channel m is the largest.

The video signals (1 _m-1 ), (1 _m ), (1 _{m + 1} ) of channels (m-1), m) and (m + 1) are passed through each filter having the filter characteristics shown in FIG. And the control video signal 5 is input as shown in FIG.

By inputting these into the A / D converters 2 _m-1 , 2 _m , 2 _{m + 1} , and 6, respectively, the amplitudes represented by the numerical values 0, 1, 2, ... Can be obtained in FIG. 6 (a). . In this way, regardless of the significance of the video signal 1 and the control video signal 5, the amplitude value is always obtained by sampling. First, in order to determine the significance of the signal, the control circuit 3m compares the threshold level (level 1 in this example) with the amplitude of the video signal to obtain the quantized signal shown in FIG. 6 (b).

The register sampling signal 11m is input to the PAL register 4ma, the PAO register 4mb, and the PAU register 4mc after a fixed time t _{1 based} on the rising edge of the quantized signal. The register sampling signals 11 _m-1 , 11 _m and 11 _{m + 1} are shown in FIG. 6 (c). PAL register 4ma of channel m has amplitude value "2",
The PAO register 4mb stores the amplitude value “8”, and the PAU register 4mc stores the amplitude value “3” although not shown. Although not shown in the PAL register 4na of the channel n, the amplitude value “2” is stored, the PAO register 4nb stores the amplitude value “6”, and the PAU register 4nc stores the amplitude value “1” although not shown. And If the contents of the PAL, PAO, and PAU registers are expressed as (PAL), (PAO), and (PAU), respectively, the comparison circuit 9
If m satisfies the following conditions (PAL) ≤ (PAO) ≥ (PAU), the Fcm (12m) signal that is the channel to be the center for calculating the frequency is validated. This is shown in FIG. 6 (d).

On the other hand, the comparator 7m compares the control video signal with the video signal of the channel m. Since the video signal of the channel m is larger, the significant signal m of the channel m is output to the comparison circuit 9m. This channel m effective signal 8m is shown in FIG. 6 (e). Channel n valid signal 8n has no significance because the amplitude of the control video signal for channel n is greater than the video signal for channel n. The channel effective storage signal CE (see FIG. 6 (f)) that stores that the channel effective signal 8 becomes significant becomes significant at the rising edge of the channel effective signal 8. Also the 6th
A signal obtained by delaying the quantized signal of FIG. 6B by t ₂ time is used as a delayed quantized signal, which is shown in FIG. The channel effective storage signal is produced by the comparison circuit 9 and the delayed quantized signal is produced by the control circuit 3 and sent to the comparison circuit 9. Comparison circuit
At 9m, The result of is stored in the flip-flop at the falling edge of the delayed quantized signal. The output of this flip-flop is Fpm (10
m). In the example of FIG. 6, Fc _m-1 (12 _m-1 ) is invalid and F
Since c _m (12 m) is valid and CE _m is valid, Fpm (10 _m
m) is valid. For channel n, Fc _n-1 (12 _n-1 )
Although not shown in the figure, it is invalid, Fcn (12n) is valid, but CEn is invalid, so Fpn (10n) is not valid.

After all, in the example of FIG. 6, the frequency calculation circuit is instructed to calculate the frequency for the channel m. The frequency operation circuit uses (PAU), (PAO), and (PAL) to find the frequency. Then, the level acknowledge signal is sent to the control circuit 3m and the comparison circuit 9m. Then, at the same time as resetting each part in this circuit, the next signal detecting operation is started.
The Fcm signal (10 m) that has become valid resets the Fcm (12 m) and the channel valid storage signal CEm.

[Problems to be solved by the invention]

Since the conventional frequency detection control device is configured as described above, when a signal with a very large amplitude is input, the video signals of many channels exceed the threshold due to the characteristics of the filter, and the video signal for comparison is also used. When the level of the video signal (hereinafter also referred to as the omni video signal) drops momentarily due to the influence of noise or the like, the video signal is at the level of the control video signal (hereinafter also referred to as the omni level) even in a channel whose frequency is away from the center channel. .) For a moment, the channel valid signal becomes valid, and (PAL) ≤ (PAO) ≥
The frequency is calculated if the condition (PAU) is satisfied. As a result, there is a problem that a plurality of frequencies may be calculated. Further, as shown in FIG. 7, if there is a difference in the quantization timing between the channel and the contrast channel (hereinafter also referred to as omni) having the contrast bandpass filter and generating the omni video signal, Since there is a reversal of the level relationship, there is a problem in that no deviation in the timing of quantizing the video signal and the omni video signal in all channels is allowed.

The present invention has been made in order to solve the above problems, and eliminates the influence of noise, and can detect only the true frequency even in a system with a large deviation of timing for quantizing a video signal. The purpose is to obtain a control device.

[Means for solving problems]

In the frequency detection control device according to the present invention, a part of the pass bands of each other overlap each other, a frequency band obtained by totalizing these pass bands forms a frequency band to be subjected to the frequency analysis, and a signal to be subjected to the frequency analysis. N (n is a positive integer) band-pass filters provided so as to be input in parallel with each other, and n A / D conversions provided corresponding to each of the n band-pass filters. A delay circuit provided in the front stage or the rear stage of each of the n A / D converters, and a pass band that covers all pass bands of the n band pass filters, The reference bandpass filter to which the signal to be subjected to the frequency analysis is input, the illumination A / D converter that converts the amplitude of the output video signal of the reference bandpass filter into a digital value, and the reference A. Maximum output of D / D converter The maximum amplitude value output circuit that repeatedly detects the value, holds the detected maximum amplitude value for a certain period, and continuously outputs the held value during the holding period, and the n band-pass filters. Corresponding to each, in order to time the output of the band pass filter with the output of the maximum amplitude value output circuit, by the n A / D converter and the n delay circuit, N control circuits that detect a signal of a certain level or more from a delayed digital signal that has been delayed for a certain period of time from the output of the bandpass filter and has become a digital signal, and output a sampling signal after a predetermined time from the time of detection , The output of the maximum amplitude value output circuit provided corresponding to each of the n band pass filters,
The delayed digital signal is compared, and a channel value valid signal is output when the amplitude of the delayed digital signal is large.
A number of comparators and n band pass filters are provided corresponding to each of the n band pass filters.
Compare the 3n registers that store the output level of the D converter and the values of these registers for each channel,
When the register value of the own channel is greater than or equal to both adjacent channel register values and the channel valid signal is valid, and a signal indicating that it is the center channel is not output from the adjacent channel,
It is provided with n comparison circuits that output a center channel signal indicating that the own channel is the center channel when calculating the frequency, to an external frequency calculation circuit.

[Action]

According to the present invention, by adopting the above configuration, even if the output video signal of the control bandpass filter, that is, the omni video signal is instantaneously lowered in level due to the influence of noise, etc. Since the maximum amplitude value output from the amplitude value output circuit is covered, it is not considered that the video signal having the value of the frequency distant from the center channel exceeds the level of the control bandpass filter. Further, there is a margin in time alignment of the video quantization timing of each channel only during the period in which the maximum amplitude value is output for the certain period, and even if there is a slight timing deviation, the magnitude relationship as shown in FIG. 7 is reversed. Does not occur, only the signal from the center channel can be taken out, and the error of calculating the frequency with respect to the signals from other channels does not occur.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a frequency detection control device according to an embodiment of the present invention, and the same reference numerals as those in FIG. 5 indicate the same parts. In FIG. 1, the channel (m-
Only three channels 1), (m), and (m + 1) are shown, and the other channels are similarly configured.

In FIG. 1, 13 is a delay circuit that delays the output 1 of the bandpass filter for a fixed time (tDL) in order to adjust the time with a later-described stretch omni level 16, and 14 is a delayed video signal that is the output. . Reference numeral 15 indicates the maximum value of the digital amplitude value obtained by converting the omni video signal 5 obtained by detecting the output of the control bandpass filter by the A / D conversion circuit 6, and further detecting the maximum amplitude value at a certain constant engine. A maximum amplitude value output circuit (hereinafter, also referred to as an omni maximum (MAX) value stretch circuit) that repeatedly executes the operation of holding t _HD and continuously outputting the held value during this holding period, 16 are outputs thereof. It is the maximum amplitude value (hereinafter also referred to as the stretch omni level) input to the channel comparator 7.

FIG. 2 is a diagram showing the omni-MAX value stretch circuit 15 of FIG. 1 in detail. Reference numeral 15a denotes an A / D-converted digital amplitude value output every time a clock pulse (not shown) is given. In the D flip-flop, 15b is a DFF storage level stored in the D flip-flop 15a, and 15c is a D flip-flop 15a _x and another D flip-flop 15a _y.
It is a comparator that calculates the magnitude relationship with the levels described in, and requires _K C ₂ pieces. Note that the following relationship holds when the cycle of the clock pulse is t _CLK .

15d is an AND gate for deciding which D flip-flop has the highest level stored in the comparator, enabling one of the tri-state buffers 15e, and outputting the stretch omni level 16 is there.

The output value of the comparator 15c _ij (the output of the AND gate 15di where "0" or "1" is lg _ij is represented by the following equation.

Next, the operation will be described with reference to FIGS. 1 to 3 as appropriate. FIG. 3 shows a case where k = 3, that is, the omni MAX value is held for 3 clocks and the delay time t _DL of the video signal of each channel is set to 1 clock. Further, it is assumed that the deviation of the quantization timing is within 1 clock. Further, here, the description will be given focusing on the channel m whose frequency is distant from the center channel, and the other channels operate in the same manner as the channel m, and thus the description thereof will be omitted.

The video signal 1m of the channel m and the omni video signal 5 are input as shown in FIG. 3 (a) through each filter having the filter characteristic shown in FIG. Video signal
1m is delayed by one clock through the delay circuit 13, and the delayed video signal 14m has a waveform as shown in FIG. 3 (b), and when input to the A / D converter 2m, 0, 3, 6 is shown in FIG. 3 (b). The amplitude represented by the numerical value of,… is obtained. Also, the omni video signal 5 is also A /
The D converter 6 obtains the amplitudes indicated by numerical values 0, 14, 5, ... In FIG.
Entered in 5. In this way, regardless of the significance of the video signal 1 and the omni-video signal 5, the amplitude value thereof is always obtained by sampling. Omni MAX value stretch circuit 15
Then, every time a clock pulse (= quantization timing, not shown) is given, the D flip-flop 15a shifts the omni amplitude level one after another, thereby changing the level information for k clocks (in the example of FIG. 3). Then, k = 3) memorize. In order to select the largest one of the k stored DFF storage levels 15b, the level comparison is performed with all the combinations ( _k C ₂ ) by the comparator 15c. Output value of comparator 15C _ij (“0” or
If "1") is lg _ij , then in AND gate 15di The logic of the AND gate 15di is input to the output control terminal of the tri-state buffer 15ei.
If the circuit is configured in this way, the maximum value D
Only the tri-state buffer 15e connected to the output of the flip-flop 15a is valid for output, and the one having the maximum amplitude value among the k DFF storage levels 15b is output as the stretch omni level 16 and shown in FIG. The waveform is as shown in b). Since the MAX value is stretched, the amplitude value 5 obtained at t ₀₃ in Fig. 3 (a) is covered by 14, and even if the omni amplitude level drops momentarily due to noise, the amplitude of the center channel frequency of the distant channel is reduced. The magnitude relationship between the video signal level and the level does not reverse. Also, FIG. 3 (b)
As is clearer, the phenomenon of reversal of the magnitude relationship does not occur even if there is a deviation between the quantized timings of the omni and other channels.

The operation other than the above is the same as that of the conventional technique, and thus the description thereof is omitted.

In the above embodiment, the circuit is configured by providing the delay circuit between the bandpass filter and the A / D converter, but the circuit may be configured by providing the digital delay circuit after the A / D converter. Good. Further, although the D flip-flop is used as the element for storing the omni-amplitude channel, any element can be used as long as it is a synchronous storage element, and the same effect as that of the above-described embodiment can be obtained.

〔The invention's effect〕

As described above, according to the frequency detection control device of the present invention, a part of the passbands of each other overlap, and the total frequency band of these passbands forms a frequency band to be subjected to frequency analysis, N band-pass filters (n is a positive integer) provided so that signals to be frequency-analyzed are input in parallel, and the band-pass filters are provided corresponding to each of the n band-pass filters. Covers the n number of A / D converters, the n number of delay circuits provided before or after each of the n number of A / D converters, and the pass band of the n number of bandpass filters. And a reference bandpass filter having a pass band that receives the signal to be subjected to the frequency analysis, and a reference bandpass filter for converting the amplitude of the output video signal into a digital value.
Operation to detect the maximum amplitude value of the output of the A / D converter and the control A / D converter, hold the detected maximum amplitude value for a certain period, and continue to output the held value during this holding period. To
The maximum amplitude value output circuit that is repeatedly executed is provided corresponding to each of the n band pass filters, and in order to time the output of the band pass filter with the output of the maximum amplitude value output circuit, With the n A / D converters and the n delay circuits, a signal of a certain level or higher is detected from the delayed digital signal which is delayed from the output of the band pass filter for a certain period and becomes a digital signal, and After a lapse of a predetermined time from the detection time point, the n control circuits that output sampling signals and the n band pass filters are provided corresponding to the outputs of the maximum amplitude value output circuit and the delayed digital signal. And n comparators that output a channel value effective signal when the amplitude of the delayed digital signal is large, and the n bandpass filters, respectively. Correspondingly provided 3n registers for storing the output level of the A / D converter in the own channel and both adjacent channels by the sampling signal of the control circuit, and compare the values of these registers for each channel. , When the register value of its own channel is greater than or equal to both adjacent channel register values, and the channel valid signal is valid, and no signal indicating that it is the center channel is output from the adjacent channel, A bandpass filter for comparison, which is provided with an n number of comparison circuits that output a center channel signal indicating that the channel is a center channel for frequency calculation to an external frequency calculation circuit. Even if the level of the output video signal (omni video signal) of the Even if there is a shift in the activation timing, it is possible to prevent the frequency of an erroneous channel other than the true channel from being calculated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a frequency detection control device according to an embodiment of the present invention, FIG. 2 is a diagram showing a maximum amplitude value output circuit (omni maximum (MAX) value stretch circuit) in FIG. 1, and FIG. Is a waveform diagram for explaining the operation of FIGS. 1 and 2, and FIG. 4 is a filter of the control channel (omni) which has each channel and a control bandpass filter and in which an omni video signal is generated. FIG. 5 is a block diagram showing a conventional frequency detection control device, and FIGS. 6 and 7 are timing charts and waveform diagrams for explaining the operation of FIG. 13 is a delay circuit, 14 is a delayed video signal, 15 is a maximum amplitude value output circuit (omni maximum (MAX) value stretch circuit), 15a is a D flip-flop, 15b is a DFF storage level, 15c is a comparator, 15d is an AND gate, 15e is a tri-state buffer, and 16 is a maximum amplitude value (stretch omni level). The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (3)

(57) [Claims] 1. Passage bands partly overlap each other, a total frequency band of these pass bands forms a frequency band to be subjected to frequency analysis, and signals to be subjected to frequency analysis are parallel to each other. N (n is a positive integer) bandpass filters provided to be input, n A / D converters provided corresponding to each of the n bandpass filters, and n Each of the A / D converters has n delay circuits provided before or after each of the A / D converters and a pass band that covers all pass bands of the n band pass filters. Of the signal to be input, a control A / D converter that converts the amplitude of the output video signal of the control band pass filter into a digital value, and a control of the control A / D converter. The maximum amplitude value of the output is detected and this The maximum amplitude value output circuit that repeatedly executes the operation of holding the maximum amplitude value for a certain period of time and continuously outputting the held value during this holding period is provided corresponding to each of the n band pass filters. , The above n n A / Ds are used to time the output of the bandpass filter with the output of the maximum amplitude value output circuit.
The converter and the n delay circuits delay the output of the bandpass filter for a certain period of time, and detect a signal of a certain level or more from the delayed digital signal that has become a digital signal, and after a predetermined time from the detection time , N sampling circuits for outputting sampling signals and the n bandpass filters are provided corresponding to each of the n bandpass filters, the output of the maximum amplitude value output circuit is compared with the delayed digital signal, and the delayed digital signal is compared. N comparators that output a channel value effective signal when the signal amplitude is large, and n band pass filters are provided corresponding to each of the n band pass filters. 3n registers that store the output level of the A / D converter and the values of these registers for each channel When the register value of its own channel is greater than or equal to the register value of both adjacent channels, the channel valid signal is valid, and no signal indicating that it is the center channel is output from the adjacent channel. A frequency detection control device, comprising: n comparison circuits that output a center channel signal indicating that the own channel is a center channel when calculating a frequency to an external frequency calculation circuit. 2. The frequency detection control device according to claim 1, wherein the delay circuit is an analog delay circuit provided before the A / D converter. 3. The frequency detection control device according to claim 1, wherein the delay circuit is a digital delay circuit provided at a stage subsequent to the A / D converter.