RU1804697C - Method of integrated sequential preparation of signal and device for its implementation - Google Patents

Description

and 8, respectively, a group of m elements OR NOT 9, the first, second and third groups of m elements AND 10, 11 and 12, respectively, the first, second, third and fourth groups of m switches 13, 14, 15 and 16, respectively sources of additional reference signals with adjustable amplitude and polarity 17, 18 and 19, a group of m adders 20, a signal source of threshold 21, an additional comparator 22, additional groups of m delay elements 23 j and samplers 24. Inputs 25 and 26 are information and the clock inputs of the device, respectively, and the group no m o rows 27 - a group of information outputs of the device.

The claimed method includes delaying the input signal x (t) (Fig. 2a) by i sampling periods T, where i 1, ..., m, (m is the number of orders) implemented by the delay elements 2i, ... , 2m (delay of the input information signal by 1, the sampling period is shown in Fig.2c); generating m difference signals (t) x (t) - x (t - iT) in the subtraction elements 1i, r .., 1m (Fig. 2d); dividing the i-ro difference signal by the i-th divider 3i C times (C 1 or C i); sampling the output signal of the i-th divider in the i-th sampler, to the clock input of which clock pulses (Fig. 26) are received from the clock input 26 of the device, each 1st sampled value is stored in the second sampler for the sampling period T; comparison of the output signal of the 1st sampler (FIG. 2d for i 1) in comparators 5i and 6i with the positive and negative reference signals U0n + and Don-, respectively (U0n + /U0n-./), if the value of the output signal of the 1st sampler is greater than the amplitude the signal U0n + of the source 17 or less than the amplitude of the signal U0n- of the source 18 at the outputs of the comparators 5i and 6j, positive signals of unit level U are generated, otherwise U ° (Figs. 2e and 2g for i 1) if the value of the output signal of the i-ro sampler is not greater than the amplitude of the signal U0n + and not less than the amplitude of the signal Don-, a signal of unit level U is formed at the output of the OR-NOT 9i element; otherwise, U ° (Fig. 2e for 1 1); two-step quantization of the input signal in the additional comparator 22 by comparing with the threshold signal of the source 21, generating a signal of the unit value U1 if the amplitude of the threshold signal is exceeded or equal to it; otherwise, the value U ° is zero (Fig.2z): delay of the output signal of the additional comparator x (t) on I sampling periods T, where 1 ...., t,

using an additional group of m delay elements 23i,.,., 23m (Fig. 2i for I 1); comparison of signals x (t) and x (t - IT), where i 1, ..., m, carried out by the first group

of m elements And 13i, ..., 13m; discretization of the output signal of the i-ro element And 131 (fig.2k for i 1) -in the i-th sampler 24 | additional group of m discretizers and storing in this discretizer

a sampled value for a sampling period; comparison of the output signals of the 1 comparators 5i and 6i and the 1st element OR NOT 9 | with the output signal of the 1st additional sampler 24j in elements

and 10i, 12i and 11i of the second, third and fourth groups of elements. And (in this case, the boundary differences between the signals of the object and the background distorted with a non-zero background are cut off); switching by output signals of 1 elements And 10i, 12i and 11i (Fig. 2l, 2n and 2m, respectively) of additional reference signals of sources 17, 19 and 18 in switches 14i, 16i and 15i, respectively, using the output signals of 1 elements And at

quality of control signals; summing the output signals of the 1 switches 14i, 15i and 16i in the adder 20, the output of which is formed a prepared signal i-order, In Fig.2o and 2p as

the example shows the timing diagrams of the output signal of the adder 20i for the case UAon1 U1 idop2 U ° 0, KdopZ -U1 AND

IDOP1 U ° 0, Tsdop2 U1, KdopZ U °, respectively, where idop1, idop2 and Odopz are the amplitudes of the additional reference signals of sources 17, 18 and 19, respectively, U1 and U ° are signals of unit and zero values. A second combination of additional reference signals is preferred when

preparation for detecting the signal x (t) (Fig. 2a) against a background of narrow positive and negative pulses. It is theoretically possible for the Ze 27 combination of reference signals idol1 idop2 and dopOz, if each of them

can take three values: U, U ° and -U1, which explains the high adaptive properties of the claimed method and the information content solved by subsequent correlation processing

information task, thereby expanding the functionality of the prototype method, i.e. The use of the claimed method improves the efficiency of correlation processing (for example, increasing the amplitude of the true and decreasing the amplitude of the maximum false correlation peaks due to the optimal choice of the values of the idop1, idop2 and idopz signals, a set of preparation orders and division factors of the respective dividers). Obviously, the prototype method is implemented as a special case of the claimed method with a division ratio of the divisors 3i, ..., 3m equal to 1 and IDOGI U, IDN2 U and Ufl0n3 -U1.

The elimination of the preparation of the most distorted at the background changes boundary differences between the background signal and the object, as well as the smoothing of the differential signals of high orders by attenuation (attenuation coefficient is equal to the order number) provides a higher accuracy of the conversion compared to the prototype method.

Thus, the claimed solution in comparison with the prototype provides increased reliability and enhanced functionality.

Formula of the invention. 1. A method for generalizing the orderly preparation of a signal, namely, that the input signal is delayed for 1 ... t sample periods, where m is the preparation order, m difference signals are generated between the input signal and each of the m delayed input signals in each period signals, sample the generated differential signals with a sampling period and store them for the sampling period, compare each of the stored values with positive and negative reference signals and form the m first signal Comparisons, each of which is chosen either to a single value with a duration equal to the sampling period, if the stored value of the corresponding difference signal exceeds the amplitude of the positive reference signal, or to a zero value of the same duration, m prepared signals are generated from the results of summing the corresponding signals, characterized in that, in order to increase the reliability and expand the scope due to the possibility of detecting a wide pulse signal on These narrow pulse signals, simultaneously with the formation of difference signals in each sampling period, compare the input signal with a threshold signal, by the equality or exceeding of which the input signal generates the signal of the first additional comparison of a single value, otherwise, a zero value, simultaneously with a delay of the input. signal delay the signal of the first

additional comparison for 1 ... rn sampling periods and comparison in each of the m sampling periods of the additional comparison signal with each of the m delayed 5 signals of the first additional comparison, form m signals of the second additional comparison unit. values, if the compared signals have unit values, and a zero value, otherwise, for the sampling period, the signals of the second additional comparison are stored at the same time as the difference signals and at the same time as the formation of m first

5 comparison signals form m second signals of comparison of a single value with a duration equal to the sampling period if the stored difference signal is less than the negative amplitude

0 reference signal, and m third signals comparing a unit value with a duration equal to the sampling period if the stored difference signal is not greater than the amplitude of the positive and

5 is less than the amplitude of the negative reference signals, otherwise, second and third signals of comparison of zero value of the same duration are generated, after which the simultaneous

0 comparison of every 1st, where i 1, mj, the first, second, and third comparison signals with the corresponding signal of the second additional comparison, m signals are generated from the comparison results, respectively, of the third, fourth and fifth additional comparisons of the unit value, if compared signals of unit value and zero value - in the remaining cases, and when summed in

0, the first, second, and third additional reference signals of a given value are selected as the corresponding signals, if, respectively, the signals of the third, fourth, and fifth additional compare to 5. neither have a single value, and of zero value, if the latter have a zero value,

2. The method according to claim 1, with the exception that the amplitude of each difference 0 signal before sampling is reduced i times. . . .

3. A device for generalized serial signal preparation containing a subtractor block, the first input 5 of which is combined with the input of the delay element block and is an input information bus / second inputs of the subtractor block are connected to the corresponding outputs of the delay element block, and the outputs are connected to the corresponding

the first inputs of the block of discretizers, the second input of which is a clock bus, and the outputs are connected to the corresponding inputs of the first and second blocks of comparators, the second inputs of which are connected respectively to the outputs of the sources of the positive and negative reference signal, the block of adders, the outputs of which are information output bus, characterized in that, in order to increase the reliability and expand the scope of application due to the possibility of detecting a wide pulse signal against the background of narrow pulses s, a threshold signal source, three reference signal sources, three switch groups, four AND element blocks, an OR-NOT element block, an additional comparator, an additional delay element block and an additional block of discretizers, the first input of which is a clock bus, are introduced into it and the second inputs are connected to the corresponding outputs of the third block of AND elements, the first input of which is combined with the input of the additional block of delay elements and connected to the output of the additional comparator, the first input of which o is the input information bus, and the second input is connected to the output of the threshold signal source, the outputs of the additional

the block of delay elements are connected to the corresponding second inputs of the third block of elements And, and the outputs of the additional block of discretizers are connected to the first inputs of the corresponding elements And the fourth, fifth and sixth blocks of elements And, the second inputs of the elements And the fourth block of elements And are combined with the corresponding first inputs of the block of elements ILI-NOT and connected to the corresponding outputs of the first block of comparators, the second inputs of the elements And the fifth block of elements AND are combined with the corresponding second input the elements block OR are NOT connected to the corresponding outputs of the second block of comparators, the second inputs of the AND elements of the sixth block of elements AND are connected to the corresponding outputs of the block of elements OR NOT, and the outputs of the fourth, fifth and sixth blocks of AND elements are connected to the corresponding first inputs of the first, second and third groups of switches, the second inputs of which are connected to the outputs of the third, fourth and fifth sources of reference signals, respectively, and the outputs of the first, second and third groups of com mutators are connected to the corresponding first, second and third inputs of the adder block, respectively. . .

o I i I I I I I i I HH

X (i-r)

 t

I --- - - - - -

e

g.

s

u.

to

l

Riga 2

rm

 No.

i-g

: E- R-;.

Jz

P:

iJi-t