JP2544727B2 - Frequency detection controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frequency analyzer that provides a plurality of bandpass filters having different frequency bands and analyzes the frequency of a radio wave using the output of each filter. Particularly, it relates to the frequency detection control device.

[Conventional technology]

FIG. 4 is a block diagram of a frequency detection control device which the applicant of the present invention has already developed and applied for (Japanese Patent Application No. 60-229310). In the figure, 1m- ₁ , ₁ , m, 1m + ₁ , ... Are video signals obtained by detecting the outputs of n band pass filters (corresponding to channels) having the pass characteristics shown in FIG. FIG. 4 shows three channels m- ₁ and m, m + ₁ out of all the channels, and the other channels are similarly configured.

Reference numeral 2 is an A / D converter that measures the amplitude of the input video signal 1 and outputs it in binary code. Reference numeral 3 is a control circuit that controls each register described later using the output of the A / D converter 2. . Reference numeral 4 is a register for storing the output of the A / D converter 2. Taking the channel m as an example, the PAU register 4ma serves as a register for storing the amplitude information from the channel m- _1.
However, a PAO register 4mb is provided as a register for storing the amplitude information from the channel m, and a PAL register 4mc is provided as a register for storing the amplitude information from the channel m + ₁ .

Taking channel m as an example below, 5m is for PAU register 4ma
Value and the value of PAO register 4mb, and the value of PAO register 4mb
This is a comparison circuit for comparing the values of the PAL register 4mc, and its output 6m is the frequency calculation command signal Fpm for the frequency calculation circuit (not shown) in the subsequent stage. 7m is control circuit 3m
Is a register sampling signal output from the PAU register 4ma, the PAO register 4mb, and the PAL register 4mc. 8m is detected by the comparison circuit 5m and indicates the channel that should be the center for calculating the frequency.
Fcm signal.

Next, the operation will be described with reference to FIG. Here, the description will be focused on the channel m, and the other channels operate in the same manner as the channel m, so the description thereof will be omitted.

Video signal of channel m- ₁ , m, m + ₁ 1m- ₁ , 1m, 1m + ₁
Is input as shown in FIG. When this is input to the A / D converter 2, the amplitude represented by the numerical values 0, 1, 2, ... Is obtained in FIG. Thus, regardless of the significance of the video signal 1m, its amplitude value is obtained by always sampling. First, in order to determine the significance of the signal, the control circuit 3m compares the threshold level (level 4 in this example) with the amplitude of the video signal to obtain the quantized signal shown in FIG. 5 (b). The register sampling signal 7m is input to the PAU register 4ma, the PAO register 4mb, and the PAL register 4mc after a fixed time t _{1 based} on the rising edge of the quantized signal. The register sampling signals 7m- ₁ , 7m, 7m + ₁ are shown in FIG. 5 (c). Amplitude value “3” in PAU register 4ma of channel m, amplitude value “7” in PAO register 4mb, PAL
The amplitude value “7” is stored in the register 4mc. The amplitude value “7” is stored in the PAU register 4m + ₁ a of the channel m + ₁ , and the amplitude value “7” is stored in the PAO register 4m + ₁ b. The PAL register 4m + ₁ c not shown and the amplitude value "3" is stored. If the contents of the PAU, PAO, and PAL registers are expressed as (PAU), (PAO), and (PAL), respectively, the comparator 5m satisfies the following conditions: (PAU) ≤ (PAO) ≥ ( PAL) Enable the Fcm signal, which is the central channel to calculate the frequency. In the example of FIG.
As shown in (d), the Fcm signal of channel m becomes valid. Further, a signal obtained by delaying the quantized signal of FIG. 5 (b) by t ₂ is used as a delayed quantized signal, which is shown in FIG. 5 (e). This delayed quantized signal is used as a control circuit 3m− ₁ , 3m, 3m + ₁ , ...
Create with. Further, in the comparison circuit 5m, the following result ▲ ▼ _-1 · Fcm is stored in the flip-flop at the falling edge of the delayed quantized signal. The output of this flip-flop is the signal Fpm (6m)
Is. In this example, Fcm- ₁ (8m- ₁ ) is invalid and Fcm- ₁
(8m) is valid, so Fpm is valid. For channel m + ₁ , Fcm + ₁ (8m + ₁ ) is valid according to the following logical formula ▲ ▼ ・ Fcm + ₁ , but since Fcm (8m) is also valid, Fpm + ₁ (6m + ₁ )) is output as invalid. It After all, in the example of FIG. 5, the frequency calculation circuit is instructed that the frequency should be calculated for the channel m.
The frequency calculation circuit obtains the frequency using (PAU), (PAO), and (PAL). Then, the level acknowledge signal is sent to the control circuit 3m and the comparison circuit 5m. In this circuit, at the same time as resetting, the next signal detecting operation starts. In addition, Fpm
By (6m), reset Fcm + ₁ (8m + ₁ ).

[Problems to be solved by the invention]

The frequency detection controller described above uses the channel m to determine the channel to be the center for calculating the frequency, that is, the center channel in which the frequency of the input signal drops.
And the signal amplitudes of the adjacent channels m- ₁ and m + ₁ . However, in such a device,
When a signal with a very large amplitude is input, due to the characteristics of the filter, a video signal that exceeds the level threshold for many channels is input to the frequency detection control device, so that multiple channels should calculate the frequency. As a result, there is a problem that a plurality of frequencies are calculated.

The present invention has been made in order to solve the above-mentioned problems, and prevents a plurality of frequency calculation commands from being output even when a signal having a large level is input, so that only a true frequency can be calculated. The purpose is to obtain a detection control device.

[Means for solving problems]

In the frequency detection control device according to the present invention, a part of the pass bands of each other overlap each other, a frequency band obtained by totalizing these pass bands forms a frequency band to be subjected to the frequency analysis, and a signal to be subjected to the frequency analysis. N band-pass filters (n is a positive integer) provided so as to be input in parallel with each other, and a pass band covering all pass bands of the n band-pass filters, A reference bandpass filter to which a signal to be analyzed is input, n A / D converters for converting the amplitudes of the outputs of the n bandpass filters into digital values, and the n A / D converters. N units that are provided corresponding to each of the A / D converters and that detect signals of a certain level or higher from the outputs of the above n A / D converters and that output sampling signals after a predetermined time from the detection time point. Control circuit, control A / D converter for converting the amplitude of the output video signal of the control bandpass filter into a digital value, output of the control A / D converter, and the n bandpass filters When the amplitude of the output of the n bandpass filters is larger than the amplitude of the output of the reference bandpass filter, the output of each of the n bandpass filters is compared with each of the outputs of the n A / D converters corresponding to The output level of the A / D converter in its own channel and both adjacent channels is provided in correspondence with the n comparators that output the channel effective signal and the n bandpass filters, and the sampling signals of the control circuit. Are compared with the 3n registers that store each, and the values of these registers are compared for each channel. If the above channel valid signal is valid and no signal indicating that it is the center channel is output from the adjacent channel, the center channel that indicates that the own channel is the center channel when calculating the frequency. And n comparator circuits that output signals to an external frequency calculation circuit.

[Action]

In the present invention, when a signal having a certain frequency is input, the signal from one of the n bandpass filters (center channel) is the largest, and the signals from the other bandpass filters are not so large. On the other hand, the signal from the control bandpass filter is smaller than the signal from the center channel but larger than the signals from the other channels. Therefore, when comparing the signal from the control bandpass filter and the signal from each bandpass filter, only the signal from the center channel can be extracted, and the frequency is calculated with respect to the signals from other channels. No mistakes will occur.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a frequency detection control device according to an embodiment of the present invention, and the same reference numerals as those in FIG. 4 indicate the same parts. In FIG. ₁ , channels m- ₁ , m, out of all channels are shown.
3 channels of m + ₁ are shown, and other channels are similarly configured. In FIG. 1, reference numeral 9 is a reference video signal obtained by detecting the output of the reference bandpass filter having the pass characteristic as shown in FIG. Reference numeral 10 is a reference A / D converter which measures the amplitude of the reference video signal 9 and outputs it in a binary code. The output code of the A / D converter is input to the comparator 11 included in all channels.

11m is a comparator that compares the output of A / D converter 2m and the output of A / D converter 10, 12m is when the output of A / D converter 2m is larger than the output of A / D converter 10 This is the "channel m valid" signal output from the comparator 11m. 13m is PAU register 4m
Although it is a comparator that compares the value of a and the value of PAO register 4mb, and the value of PAO register 4mb and the value of PAL register 4mc, its output 6m is for the frequency operation circuit (not shown) in the subsequent stage,
When the channel m valid signal 12m is valid, it is output as the frequency calculation command signal Fpm.

Next, the operation will be described with reference to FIG. Here, the description will be focused on the channel m, and the other channels operate in the same manner as the channel m, so the description thereof will be omitted.

Consider the frequency where the passage amount of the channel m is the largest. Through each filter having a filter characteristic shown in FIG. 2, channels m- _1, m, m + ₁ of the video signal 1M- _1, 1 m, 1
m + ₁ and the control video signal 9 are input as shown in FIG. These are A / D converters 2m− ₁ , 2m,
Inputting 2m + ₁ and 10 causes 0, 1, 2, ... in Fig. 3 (a).
The amplitude represented by the numerical value of is obtained. In this way, regardless of the significance of the video signal 1 and the control video signal 9, the amplitude value thereof is always obtained by sampling. First, in order to determine the significance of the signal in the control circuit 3m, the threshold level (level 1 in this example) is compared with the amplitude of the video signal to obtain the quantized signal shown in FIG. 3 (b).
The register sampling signal 7m is input to the PAU register 4ma, the PAO register 4mb, and the PAL register 4mc after a fixed time t _{1 based} on the rising edge of the quantized signal. The register sampling signals 7m- ₁ , 7m, and 7m + ₁ are shown in FIG. 3 (c). The amplitude value “2” is stored in the PAU register 4ma of the channel m, the amplitude value “8” is stored in the PAO register 4mb, and the amplitude value “3” is stored in the PAL register 4mc although not shown. Although not shown in the PAU register 4na of the channel n, the amplitude value "2", the amplitude value "6" in the PAO register 4nb, PA
Although not shown, the L register 4nc stores an amplitude value “1”. The contents of the PAU, PAO, and PAL registers are expressed as (PAU), (PAO), and (PAL), respectively. Comparison circuit 13m
Then, if the following conditions (PAU) ≤ (PAO) ≥ (PAL) are satisfied, the Fcm (8m) signal that is the channel that should be the center for calculating the frequency is validated. This is shown in FIG. 3 (d). On the other hand, the comparator 1m compares the control video signal 9 with the video signal of the channel m. Since the video signal of the channel m is larger, the significant signal m of the channel m is output to the comparison circuit 13m. This channel m effective signal 12m is shown in FIG. 3 (e). On the other hand, other channels, that is, channels other than the channel m among the n channels, the channel having the bandpass filter of the passband of the maximum frequency, and the channel having the bandpass filter of the passband of the minimum frequency. , The channel valid signal has no significance because the amplitude of the control video signal is greater than the video signal of that channel. Channel valid memory signal CE that stores that this channel valid signal 12 becomes significant
(FIG. 3 (f)) becomes significant at the rising edge of the channel effective signal 12. The quantized signal of FIG. 3 (b) t ₂
The delayed signal is a delayed quantized signal, which is shown in FIG. 3 (g). The channel effective storage signal is generated by the comparison circuit 13, and the delayed quantized signal is generated by the control circuit 3,
Send to the comparison circuit 13. The comparison circuit 13m stores the following results of ▲ ▼ FcmCEm in the flip-flop at the falling edge of the delayed quantized signal. The output of this flip-flop is Fpm (6
m). In the example of FIG. 3, Fcm- ₁ (8m- ₁ ) is invalid, Fcm (8m) is valid, and CEm is valid, so Fp
m (6m) is valid. For channel n, Fcn- ₁ (8n
_-1 ) is not shown, but is invalid, Fcn (8n) is valid, but CEn is invalid, so Fpn (6n) is not valid.

After all, in the example of FIG. 3, the frequency calculation circuit is instructed to calculate the frequency for the channel m. The frequency operation circuit uses (PAU), (PAO), and (PAL) to find the frequency. Then, the level acknowledge signal is sent to the control circuit 3m and the comparison circuit 13m. Then, at the same time as resetting each part in this circuit, the next signal detecting operation is started. In addition, it becomes Fcm (8m) by the enabled Fpm signal (6m).
And reset the channel effective memory CEm.

Although the channel effective signal and the channel effective storage signal are provided in the above embodiment, a quantized signal that is effective if the video signal of the channel is larger than the amplitude of the reference video signal and larger than the threshold is obtained. You may do it. That is, the output channel valid signal of the comparator may be input to the control circuit. In this case, the channel effective signal and the same figure (f) are shown in FIG.
The channel effective storage signal of is lost, but the others are the same. Further, although the Fp signal for the frequency operation circuit in the subsequent stage is reset by the level acknowledge signal from the frequency operation circuit, the Fp signal may be sent to the frequency operation circuit in pulses.

〔The invention's effect〕

As described above, according to the frequency detection control device of the present invention, a part of the passbands of each other overlap, and the frequency band in which these passbands are totaled forms the frequency band to be subjected to frequency analysis, N band-pass filters (n is a positive integer) provided so that signals to be frequency-analyzed are input in parallel to each other, and pass bands covering all pass bands of the n band-pass filters. A reference band-pass filter having a band and to which a signal to be subjected to the frequency analysis is input, and n outputs the amplitudes of the outputs of the n band-pass filters.
A number of A / D converters and n number of A / D converters are provided corresponding to each of the n number of A / D converters. After a predetermined time from the time of detection, n control circuits that output sampling signals, a reference A / D converter that converts the amplitude of the output video signal of the reference bandpass filter into a digital value, and the reference A The output of the / D converter is compared with the output of each of the n A / D converters provided corresponding to the n bandpass filters, and the amplitude of the output of the n bandpass filters is compared. Are provided corresponding to the n number of comparators that output a channel effective signal when the output of the control band circuit is larger than the amplitude of the output of the control band pass filter, and the number of comparators provided by the sampling signal of the control circuit. Channel and adjacent channels The A / D in the tunnel
The 3n registers that store the output level of the converter and the values of these registers are compared for each channel, and the register value of the own channel is greater than or equal to the value of both adjacent channel registers and the channel valid signal is valid. In addition, when the signal indicating that it is the center channel is not output from the adjacent channel, the center channel signal indicating that the own channel is the center channel when calculating the frequency is used as an external frequency calculation circuit. Since there are n comparator circuits for outputting to, it is possible to prevent the frequency of an erroneous channel other than the true channel from being calculated even when a signal having a large amplitude is input.

[Brief description of drawings]

FIG. 1 is a block diagram showing a frequency detection control device according to an embodiment of the present invention, FIG. 2 is a diagram showing filter characteristics of a bandpass filter and a control bandpass filter, and FIG.
FIG. 4 is a timing chart diagram for explaining the operation of FIG. 1, FIG. 4 is a block diagram showing a conventional frequency detection control device, and FIG. 5 is a timing chart diagram for explaining the operation of FIG. . 2 ... A / D converter, 3 ... control circuit, 4 ... register, 1
0 …… Comparison A / D converter, 11 …… Comparator, 13 …… Comparison circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. Passage bands partly overlap each other, a total frequency band of these pass bands forms a frequency band to be subjected to frequency analysis, and signals to be subjected to frequency analysis are parallel to each other. The frequency analysis should be performed by having n band pass filters (n is a positive integer) provided so as to be input, and a pass band covering all pass bands of the n band pass filters. A reference bandpass filter to which a signal is input, n A / D converters that respectively convert the amplitudes of the outputs of the n bandpass filters into digital values, and the n A / D converters described above. Corresponding to each, the signals of a certain level or higher are detected from the outputs of the n A / D converters, respectively, and after a predetermined time from the detection time,
N control circuits that output sampling signals, a reference A / D converter that converts the amplitude of the output video signal of the reference bandpass filter into a digital value, and the output of this reference A / D converter , Each of the outputs of the n A / D converters provided corresponding to the n bandpass filters is compared, and the amplitude of the output of the n bandpass filters is compared with the reference bandpass filter. N which outputs a channel valid signal when the output amplitude is larger than
Number of comparators and 3n number of output signals of the A / D converters for the own channel and both adjacent channels, which are provided corresponding to the n number of band pass filters, are stored by the sampling signal of the control circuit. The registers and the values of these registers are compared for each channel, and the register value of the own channel is greater than or equal to the register values of both adjacent channels, and the channel valid signal is valid, and the adjacent channel is the center channel. And n comparator circuits that output a center channel signal indicating that the own channel is the center channel when calculating the frequency to an external frequency calculating circuit when a signal indicating that A frequency detection control device characterized by the above.