JPS59188728A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To estimate the level of an analog signal before digitization of an overflowed digital signal, by directly detecting the overflow of the digital signal from the said digitized signal. CONSTITUTION:At an overflow data forming section 30 equipped with the 1st and 2nd shift registers 31 and 33 and 1st-5th AND gates 32, 34, 35, 36, and 37, a period, during which the maximum value data of digital signals outputted from an AD converter 11 continue, is judged as an overflow period and overflow data Q0, Q1, and Q2 corresponding to the length of the period are outputted. Since the length of overflowing period usually corresponds to the level of overflowed signals in the case of input analog signals having simple waveforms, such as a sine wave signal, etc., the overflow data Q0, Q1, and Q2 give information indicating the level of overflowed signals of input analog signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing circuit for detecting an open low of a digital signal.

[Background technology and its problems]

Generally, in an analog-to-digital (A/D) conversion circuit that converts an analog signal into a digital signal, when an analog signal with a signal level exceeding the dynamic range is applied, a so-called overflow state occurs, and the signal exceeds the dynamic range. The level is converted to data with the maximum value of the quantization level. Therefore, even if digital arithmetic processing is performed on the digital signal that has caused the overflow, correct arithmetic results cannot be obtained.

Conventionally, when converting an analog signal into a digital signal, as shown in FIG. 1, the input analog signal to be digitized by the A/D conversion circuit 2 is supplied to the level comparator 1, The signal level of
The level comparator 1 detects whether the dynamic range of the /D conversion circuit 2 is exceeded, that is, whether an overflow occurs, and the digital signal obtained from the A/D conversion circuit 2 is compared with the level comparator 1. The detected overflow signal was output at the same time.

In this way, in conventional A/D converters that detect overflow of digital signals from input analog signals before digitization, it is necessary to transmit the digital signals and overflow signals to the digital signal processing device at the subsequent stage. First, on the digital signal processing device side, unless the open-low signal is transmitted, it is not possible to perform correct signal processing on the digital signal taking open-low signals into consideration.

[Purpose of the invention]

An object of the present invention is to directly detect the overflow 70- of the digital signal from the digital signal, and to make it possible to estimate the signal level of the analog signal before digitization of the overflowing digital signal.

[Summary of the invention]

In order to achieve the above-mentioned object, the digital signal processing circuit according to the present invention includes a first detection means for detecting the maximum value data of a digital signal, and a period during which the detection output from the first detection means is continuous. The present invention is characterized by comprising a second detection means and a data formation means for forming and outputting overflow data corresponding to a period in which the maximum value data is continuous based on the detection output of the second detection means. It is something.

That is, in the present invention, since the digital signal obtained by digitizing the analog signal is in a continuous state of maximum value data during an overflow period in which an overflow occurs, the digital signal is converted based on the continuous period of maximum value data. Open low data is formed by estimating the signal level of the original analog signal of the over low part.

〔Example〕

Hereinafter, one embodiment of the digital signal processing circuit according to the present invention will be described in detail with reference to the drawings.

In the embodiment shown in FIG. 2, the A/D converter 11 converts all the input analog signals supplied from the signal input terminal 1o into n-bit digital signals, and converts the input analog signals supplied from the signal input terminal 1o into n-bit data CB,
-Bn) i Output in parallel.

Here, the n-bit digital signal obtained by the A/D conversion circuit 11 has the most significant bit Bn as polarity □ data, and the least significant bit BI as n-1 bits (B
n, .

The maximum value of the digital signal output from the A/D converter 11 is detected by a maximum value detection section 2o using an n-1 manually operated AND gate 21.

That is, the AND gate 21 is connected to the A/D converter 1o.
The least significant bit Bl of the digital signal output from
-1 bit (Bn-1) data is input, and when each data is all logic "1", that is, the maximum value, all detection output signals of logic "1" are output.

The detection output signal output from the maximum value detection section 20 is as follows:
The signal is supplied to the first shift register 31 of the overflow data forming section 3o. The first shift register 31 is
The output of each stage of the four-stage shift register is supplied to the first AND gate 32, and the output of the final stage is further supplied to the second shift register 33. The second shift register 33 is an eight-stage shift register, which supplies the outputs of the four stages on the manual side to the second AND gate 34, and supplies the outputs of the four stages on the final stage to the third AND gate. It is supplied to gate 35. Here, each of the shift registers 31 and 33 has a transfer lock φCK supplied from the clock input terminal 4o.
The first AND gate 32 is constantly driven so that all the outputs of each stage of the first register 31 are logic "1", that is, the maximum value of the digital signal is determined by the maximum value detection section 20. The first overflow data Q of logic "1" when detected four or more times in succession. is supplied to the fourth AND gate 36 and output from the first signal output terminal 41.

Further, the fourth AND gate 36 is connected to the second AND gate 36.
The output of the D gate 34 is supplied, and the maximum value of the digital signal is detected eight times or more in the maximum value detection section 20 as a AND output of each output of the first and second AND gates 32 and 34. When continuously detected, the second overflow data forming section supplies the data to the fifth AND gate 37 and outputs it from the second signal output terminal 42.Furthermore, the fifth AND gate 37 3 A
The output of the ND gate 35 is supplied, and the maximum value detection section 20 detects the maximum value of the digital signal 12 times or more as a AND output of each output of the third and fourth AND gates 35 and 36. When continuously detected, third overflow data Q2- is output from the third signal output terminal 43.

That is, the first and second shift registers 31,
33, and first to fifth AND gates 32, 34
, 35, 36, and 37, the overflow data forming unit 30 determines that the period in which the maximum value data of the digital signal outputted from the A/D converter 10 is continuous is an overflow period, and Open low data Q according to the length of. Output yQlyQ2. usually,
In the case of an input analog signal with a simple waveform such as a sine wave signal, the overflow period length corresponds to the overflow signal level, so as in this embodiment, the open low period is directly detected from the digital signal and the overflow period is determined. Overflow data QQ formed according to the length of ,
Ql and Q2 can provide information indicating the overflow period and the open-low signal level of the input analog signal.

Next, in the embodiment shown in FIG. 3, an overflow of a digital signal obtained by digitizing an analog signal having a complicated spectrum such as an audio signal is detected by the digital signal processing circuit according to the present invention. .

In this embodiment, the data of each bit of the digital signal is supplied to the AND gate 51 of the maximum value detection section 50 and also to the difference detection circuit 61 of the overflow data formation section 60. The maximum value detection section 50 detects the maximum value of the digital signal, and outputs a detection output signal of logic "1" when the data of the digital signal is the maximum value, as in the above-described embodiment.

The detection output signal output from the maximum value detection section 50 is
The signal is supplied to a counter circuit 62 and a differential data detection circuit 61 of an overflow data forming section 60 .

The counter circuit 62 performs a counting operation during a period in which the detection output signal output from the maximum value detection section 50 is at logic "1", and calculates count output data p indicating the length of the overflow period. It is supplied to the processing section 63. However, the differential data detection circuit 61 sequentially detects the differential coefficient of the digital signal data, that is, the differential data between the current data and the data one clock ago, and detects the differential coefficient from the maximum value detection section 50. The difference data q when the output signal becomes logic "1" is held and supplied to the arithmetic processing section 63.

The arithmetic processing section 63 calculates data p indicating the length of the overflow period supplied from the counter circuit 62 and difference data q indicating the differential coefficient of the data at the start of overflow supplied from the differential data detection circuit 61. Based on this, the thickest value of the overflow part (J is calculated as follows, and the entire overflow data D is formed.

That is, assuming that the digital signal data is not open low, the signal level y of the original analog signal indicated by the digital signal data is as follows: 3'=-a(x-b)2+c, where C is the thickest value. The vicinity of a portion of the overflow can be approximated by a quadratic expression of X (see FIG. 4). If the maximum level of the analog signal at which the digital signal actually overflows is m, then the digital signal overflows when y>m, the length of the overflow period p is 70, and the differential coefficient q at the start of overflow is is 9225 stones;
5 Therefore, the maximum value C is determined by the number of bits of the digital signal. m1 The above calculation process is performed using the data p given by the force counter circuit 62 and the difference data q given by the difference data detection circuit 61. 63, it can be calculated as qC--10m.

In each of the embodiments configured as described above, when the signal level of the input analog signal to be A/D converted is excessive and the digital signal is overflowing, the input analog signal before digitization is successively referred to. The overflow state can be directly detected from the digital signal after digitization without any trouble, and the configuration of the circuit required for this detection process is also extremely simple.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, the digital signal processing circuit according to the present invention directly detects that the data of the digital signal obtained by digitizing the analog signal is overflow, and corrects the overflow part. The overflow data estimated from the original analog signal can be fully formed and output, and the intended purpose can be fully achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example of a signal processing circuit that performs overflow detection of a digital signal. FIG. 2 is a block diagram showing an embodiment of a digital signal processing circuit according to the present invention. FIG. 3 is a block diagram showing another embodiment. FIG. 4 is an explanatory diagram for explaining the principle of operation of the arithmetic processing unit in this embodiment. Person Sony Corporation Representative Patent Attorney Akira Koike

Claims (1)

[Claims] A first detection means for detecting the maximum value data of the digital signal, a second detection means for detecting a period in which the detection output by the first detection means is continuous, and based on the detection output by the second detection means. A digital signal processing circuit that is completely equipped with data forming means for forming and outputting overlow data corresponding to a period in which the maximum value data is continuous.