JPH01229521A - Noise suppressing circuit - Google Patents

Abstract

PURPOSE:To prevent noise level when no signal exists by replacing low order (n-m) bits in an n-bit digital signal with '0' by a selector when high order (m) bits are all '0', and outputting it for a prescribed time. CONSTITUTION:The high order (m) bits out of the output of an A/D converter 2 with n-bit resolution and m-bit accuracy are added to a no-signal detecting means 3, and whether the high order (m) bits are all '0' or not is detected here. When the high order (m) bits are all '0', it is decided that a signal is not inputted to the A/D converter, namely, no signal, and when this state continues for the prescribed time, the low order (n-m) bits of the n-bit digital signal outputted from the A/D converter 2 are replaced with '0' and it is outputted. Thus, even when the '0' point of the analog/digital converter 2 shifts near to a threshold value, the noise level when no signal exists does not increase.

Description

[Detailed Description of the Invention] [Summary] Regarding a noise suppression circuit used in an analog/digital converter that converts an analog signal such as voice into a digital signal, the zero point of the analog/digital converter is shifted to near a threshold value. The purpose of this method is to prevent the noise level from increasing when there is no signal, and when converting an analog signal to a digital signal using an analog/digital converter with n-bit resolution and 9m-bit accuracy, a no-signal detection means for detecting whether upper m bits of the n-bit digital signal outputted from the digital signal are all "0"; and a counting means whose counting operation is controlled by the output of the no-signal detection means. , and a selector for selecting the lower (n-m) hits or "0" of the digital signal in response to the output of the counting means, and for a predetermined period of time, all of the upper m (n-m) hits or "0" are set to "0". At this time, the selector is configured so that the lower (n-m) bits of the n-bit digital signal are replaced with "0" and output.

[Industrial application field]

The present invention relates to a noise suppression circuit for an analog/digital converter that converts an analog signal such as voice into a digital signal.

With the development of digital signal processing for audio, images, etc., requirements regarding the number of bits, precision, and speed for analog/digital converters (hereinafter abbreviated as A/D converters) are becoming stricter.

On the other hand, after adjusting the zero point of the A/D converter, if the zero point moves to near the threshold of the least significant digit LSB due to A degree fluctuation, etc., the noise during no signal increases, so the noise level during no signal increases. A noise suppression circuit that does not increase the noise is required.

[Conventional Technique] FIG. 3 shows a block diagram of a conventional example. As shown in the figure, the zero adjustment of the A/D converter 1 is performed by adjusting the variable claw resistor Rv. In order to reduce the movement of the zero point after adjustment, the offset resistor Rv, which is composed of the resistors R and -R3, is In addition to lowering the temperature coefficient of the adjustment circuit, the temperature drift of the input signal is also reduced.

Now, the A/D converter 1 that has been zero-adjusted as described above is
When the conversion characteristics are as shown in the figure, the input analog signal with amplitude is converted to a digital signal of OO...100, and when no analog signal is input, or when there is no signal, it is converted to a digital signal of OO...000. A digital signal is output.

[Problem to be solved by the invention]

Here, as shown in Figure 5, the resolution of a 12-bit, full-scale 10V A/D converter is 2.4mV, and 1
The resolution of a 6-bit A/D converter with a full scale of 10 V is 0.15 mV, and the resolution decreases as the number of bits increases.

On the other hand, as described above, measures have been taken to reduce the movement of the zero point after adjustment, but it is difficult to reduce the movement corresponding to one resolution.

For this reason, when the zero point moves to the vicinity of the LSB threshold value B in FIG. 4, the A/D converter receives 00...000. Since a digital signal of OO...001 is output, there is a problem that the noise level increases when there is no signal.

An object of the present invention is to prevent the noise level from increasing when there is no signal even if the zero point of an analog/digital converter shifts to near a threshold value.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 2 is an analog signal with n-bit resolution and 1 m-bit precision.
In the digital converter, 3 is a no-signal detection means for detecting whether or not the upper m bits of the n-bit digital signal outputted from the analog/digital converter are all "0".

Further, 4 is a counting means whose counting operation is controlled by the output of the no-signal detecting means, and 5 is the lower (n - m) bits or 70" of the digital signal corresponding to the output of the counting means.
This is a selector that selects.

[Effect]

In the present invention, the upper m bits of the output of the A/D converter 2 with n-bit resolution and 1 m-bit precision are applied to the no-signal detection means 3, and it is detected here whether or not all the upper m bits are "0".

(1) When all upper m bits are “0” A/D converter 2
When this state continues for a predetermined period m, the lower (n
-m) Replace the bit with "0" and output.

(2) If all upper bits are not O', there is no signal, so the counting means 4 is reset and all n-bit digital signals output from the A/D converter 2 are sent out.

That is, when the output of the A/D converter is small and is considered as noise when there is no signal, this noise is replaced with "0" and output, so that the noise when there is no signal does not increase.

〔Example〕

FIG. 2 shows an embodiment of the invention. Here, the NOR gate 31 represents a component of the no-signal detection means 3, and the counter 41 represents a component of the counting means 4. Below, n=16, m=1
4, the operation shown in FIG. 2 will be explained.

First, the A/D converter 2, which has a 16-bit resolution and 14-bit accuracy, converts an input analog signal into a 16-bit digital signal using conversion control pulses and outputs it. Bit (Bus~nz) to N
In addition to the OR gate 31, these upper 14 bits are all ““
0” is detected.

(If the upper 14 bits of 11 are all "0", the H level is output from the NOR gate 31, so the 1 counter 41 is not reset and counts the input conversion control pulses.

Then, the no-signal state continues for a predetermined period of time, and the counter 4
The selector 5 is switched to the "0" side by the overflow signal output when the count value of 1 overflows, and the lower 2 bits of the 16-bit digital signal output from the A/D converter 2 are set to that value. 00 regardless
is replaced with and output. (2) If the upper 14 bits are not all "0", the NOR gate 31 outputs an L level, so the counter 41 is reset, and the selector 5 is switched to the B+ and Bo sides, so the A/D converter outputs The 16 bits themselves are output.

In other words, if the output of the A/D converter is sufficiently small that it can be considered as noise when there is no signal (as mentioned above, the zero point fluctuates close to the LSB L threshold voltage due to one temperature drift after zero adjustment, etc.) (including cases where the output is unstable due to minute noise), this noise is replaced with 00 and output, so the noise when there is no signal does not increase.

〔Effect of the invention〕

As described above in detail, the present invention has the effect that the noise level does not increase when there is no signal.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention. Figure 2 is a block diagram of an embodiment of the present invention. Figure 3 is a block diagram of a conventional example. Figure 4 is an example of ideal unipolar A/D conversion characteristics. 5
The figure shows an explanatory diagram of the resolution of the A/D converter. In the figure, 2 is an analog/digital converter, 3 is a no-signal detection means, 4 is a counting means, and 5 is a selector.

Claims (1)

[Claims] Analog/digital converter (2) with n-bit resolution and m-bit precision (n and m are each positive integers, n>m)
When converting an analog signal into a digital signal using
The upper m bits of the bit digital signal are all “
0'' or not; a counting means (4) whose counting operation is controlled by the output of the no-signal detection means; and a digital signal corresponding to the output of the counting means. Lower part of (
n-m) bit or a selector that selects “0” (
5), and when the upper m bits are all "0" for a predetermined time, the lower (n-m) bits of the n-bit digital signal are set to "0" by the selector (5). A noise suppression circuit characterized in that it is configured to be replaced and output.