JP2551365B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device capable of supporting both progressive scan (sequential scan) and interlace scan (interlaced scan) scanning systems.

[0002]

2. Description of the Related Art In the interlaced scan system in the field of television signal processing, the required video signal bandwidth is half that of the progressive scan system. Therefore, it is widely used for standard television (NTSC system) and industrial televisions. Has been adopted.

On the other hand, when the interlaced scan system is used, the video signal bandwidth is halved, but it has been pointed out that deterioration of image quality such as interlaced flicker cannot be ignored (NHK Giken monthly report, December 1984, p. 5
07-512). Therefore, a workstation, a computer terminal device or an EDTV (Extended Definition) that requires high-precision images is required.
Progressive scanning is being adopted for second generation cameras and receivers such as TVs.

Therefore, a solid-state image pickup device, which is a camera, is required to be compatible with both the progressive scan and the interlace scan, and various proposals have been made.

4 and 5 are views showing the structure of a conventional CCD image pickup device of this type, which is disclosed in Japanese Patent Laid-Open No. 1-220986. Referring to FIG. 4, the imaging unit 1
1, a horizontal drive unit 12, a switch circuit 13, a clock generator 14, an adder 15 and a clock source 16.

As shown in FIG. 5, the image pickup section 11 includes a photosensitive section 17 composed of, for example, 500 vertical × 400 horizontal photodiodes, and, for example, 500 arranged adjacent to each vertical line of the photosensitive section 17. Vertical transfer unit 18 including stages
And the first and second line transfer units 19 and 20 provided adjacent to these, and the first and second line transfer units 19 and 2.
It is composed of a gate 21 interposed between 0s. A pulse for operating the vertical transfer unit 18 is input from the terminal 22.

The horizontal drive unit 12 horizontally drives the first and second line transfer units 19 and 20 based on the clock supplied from the clock generator 14.

The switch circuit 13 performs various switching based on the selection pulse supplied from the clock generator 14.

The clock generator 14 receives the clock generated by the clock source 16 and outputs pulses for opening and closing the gate 21, 28 MHz and 14 MHz clocks supplied to the horizontal drive unit 12, and a switching circuit 13 for switching. To output the selection pulse.

The adder 15 includes the first and second line transfer units 1
The signals output from 9 and 20 are superimposed.

In the progressive scan system, one frame is composed of 525 progressive scanning signals in 1/30 seconds. When a field shift pulse is applied to the terminal 22 in the vertical blanking period, the charges photoelectrically converted and accumulated in the photosensitive section 17 are transferred to the vertical transfer section 18.

At this time, the switch 13 is switched to the A side. Therefore, the horizontal driving unit 12 includes the clock generator 14
The first and second line transfer units 19 and 20 are driven based on the supplied 14 MHz clock, and the gate 21 is closed by the low level (0) pulse from the clock generator 14. Charge is not supplied from the first line transfer unit 19 to the second line transfer unit 20. As a result, only the charges from the first line transfer unit 19 are output from the output terminal 23.

In this way, the charges sent from the vertical transfer section 18 are sequentially sent to the first line transfer section 19 and output from the output terminal 23 as a video signal.

Next, in the interlaced scan system,
It is assumed that one frame consists of first and second fields, and these two fields each consist of 250 scanning signals in 1/60 seconds.

During the vertical blanking period, the terminal 22
When a field pulse is applied to the vertical transfer section 18, the charges photoelectrically converted and accumulated in the photosensitive section 17 are transferred to the vertical transfer section 18. At this time, the switch 13 is switched to the B side. Therefore, the horizontal drive unit 12 drives the first and second line transfer units 19 and 20 based on the 28 MHz clock supplied from the clock generator 14, and the gate 21 is supplied with “H” from the clock generator 14. The pulse causes an open state, that is, a state in which signal charges are supplied from the first line transfer unit 19 to the second line transfer unit 20, and the signal charges from the first and second line transfer units 19 and 20 are added.
In the state of being superposed at 5, the state is outputted from the second output terminal 24.

The signal charges sent from the vertical transfer unit 18 are sequentially sent to the first and second line transfer units 19 and 20, and the signal charges from the first and second line transfer units 19 and 20 are added. And output terminals 24 to 25
The video signal of the first field and the video signal of the second field corresponding to 0 scanning lines are alternately output.

By doing so, it is constructed so as to be compatible with both interlace scanning and progressive scanning.

[0018]

In such a configuration of the prior art, the horizontal transfer registers 19 and 2 which are line transfer units.
Since it is necessary to provide two sets of 0s, there is a drawback that the structure is complicated and the rate of signal transfer failure due to element failure in these registers becomes large, resulting in deterioration of image quality.

Therefore, the present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a progressive scan and interlace with a simple structure having only one horizontal transfer register. An object of the present invention is to provide a solid-state imaging device capable of supporting both scanning and scanning methods.

[0020]

A solid-state image pickup device according to the present invention comprises a photoelectric conversion element group arranged in a matrix.
Vertical transfer means provided for each line of the photoelectric conversion element for vertically transferring the charges from the photoelectric conversion element, horizontal transfer means for horizontally transferring the charges transferred from each line of the vertical transfer means, and Charge transfer means for absorbing the charge of each transfer element of the equal horizontal transfer means, and during the progressive scan, the charge transferred by the vertical transfer means for each horizontal blanking period is transferred horizontally for each line. After transfer to the means, horizontal transfer is performed at a predetermined frequency, and during interlaced scanning, the charges transferred by the vertical transfer means are absorbed by one line through the horizontal transfer means in the first half of each horizontal blanking period. Is absorbed by the means and transferred to the horizontal transfer means for one line in the latter half of each horizontal blanking period, and then to the predetermined frequency. Characterized in that to perform the horizontal transfer at half the frequency.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. In the following, for convenience, a case will be described as an example in which the present invention is adapted to the NTSC television system of 525 scanning lines (485 effective scanning lines).

FIG. 1 is a block diagram showing the arrangement of a CCD image pickup device according to an embodiment of the present invention, which is composed of photoelectric conversion elements of vertical 485 pixels × horizontal n pixels (n is a positive number such as 768 or 948). A photosensitive unit 1, a vertical register 2 including 485 transfer stages arranged along each vertical line of the photosensitive unit 1, a horizontal register 3 electrically connected to one end of the vertical register 2, and a horizontal register 3, a drain region 4 provided on the side opposite to the vertical register 2 for absorbing unnecessary charges, a drain gate 5 controlling transfer of charges from the horizontal register 3 to the drain region 4, and one end of the horizontal register 3. And a charge detection circuit 6 connected to the.

ΦV1 to φV4 are drive pulses for the vertical register 2, φH1 to φH2 are drive pulses for the horizontal register 3, and φ
D indicates a gate pulse, and VD indicates a drain bias.

FIG. 2 is a diagram for explaining a driving method at the time of progressive scanning. In the same figure, the signal charge read pulse 7 in the vertical blanking period (see FIG. 2A)
Signal charges read from the photosensitive section 1 to the vertical register 2 (see symbols Δ, ◯, from the side closer to the horizontal register 2).
(Indicated by □) is vertically transferred in the vertical register 2 by one clock of the drive pulses φV1 to φV4 in each horizontal blanking period.

After that, the signal charges transferred to the horizontal register 3 are transferred in the horizontal direction by the drive pulse φH at a frequency twice as high as that in the interlaced scan described later, and are transferred as a time series video signal to the outside through the charge detection circuit 6. Is output to.

FIG. 3 is a diagram for explaining a driving method during interlaced scanning. In the figure, the charges read from the photosensitive section 1 to the vertical register 2 by the signal charge read pulse 8 (see FIG. 3A) in the vertical blanking period of the first field are driven in each horizontal blanking period. Pulses φV1 to φV4 are transferred vertically in the vertical register 2 every two clocks.

Of the charges transferred to the horizontal register 3, unnecessary charges (indicated by a symbol Δ) are such that the drain gate pulse φD applied to the drain gate 5 is turned on in the first half of each horizontal blanking period. Is swept away in the drain region 5.

Next, the signal charges that contribute to the interlace transferred to the horizontal register 3 (denoted by the symbol ◯)
Are transferred in the horizontal direction at a frequency half that of the progressive scan described above, and are output to the outside as a time-series video signal via the charge detection circuit 6. After that, sweeping out unnecessary electricity and outputting signal charges are repeated for each horizontal blanking. Next, in the second field, the interlace operation is performed by using the charges indicated by the symbols Δ and □ as signal charges and the charges indicated by the symbol ◯ as unnecessary charges.

In the embodiment of the present invention, the case of applying to the interlace transfer type CCD image pickup device has been described, but it is of course applicable to the frame transfer type CCD and the frame interline transfer type CCD. Further, the number of scanning lines of the CCD is not limited to 525, and it can be applied to CCDs having any number of scanning lines such as 1125 which is compatible with high definition.

[0030]

As described above, according to the present invention, both scanning systems can be supported with a simple structure in which only one set of horizontal transfer registers is used. Therefore, the image quality is low and the reliability is high. There is an effect that the solid-state imaging device can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2A and 2B are operation waveform diagrams during progressive scanning according to the embodiment of the present invention, in which FIG. 2A is an operation waveform diagram in a frame period and FIG. 2B is an operation waveform diagram in a horizontal scanning period.

FIG. 3 is an operation waveform diagram at the time of interlaced scanning according to the embodiment of the present invention, in which (A) shows each operation waveform diagram in a frame period and (B) shows a horizontal scanning period.

FIG. 4 is a block diagram showing an example of a conventional solid-state imaging device.

FIG. 5 is a diagram showing a part of details of FIG. 4;

[Explanation of reference numerals] 1 photosensitive section 2 vertical register 3 horizontal register 4 drain region 5 drain gate 6 charge detection circuit

Claims (2)

(57) [Claims] 1. A photoelectric conversion element group arranged in a matrix, and vertical transfer means provided for each line of the photoelectric conversion element to vertically transfer charges from the photoelectric conversion element,
It has horizontal transfer means for horizontally transferring the charges transferred from each line of the vertical transfer means, and charge absorbing means for absorbing the charges of each transfer element of these horizontal transfer means. The charges transferred by the vertical transfer means for each horizontal blanking period are transferred to the horizontal transfer means one line at a time and then transferred in the horizontal direction at a predetermined frequency.
The electric charge transferred by the vertical transfer means is absorbed by the charge absorption means by one line through the horizontal transfer means in the first half of each horizontal blanking period, and by one line in the latter half of each horizontal blanking period. A solid-state image pickup device, characterized in that after being transferred to a horizontal transfer means, horizontal transfer is carried out at a frequency of 1/2 of the predetermined frequency. 2. The charge absorbing means is configured so that a gate is opened during interlaced scanning to electrically connect each transfer element of the horizontal transfer means and the charge absorbing means. 1. The solid-state imaging device according to 1.