JP2551046B2 - Multilayer circuit board - Google Patents
Multilayer circuit boardInfo
- Publication number
- JP2551046B2 JP2551046B2 JP62278837A JP27883787A JP2551046B2 JP 2551046 B2 JP2551046 B2 JP 2551046B2 JP 62278837 A JP62278837 A JP 62278837A JP 27883787 A JP27883787 A JP 27883787A JP 2551046 B2 JP2551046 B2 JP 2551046B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- wiring conductor
- multilayer circuit
- internal wiring
- dielectric constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は多層回路基板、特に、周波数の高い信号を扱
う高周波回路に適した多層回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board, and more particularly to a multilayer circuit board suitable for a high frequency circuit handling a high frequency signal.
（従来の技術） 従来、多層回路基板としては、誘電率が約４と低く、
製造工程も簡単なガラスエポキシ材に代表される有機高
分子材料からなる基板が汎用されているが、これらの多
層回路基板は、耐熱性の点からICチップを直付けでき
ず、また、20〜30層のような多層化ができないという問
題があった。このため、アルミナセラミック材を基板材
料としたものが実用に供されてきている。(Prior Art) Conventionally, as a multilayer circuit board, the dielectric constant is as low as about 4,
Substrates made of organic polymer materials, typified by glass epoxy materials, which are easy to manufacture, are widely used, but these multi-layer circuit boards cannot be directly attached to IC chips because of their heat resistance. There was a problem that it could not be multi-layered like 30 layers. For this reason, those using an alumina ceramic material as a substrate material have been put to practical use.
（発明が解決しようとする問題点） しかしながら、アルミナセラミック材は誘電率が９〜
10と高いため、電子機器、例えば、スーパーコンピュー
タの高速化に伴ない、100〜300MHzと高いクロック周波
数が採用されるようになると、基板材料の誘電率が無視
できなくなり、従来の多層回路基板では、内部配線導体
の配線長が長くなる部位での信号の伝搬遅延が問題とな
っきている。また、基板材料の誘電率が高い場合、配線
導体間の静電容量（Ｃ）大きくなり、信号の減衰とイン
ピーダンスの低下をもたらすという問題もある。(Problems to be Solved by the Invention) However, an alumina ceramic material has a dielectric constant of 9 to
Since it is as high as 10, electronic devices such as supercomputers are becoming faster, and when a high clock frequency of 100 to 300 MHz is adopted, the dielectric constant of the substrate material cannot be ignored, and in conventional multilayer circuit boards The signal propagation delay at the portion where the wiring length of the internal wiring conductor becomes long has become a problem. Further, when the dielectric constant of the substrate material is high, there is a problem that the capacitance (C) between the wiring conductors becomes large, resulting in signal attenuation and impedance reduction.
この問題を解決する手段として、アルミナセラミック
材に比べ誘電率の小さな材料を内部配線導体層間に介在
させたもの（特公昭56−39077号公報に）、あるいは絶
縁体層に空洞部を設け構造的に誘電率を低減させるよう
にしたもの（特開昭56−15098号公報）などが提案され
ているが、誘電率が低く、製造がより容易な絶縁体層材
料の開発が要望されている。As a means for solving this problem, a material having a dielectric constant smaller than that of an alumina ceramic material is interposed between the inner wiring conductor layers (Japanese Patent Publication No. 56-39077), or a hollow portion is provided in the insulator layer for structural purposes. Although a material having a reduced dielectric constant (Japanese Patent Laid-Open No. 56-15098) has been proposed, the development of an insulating layer material having a low dielectric constant and easier to manufacture is desired.
従って、本発明の目的は、誘電率をより低減でき、周
波数の高い信号の伝搬遅延や信号の減衰の少ない多層回
路基板を提供することにある。Therefore, an object of the present invention is to provide a multi-layer circuit board which can further reduce the dielectric constant and which has a small propagation delay of a high frequency signal and a small signal attenuation.
（問題点を解決するための手段） 本発明は、前記問題点を解決する手段として、基本的
には、内部配線導体と絶縁体基板との界面の一部に空洞
部を形成を介在させることによって、絶縁体層の誘電率
を小さくし、構造的に信号の伝搬遅延を抑制するように
したものである。(Means for Solving the Problems) As a means for solving the above problems, the present invention basically involves forming a cavity at a part of the interface between the internal wiring conductor and the insulating substrate. In this way, the dielectric constant of the insulator layer is reduced, and the signal propagation delay is structurally suppressed.
即ち、本発明の要旨は、複数の絶縁体層を積層、一体
化し、絶縁体層間に内部配線導体を形成してなる多層回
路基板において、内部配線導体と絶縁体層との界面の一
部に空洞部を形成してなることを特徴とする多層回路基
板にある。That is, the gist of the present invention is to provide a multilayer circuit board in which a plurality of insulating layers are laminated and integrated to form an internal wiring conductor between the insulating layers, and a part of the interface between the internal wiring conductor and the insulating layer is formed. A multilayer circuit board is characterized in that a cavity is formed.
前記空洞部は内部配線導体の片側表面の全面と該片側
表面に相対する絶縁体層との間に形成された比較的大き
な空洞部であっても良く、また、内部配線導体の片側面
と該表面に相対する絶縁体層との間の多孔質層により形
成された微少な空洞部であっても良い。The hollow portion may be a relatively large hollow portion formed between the entire surface of one side surface of the internal wiring conductor and an insulating layer facing the one side surface. It may be a minute cavity formed by a porous layer between the insulating layer facing the surface.
絶縁体層の形成材料としては、公知のガラスエポキシ
材、ポリイミド材などの有機高分子材料；アルミナセラ
ミック、結晶化ガラス材、マイカレックス材等の無機材
料など任意の材料を使用できるが、できる限り誘電率の
小さな材料を採用するのが好適である。特に、絶縁体層
をセラミック材料とし、内部配線導体として銅を採用す
るのが好適である。As a material for forming the insulator layer, any known material such as a glass epoxy material, an organic polymer material such as a polyimide material; an inorganic material such as an alumina ceramic, a crystallized glass material, or a mycarex material can be used, but as far as possible, It is preferable to use a material having a low dielectric constant. In particular, it is preferable to use a ceramic material for the insulator layer and adopt copper as the internal wiring conductor.
また、セラミック材料としては、MgO:15％以下、Al2O
3:1〜30％、SiO2:25〜80％、CaO:15〜70％およびB2O3:
1.5〜５％からなるコージライト系低温焼結磁器組成物
が好適である。この磁器組成物は、５〜10の範囲内の任
意の誘電率が得られ、また焼結温度が850〜1000℃と、
アルミナセラミックの焼結温度1500〜1600℃に比べて著
しく低く、従って、配線導体材料として銀、銀−パラジ
ウム合金などの他、銅やニッケル等の安価な材料の使用
を可能にする。As a ceramic material, MgO: 15% or less, Al 2 O
3: 1~30%, SiO 2: 25~80%, CaO: 15~70% and B 2 O 3:
A cordierite low temperature sintered porcelain composition consisting of 1.5 to 5% is suitable. This porcelain composition can obtain an arbitrary dielectric constant within the range of 5 to 10, and has a sintering temperature of 850 to 1000 ° C.
The sintering temperature of the alumina ceramic is remarkably lower than 1500 to 1600 ° C., so that it is possible to use inexpensive materials such as copper and nickel in addition to silver, silver-palladium alloy, etc. as the wiring conductor material.
この磁器組成物を絶縁体層の材料とし、内部配線導体
として銅を使用する場合、銅の酸化を防止するため、焼
成雰囲気を非酸化性ましくは還元性雰囲気とするのが好
ましく、特に、微量の水蒸気を含有させた窒素ガス雰囲
気（通常、窒素99.7〜99.8％）とするのが好適である。
この場合、微量の水蒸気を含有させるのは、焼成時、絶
縁体層に残留する炭素を水性ガス反応によって完全に消
失させるためである。When this porcelain composition is used as the material of the insulator layer and copper is used as the internal wiring conductor, the firing atmosphere is preferably a non-oxidizing or reducing atmosphere in order to prevent oxidation of the copper, and in particular, A nitrogen gas atmosphere containing a small amount of water vapor (usually nitrogen 99.7 to 99.8%) is suitable.
In this case, a small amount of water vapor is contained in order to completely eliminate carbon remaining in the insulator layer by a water gas reaction during firing.
前記低温焼結磁器組成物の成分組成を前記範囲に限定
したのは次の理由による。MgOを15％以下としたのは、M
gOの含有量が15％を越えると焼結温度が1000℃以上にな
るからである。なお、MgOは0.1％でも十分にその効果を
奏するが、その含有量が０の場合には、熱膨張係数が8.
0×10−6/℃より大きくなり、シリコンチップを搭載し
たとき両者の熱膨張係数の差に起因するサーマルストレ
スによりシリコンチップにクラックを生じる恐れがある
ので前記範囲とした。また、Al2O3が１％未満では焼結
温度が1000℃以上になり、30％を越えると誘電損失が0.
2％以上になるので前記範囲とした。SiO2を25〜80％と
したのは、SiO2が25％未満では誘電率が10以上になって
信号の伝搬遅延が大きくなり、80％を越えると、抗折強
度が1500kg/cm2より小さくなるからである。The reasons for limiting the composition of the low-temperature sintered ceramic composition to the above range are as follows. The reason why MgO is reduced to 15% or less is that M
This is because when the content of gO exceeds 15%, the sintering temperature becomes 1000 ° C. or higher. Although 0.1% of MgO sufficiently exerts its effect, when its content is 0, the thermal expansion coefficient is 8.
0 × 10- 6 / ℃ becomes greater than was the above range because there is a possibility of causing cracks in the silicon chip by a thermal stress caused by difference in thermal expansion coefficient therebetween when mounting the silicon chip. When Al 2 O 3 is less than 1%, the sintering temperature is 1000 ° C or higher, and when it exceeds 30%, the dielectric loss is 0.
Since it is 2% or more, the above range is set. The SiO 2 content of 25 to 80% means that when the SiO 2 content is less than 25%, the dielectric constant becomes 10 or more and the signal propagation delay increases, and when it exceeds 80%, the bending strength is 1500 kg / cm 2 or more. Because it becomes smaller.
GaOを15〜70％としたのは、15％未満では抗折強度が1
500kg/cm2より小さくなり、70％を越えると誘電率が10
以上になって信号の伝搬遅延が大きくなるからである。
B2O3は焼結温度に多大な影響を及ぼすが、B2O3が1.5％
未満では焼結温度が1000℃以上になり、５％を越えると
抗折強度が1500kg/cm2より小さくなるので前記範囲とし
た。GaO is set to 15-70% because the bending strength is less than 15%.
It becomes smaller than 500 kg / cm 2 , and when it exceeds 70%, the dielectric constant is 10
This is because the signal propagation delay increases as described above.
B 2 O 3 has a great influence on the sintering temperature, but B 2 O 3 is 1.5%
If it is less than 1, the sintering temperature is 1000 ° C. or higher, and if it exceeds 5%, the bending strength becomes less than 1500 kg / cm 2 , so the above range was set.
（作用） 本発明に係る多層回路基板においては、絶縁体層と内
部配線導体との界面に空洞部が形成されているため、隣
あった内部配線導体間には誘電率が１の空気層と絶縁体
層とが介在することになり、全体としての誘電率が著し
く低減し、また、浮遊容量も、絶縁体層と内部配線導体
との界面に空洞部のない場合に比べて著しく低下する。(Operation) In the multilayer circuit board according to the present invention, since the cavity is formed at the interface between the insulator layer and the internal wiring conductor, an air layer having a dielectric constant of 1 is provided between the adjacent internal wiring conductors. Since the insulating layer is interposed, the dielectric constant as a whole is significantly reduced, and the stray capacitance is also significantly reduced as compared with the case where there is no cavity at the interface between the insulating layer and the internal wiring conductor.
次に、添付の図面を参照して本発明に係る多層回路基
板について説明する。Next, a multilayer circuit board according to the present invention will be described with reference to the accompanying drawings.
（実施例） 第１図において、多層回路基板１は積層して一体化さ
れた複数の絶縁体層２と配線導体３、４とから構成さ
れ、内部配線導体３の上側表面およびその側壁とその上
側の絶縁体層２との間には空洞部５が形成されている。
図中、６はスルーホールである。(Embodiment) In FIG. 1, a multilayer circuit board 1 is composed of a plurality of insulating layers 2 and wiring conductors 3 and 4 which are laminated and integrated, and an upper surface of an internal wiring conductor 3 and its side wall and its side wall. A cavity 5 is formed between the insulating layer 2 on the upper side.
In the figure, reference numeral 6 denotes a through hole.
前記構造の多層回路基板１は、例えば、次のようにし
て製造することができる。即ち、第２図イに示すよう
に、まず、所定寸法のセラミックグリーンシートＡ、
Ｂ、Ｃ、Ｄを用意し、中間層となるグリーンシートＢ、
Ｃの片側表面に内部配線導体形成用ペーストを印刷して
それぞれ所定の内部配線導体パターン10、12を形成した
後、各配線導体パターン10、12の上に可燃性ペースト11
を印刷して配線導体パターン10、12と同じパターンの可
燃性ペースト層11、13を形成する。この場合、スルーホ
ール印刷部には可燃性ペースト層を形成しない方が好ま
しい。The multilayer circuit board 1 having the above structure can be manufactured, for example, as follows. That is, as shown in FIG. 2A, first, a ceramic green sheet A having a predetermined size,
B, C, and D are prepared, and the green sheet B serving as an intermediate layer,
An internal wiring conductor forming paste is printed on one surface of C to form predetermined internal wiring conductor patterns 10 and 12, respectively, and then a flammable paste 11 is formed on each wiring conductor pattern 10 and 12.
Is printed to form flammable paste layers 11 and 13 having the same pattern as the wiring conductor patterns 10 and 12. In this case, it is preferable not to form a flammable paste layer on the through-hole printing portion.
次いで、バイアホールを形成し、該ホール部に銅ペー
ストを充填した後、グリーンシートＡ、Ｂ、Ｃ、Ｄを積
層して圧着し（第２図ロ）、さらにスルーホールを形成
した後、表面配線パターン15を印刷し、これを非酸化性
雰囲気中で焼成することにより製造できる（第２図
ハ）。Next, after forming a via hole and filling the hole portion with copper paste, green sheets A, B, C and D are laminated and pressure-bonded (FIG. 2B), and after forming a through hole, the surface is formed. It can be manufactured by printing the wiring pattern 15 and firing it in a non-oxidizing atmosphere (Fig. 2C).
ちなみに、絶縁体層の形成材料の原料として、SiO280
％、CaO:15％、B2O3:2.0％、Al2O3:2.0％およびMgO:0.3
％を用い、これらを秤量し、十分に混合した後、900℃
で仮焼し、これを粉砕して仮焼粉末を得、これに適量の
有機溶剤と有機バインダーを加えてスラリー化し、ドク
ターブレード法で形成した厚さ100μのセラミックグリ
ーンシートを用いて、前記方法で第１図の構造の多層回
路基板を製造したところ、可燃性ペーストを塗布しあっ
た内部配線導体の表面とそれに隣接するセラミック層と
の間には空洞部が観察され、信号の伝搬遅延は約7nsec/
mであった。By the way, as a raw material for the insulating layer forming material, SiO 2 80
%, CaO: 15%, B 2 O 3 : 2.0%, Al 2 O 3 : 2.0% and MgO: 0.3
%, Weigh them, mix well, and then 900
By calcination, pulverizing it to obtain a calcination powder, adding an appropriate amount of an organic solvent and an organic binder to form a slurry, and using a ceramic green sheet having a thickness of 100 μ formed by a doctor blade method, the method described above. When a multilayer circuit board having the structure shown in FIG. 1 was manufactured, a cavity was observed between the surface of the internal wiring conductor coated with the flammable paste and the ceramic layer adjacent to it, and the signal propagation delay was About 7 nsec /
m.
なお、内部配線導体形成用ペーストとして銅ペースト
を、可燃性ペーストとしてワニスを用いた。焼成は、窒
素雰囲気中1000℃で行った。A copper paste was used as the internal wiring conductor forming paste, and a varnish was used as the flammable paste. The firing was performed at 1000 ° C. in a nitrogen atmosphere.
（比較例） 実施例で容易したグリーンシートを適当な大きさにカ
ットした後、片側表面に銅ペースト用いて実施例と同じ
配線パターンを印刷し、乾燥させた。また、印刷された
グリーンシートにバイアホールを形成し、該ホール部に
銅ペーストを充填した後、複数枚積み重ねて圧着させ、
さらにスルーホールを形成した後、表面配線パターンを
印刷し、これを窒素雰囲気中1000℃で焼成して多層回路
基板を得た。(Comparative Example) The green sheet prepared in Example was cut into an appropriate size, and the same wiring pattern as that in Example was printed using a copper paste on one side surface and dried. In addition, after forming a via hole in the printed green sheet, filling the hole portion with copper paste, stacking a plurality of sheets and crimping,
Further, after forming through holes, a surface wiring pattern was printed and baked at 1000 ° C. in a nitrogen atmosphere to obtain a multilayer circuit board.
この多層回路基板の電気的特性を測定したところ、誘
電率は６で、信号伝搬遅延は約8nsec/mであった。When the electrical characteristics of this multilayer circuit board were measured, the dielectric constant was 6, and the signal propagation delay was about 8 nsec / m.
前記実施例および比較例の結果から、本発明に係る多
層回路基板は、絶縁体層の材料が比較例と同じであるに
も拘わらず、信号の伝搬遅延が顕著に抑制され、誘電率
が約４の材料に匹敵する性能を示すことが判る。From the results of the examples and the comparative examples, the multilayer circuit board according to the present invention, although the material of the insulator layer is the same as the comparative example, the propagation delay of the signal is significantly suppressed, the dielectric constant is about It can be seen that it has a performance comparable to that of the No. 4 material.
前記実施例においては、内部配線導体パターンの上に
可燃性ペーストを塗布し、該可燃性ペーストを消失させ
ることによって空洞部を形成しているが、可燃性ペース
トの代わりに、可燃性材料とセラミック粉末との混合ペ
ーストを配線導体パターン上に印刷し、焼成時に可燃性
材料のみを消失させてセラミック材料からなる多孔質層
を形成させ、その微少な孔を空洞部としても良い。ま
た、内部配線導体パターンの肉厚を厚く形成し、内部配
線導体の片側表面のみならず、その側壁と絶縁体層との
間にも空洞部を形成するようにしても良い。In the above-mentioned embodiment, the combustible paste is applied on the internal wiring conductor pattern and the cavity is formed by extinguishing the combustible paste. However, instead of the combustible paste, the combustible material and the ceramic are used. It is also possible to print a mixed paste with the powder on the wiring conductor pattern, to eliminate only the flammable material at the time of firing to form a porous layer made of a ceramic material, and to make the minute holes the hollow portions. Further, the internal wiring conductor pattern may be formed to have a large thickness, and a cavity may be formed not only on one surface of the internal wiring conductor but also between the side wall and the insulating layer.
（発明の効果） 以上の説明から明らかなように、本発明によれば、簡
単な構成により多層回路基板に於ける信号の伝搬遅延や
減衰を著しく低減できる。また、前記コージライト系磁
器組成物を絶縁体の材料として使用することにより内部
配線導体として銅等を使用できるため、製造コストの低
減を図ることができる。(Effects of the Invention) As is apparent from the above description, according to the present invention, it is possible to remarkably reduce the signal propagation delay and the attenuation in the multilayer circuit board with a simple configuration. Further, by using the cordierite-based porcelain composition as a material for the insulator, copper or the like can be used as the internal wiring conductor, so that the manufacturing cost can be reduced.
第１図は本発明の実施例を示す多層回路基板の断面図、
第２図は第１図の多層回路基板の製造過程での分解斜視
図である。 1:多層回路基板、2:絶縁体層、3,4:配線導体、5:空洞
部。FIG. 1 is a sectional view of a multilayer circuit board showing an embodiment of the present invention,
FIG. 2 is an exploded perspective view in the manufacturing process of the multilayer circuit board of FIG. 1: Multilayer circuit board, 2: Insulator layer, 3, 4: Wiring conductor, 5: Cavity part.
Claims (3)
化し、絶縁体層間に内部配線導体を形成してなる多層回
路基板において、内部配線導体の片側表面及びその両側
壁と前記片側表面に相対する絶縁体層との界面に空洞部
又は多孔質層を形成してなることを特徴とする多層回路
基板。1. A multilayer circuit board in which a plurality of ceramic insulating layers are laminated and integrated to form an internal wiring conductor between the insulating layers, wherein one side surface of the internal wiring conductor and both side walls and the one side surface are formed. A multi-layer circuit board, characterized in that a cavity or a porous layer is formed at an interface with an opposing insulating layer.
からなり、前記内部配線導体が銅であり形成されている
特許請求の範囲第１項記載の多層回路基板。2. The multilayer circuit board according to claim 1, wherein the insulating layer is made of a cordierite magnetic composition, and the internal wiring conductor is made of copper.
部配線導体が銅で形成されている特許請求の範囲第１項
記載の多層回路基板。3. The multilayer circuit board according to claim 1, wherein the insulating layer is made of ceramics, and the internal wiring conductor is made of copper.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62278837A JP2551046B2 (en) | 1987-11-02 | 1987-11-02 | Multilayer circuit board |
| US07/265,500 US4931354A (en) | 1987-11-02 | 1988-11-01 | Multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62278837A JP2551046B2 (en) | 1987-11-02 | 1987-11-02 | Multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01120095A JPH01120095A (en) | 1989-05-12 |
| JP2551046B2 true JP2551046B2 (en) | 1996-11-06 |
Family
ID=17602842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62278837A Expired - Lifetime JP2551046B2 (en) | 1987-11-02 | 1987-11-02 | Multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2551046B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0653652A (en) * | 1991-03-14 | 1994-02-25 | Nec Corp | Multilayer ceramic wiring board and manufacture of the same |
| JP6924106B2 (en) * | 2017-09-11 | 2021-08-25 | Ｋｙｂ株式会社 | Fluid property detector |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0231802Y2 (en) * | 1985-10-16 | 1990-08-28 |
-
1987
- 1987-11-02 JP JP62278837A patent/JP2551046B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01120095A (en) | 1989-05-12 |
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