JP2550686B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an information processing apparatus which adopts a virtual computer system or has a debug state.

[Prior Art] Conventionally, with respect to a debug interrupt, this type of information processing apparatus has been unable to specify a virtual computer for which a debug interrupt is desired to be generated. Further, the information processing device having the debug state has a debug interrupt for fetching an instruction, fetching an operand, and storing an operand. Further, in this type of information processing apparatus, even if the value of the segment base register becomes abnormal while the apparatus is operating as a virtual computer, this cannot be detected.

[Problems to be Solved by the Invention] In the above-described conventional information processing apparatus, when different virtual machines use the same address, both virtual machines have a drawback that a debug interrupt is detected.

The conventional debug function described above has a drawback in that a necessary condition cannot be set in an abnormality due to a failure of the device or a debug during evaluation of the device.

In the conventional information processing device described above, the value of the segment base register is set when the device is operating as a virtual computer.
Even if it is destroyed by a VM monitor program mistake, VMOS
Since the abnormal state cannot be detected above, the VMOS runs out of control, which requires a great deal of labor for analysis.

[Means for Solving the Problem] A first information processing apparatus of the present invention is, in an information processing apparatus employing a virtual computer system, a VM mode flag indicating that the apparatus is operating as a virtual computer, and the apparatus being debugged. A debug mode flag that indicates the status, a debug interrupt detection circuit that detects a debug interrupt, a virtual computer identification register that stores the virtual computer identification number of a virtual computer that is operating, and a debug interrupt that occurs A debug computer designating register that designates a virtual computer, a comparing unit that detects a match between a stored value of the virtual computer identification register and a stored value of the debug computer designating register, and the VM mode flag is operating as a virtual computer. And also indicates that the debug mode flag is in a debug state,
And, the debug interrupt detection circuit detects a debug interrupt,
And a control circuit for generating a debug interrupt when the comparison circuit detects that the stored value of the virtual computer identification register matches the stored value of the debug computer designating register. Further, in another embodiment, the first information processing apparatus of the present invention shows that the VM mode flag is not operating as a virtual computer, and the debug interrupt detection circuit detects a debug interrupt. Sometimes, the control circuit is also configured to generate a debug interrupt.

A second information processing apparatus of the present invention includes a debug mode register which indicates a debug state of the apparatus, an exception detection circuit which detects a program interrupt and creates an exception number, an address given by the exception number, and an exception number. The memory decoder that outputs the interrupt code to notify the corresponding software, the instruction count register that points to the software instruction that generated the program interrupt, and the interrupt code and the value of the instruction count register in the debug state are monitored and It has a debug detection circuit that detects that the value of the instruction count register has reached a specified value and generates a check signal.

The third information processing apparatus of the present invention includes a debug mode flag indicating that the apparatus is operating in a debug state, a VM mode flag indicating that the apparatus is operating as a virtual computer, a VM monitor and a VMOS. A data register that holds data to be compared with the upper bit value of the segment base register that is commonly used, and a value of the data register and an upper bit of the segment base register when the device is in a debug state and operating as a virtual machine It has a check circuit that generates a check signal when the bit values match.

[Operation] In the first information processing apparatus, since the debug interrupt is generated only in the designated virtual machine, the debug interrupt is generated only in the target virtual machine even if the same address is used in different virtual machines. Can be made.

Since the second information processing device checks the program interrupt code and the value of the instruction count register that points to the software instruction that generated the program interrupt, it can detect an illegal exception that should not occur.

The third information processing device detects the value of the segment base register used by the VM monitor if the value of the segment base register used by the VM monitor is loaded in the upper bit of the segment base register when the device is operating as a virtual machine in the debug state. , It is possible to detect an abnormality when the device operates as a virtual computer.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main part of a first embodiment of the information processing system of the invention.

This information processing apparatus has a VM mode flag 1, a virtual computer identification register 2, a debug computer designation register 3, a debug status flag 4, a debug mask register 5, a debug interrupt detection circuit 6, a comparator 7 and a logic gate. .

VM mode flag 1 is a tag that indicates that the device is operating as a virtual machine. When it is "0", it is a real machine mode.
When "1" indicates that the device is operating in virtual machine mode. The value of the VM mode flag 1 is output as the signal VM. The virtual machine identification register 2 is a register that holds a virtual machine identification number that distinguishes an operating virtual machine when the device is operating as a virtual machine (when the VM mode flag 1 is "1"). Output as VMID. The debug computer designation register 3 is a register for designating a virtual computer in which a debug interrupt occurs when the device is operating as a virtual computer, and is output as a signal DBGID. The debug status flag 4 is a flag indicating that the device is in a debug status. When it is "0", it is a normal status, and when it is "1"
Indicates that it is in a debug state. The value of the debug status flag 4 is output as the signal DBG. The debug mask register 5 is a mask register that holds mask information corresponding to each debug interrupt factor. In this embodiment, a 3-bit mask is used and signals msk0, msk1, msk2 are output. The debug interrupt detection circuit 6 is a circuit for detecting a debug interrupt factor such as an instruction fetch or an operand fetch, and in the present embodiment, a 3-bit debug interrupt detection signal dbg.
Suppose that 0, dbg1, dbg2 is output. The comparator 7 compares the signal VMID output from the virtual computer identification register 2 with the signal DBGID output from the debug computer specifying register 3, and outputs a coincidence signal (VMID = DBGID) when they match. The debug interrupt generation signal INT is output to the outside via the signal line 10. The debug interrupt generation signal INT is INT = (▲ ▼ + VM ・ (VMID = DBGID)) ・ DBG ・ (msk
0 ・ dbg0 ＋ mskl ・ dbgl ＋ msk2 ・ dbg2).

FIG. 2 is a block diagram showing the main part of the second embodiment of the present invention.

The information processing apparatus has a debug mode register 11, an exception detection unit 12, a memory decoder 13, an instruction count register 14, and a debug detection circuit 15.

The debug mode register 11 is a 2-bit register indicating that the device is operating in the debug mode. The 2-bit values DM0 and DM1 of the debug mode register 11 determine the debug detection condition as shown in the following table.

The exception detection unit 12 includes an exception detection circuit 16 and an exception detection circuit 16
It consists of an exception number register 17 that holds the exception number detected and coded by. Memory decoder 13 is an exception number register
Address is given by the exception number EN output from 17,
Outputs interrupt code pc to notify the software corresponding to exception number EN. The exception number EN is output via the signal line 100, and the interrupt code pc is output via the signal line 200. The instruction count register 14 is a register that adds the instruction word length (ILC) as the software instruction is executed and indicates the address of the software instruction being executed. The value IC held by the instruction count register 14 is output via the signal 300. The debug detection circuit 15 has registers 18, 19,
It is composed of a register 20, a comparator 21, a comparator 22, and a logic gate. The register 18 is a register that holds the interrupt code pc output by the memory decoder 13, and the output signal is the interrupt code PC. The interrupt code pc and the interrupt code PC have the same value. The register 19 is a register for setting an interrupt code to be detected, and the register 20 is a register for setting an IC value to be detected. The values held by the registers 19 and 20 are DPC and DIC, respectively. The comparator 21 is a comparator that detects a match between the interrupt codes PC and DPC, and the comparator 22 is a comparator that detects a match between the values IC and DIC held by the instruction count register 14. The debug detection circuit 15 determines the debug detection signal CHK according to the mode instructed by the debug mode register 11.
Is output to the outside via the signal line 400.

The debug detection signal CHK is CHK = DM0 ・ ▲ ▼ ・ (PC = DPC) ＋ ▲ ▼ ・ DM1
・ (IC = DIC) ＋ ▲ ▼ ・ ▲ ▼ ・ (PC = DPC)
・ (IC = DIC).

(PC = DPC) indicates that the comparator 21 has detected the coincidence of PC = DPC.

(IC = DIC) indicates that the comparator 22 has detected the coincidence of IC = DIC.

FIG. 3 is a block diagram showing a main part of a third embodiment of the information processing system of the invention.

The information processing apparatus has a debug mode flag 31, a VM mode flag 32, a data register 33, a segment base register 34, a comparator 35, and a logic gate.

The debug mode flag 31 is a flag indicating that the device is operating in the debug state. The value of this flag 31 is DBG
, Indicates a debug state when "1". The VM mode flag 32 is a flag indicating that the device is operating as a virtual machine. The value of this flag 32 is VMM, and when it is "1", it represents the VM mode. The data register 33 is a register for holding data for comparison with the upper bit data of the segment base register 34. The value held in this register 33 is DATA. The segment base register 34 is a register used by the VM monitor and the VMOS, and is a register to which the real address indicated by the head of the segment table is loaded.
When the VM monitor is operating (VMM = "0"), the value for VM monitor is loaded, and when the VMOS is operating (VM
M = “1”) is loaded with the value for VMOS. The segment base register 34 is loaded by executing a VM monitor software instruction. The value of the upper bits of the segment base register 4 is SBR (: 0-n) (n
Is optional). The comparator 35 is a comparator that compares DATA of the data register 33 with the upper bits SBR (: 0-n) of the segment base register 34 to detect a match. The check circuit is composed of a comparator 35 and a logic gate.

The signal CHK detected by the check circuit is CHK = DBG.VMM. (DATA = SBR (: 0-n)).

The debug mode flag 31 and the data register 33 can be set from a control microprogram or an external device, and the VM mode flag 32 and the segment base register 34 are set by a microprogram corresponding to a software instruction.

When the VM monitor operates (VM mode flag 32 = "0")
And the VMOS operate (VM mode flag 32 = "1"), the VM monitor manages the upper (O-n) bits of the segment base register 34 so that they do not overlap. This management is required to operate by allocating the VM monitor and VMOS segment table to different spaces. When the VMOS tries to load data into the segment base register 34, this operation is notified as an exception to the VM monitor, and the VM monitor executes the VMOS load operation instead, so that the VM monitor can execute the segment of the VM monitor. Manage tables and VMOS segment tables.

When the VM monitor makes a program error such as starting the VMOS while the segment base register 34 is loaded with an incorrect value, the VMOS will run out of control. When a system malfunction occurs as a result of a VMOS runaway, it is very difficult to analyze the cause and it takes a lot of labor and time.

[Effects of the Invention] As described above, according to the present invention, by generating a debug interrupt only in a designated virtual computer, even if different virtual computers use the same address, only the target virtual computer can use it. It has the effect of being able to generate a debug interrupt, and by checking the interrupt code of the program interrupt and the value of the instruction count register that points to the software instruction that generated the program interrupt independently or simultaneously, This has the effect of being able to detect illegal exceptions that are not allowed, and when the device is operating as a virtual machine in a debug state, if the value of the segment base register used by VM monitor is loaded in the upper bits of the segment base register, this should be Abnormality when the device operates as a virtual machine by detecting There is a detectable effect.

[Brief description of drawings]

FIG. 1, FIG. 2 and FIG. 3 are block diagrams showing the essential parts of the first, second and third embodiments of the information processing apparatus of the present invention. 1 ... VM mode flag 2 ... Virtual computer identification register 3 ... Debug computer designation register 4 ... Debug status flag 5 ... Debug mask register 6 ... Debug interrupt detection circuit 7 ... Comparator 10 ... Signal line 11 …… Debug mode register 12 …… Exception detection unit 13 …… Memory decoder 14 …… Instruction count register 15 …… Debug detection circuit 16 …… Exception detection circuit 17 …… Exception number register 18, 19, 20 …… Register 21, 22 …… Comparator 31 …… Debug mode flag 32 …… VM mode flag 33 …… Data register 34 …… Segment base register 35 …… Comparator 100,200,300,400,500 …… Signal line

Claims (3)

(57) [Claims] 1. An information processing apparatus employing a virtual computer system, wherein a VM mode flag indicating that the apparatus is operating as a virtual computer, a debug mode flag indicating that the apparatus is in a debug state, and a debug interrupt are set. A debug interrupt detection circuit to detect, a virtual computer identification register that stores the virtual computer identification number of the virtual computer that is operating, a debug computer designation register that specifies the virtual computer that causes the debug interrupt, and the virtual computer identification Comparing means for detecting a match between the stored value of the register and the stored value of the debug computer designated register, and showing that the VM mode flag is operating as a virtual computer, and that the debug mode flag is in the debug state. And the debug interrupt detection circuit detects a debug interrupt, and the comparison circuit performs the virtual calculation. When it is detected that the value stored in the identification register and the stored value of the debugging computer specified register match, the information processing apparatus characterized by comprising a control circuit for generating a debug interrupt. 2. The control circuit causes a debug interrupt even when the VM mode flag indicates that it is not operating as a virtual computer, and when the debug interrupt detection circuit detects a debug interrupt. The information processing apparatus according to claim 1, wherein: 3. An information processing apparatus having a debug state, a debug mode register indicating a debug state of the apparatus, an exception detection circuit for detecting a program interrupt and creating an exception number, and an address given by the exception number, A memory decoder that outputs an interrupt code that notifies the software corresponding to the exception number, an instruction count register that indicates the software instruction that generated the program interrupt, and monitors the interrupt code and instruction count register values when in the debug state. The information processing apparatus further comprises a debug detection circuit that detects that the interrupt code and the value of the instruction count register have reached the specified values and that generates a check signal.