JP2542439B2 - Bus slave device - Google Patents

Description

Detailed Description [Table of Contents] Outline Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problem Action Example Effect of the invention [Outline] Connection to a bus provided with an arbiter A bus slave device that is accessed in a split mode by a plurality of bus masters connected to the bus, and is intended to provide a device that enables downsizing of the system. Means for storing the requested level of bus mastership, and means for acquiring the bus mastership at the request level stored when the response to the split mode access was sent.

TECHNICAL FIELD The present invention relates to a bus slave device which is connected to a bus provided with an arbiter and which is accessed in a split mode by a plurality of bus masters connected to the bus.

In a system in which the bus mastership of multiple bus masters and bus slaves is managed by an arbiter, when a bus slave device with a slow response (hereinafter referred to as a bus slave) is accessed, the bus is occupied for a long time until the access is completed. As the bus is busy during this access,
Bus usage efficiency decreases.

Therefore, a bus slave having a slow response is accessed in the split mode.

[Prior Art] The split mode access is performed only for a bus slave having a slow response, and in this mode, the mastership of the bus is abandoned during the access.

After that, the bus slave becomes ready to respond, but the bus mastership is acquired by the request of the bus slave, and the response to the bus master of the access source is started.

Therefore, another access can be performed during the access in the split mode, so that the bus usage efficiency can be improved.

FIG. 6 illustrates the bus configuration of a system in which split access is performed.
14-1 ... 14-n, bus slaves 16-m ... 16-z request bus mastership from bus signal line * REQ1 ... n, m
... is given to the arbiter 10 via each z.

As a result, the required levels of the bus masters 14-1 ... 14-n and the bus slaves 16-m ... 16-z are determined, and the arbiter 10 should permit the mastership of the bus master 14 to obtain the bus mastership.
-1 ... or 14-n, or bus slave 16-m ...
-Or 16-z is decided according to the priority shown by the request level.

From the arbiter 10 to the bus master 14-1 ... or 14-
n, or the bus slaves 16-m ... or 16-z, are given permission to acquire the bus control right via the signal line * BG1 ... or z, and when the bus control right is acquired, the normal mode is acquired. Alternatively, access in split mode is started.

[Problems to be Solved by the Invention] However, the required level of bus mastership is different for each bus master and bus slave, and the mastership of bus mastership is given to each of them individually. The number of signal lines increases, their mounting efficiency decreases, and the system becomes large.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object thereof is to provide a bus slave device capable of reducing the number of bus signal lines and downsizing the system.

[Means for Solving the Problem] In FIG. 1 (A), a bus provided with an arbiter 10.
A plurality of bus masters 14-1, 14-2 ... 14-i and bus slaves 16-1, 16-2 ... 16-j are connected to 12 and any of the bus slaves (bus slave devices) 16- 1 is accessed in split mode by the bus master 14-1, 14-2 ... Or 14-i.

Bus slaves accessed in that split mode
16-1 includes bus masters 14-1, 14-2, ...
Or means for arranging the request level of the bus mastership sent from 14-i to the bus 12, and means 20 for obtaining the bus mastership at the request level stored at the time of sending the response to the split mode access , Are included as shown in FIG.

[Operation] According to the present invention, the request level of the bus mastership transmitted from the access source to the bus 12 is stored in the bus slave 16-1 accessed in the split mode, and the request destination of the access destination is transmitted when the response to the split mode access is transmitted. Since the bus slave 16-1 acquires the bus control right at the memory level, the bus slave 16-1 requests the acquisition of the bus control right by using the same bus signal line as the access source, and It will be possible to obtain an acquisition permit.

Therefore, it becomes unnecessary to distinguish the bus slave 16-1 accessed in the split mode from the other high-speed slaves 16-2 ... 16-j accessed in the normal mode at the request level.

Therefore, the bus signal lines used for requesting the acquisition of the bus control right and receiving the acquisition permission can be omitted for all the bus slaves 16-1, 16-2, ... 16-j.

For example, a system similar to that of FIG. 6 described above can be configured as shown in FIG. 2, and in this system, a bus signal line used to request acquisition of bus mastership and to receive the acquisition permission. Is only for bus masters 14-1 ... 14-n, and bus slaves 16-m ... 16
-Z is omitted (bus master 14-1.
..Preparing only the 14-n signal lines * REQ1 to n and * BG1 to n for the bus master 14-1 ... 14-n side and the bus slave 16-m ... 16-z side Commonly used, and reduce the number of signal lines by multiplying the number of bus slaves by 2.)

[Embodiment] In FIG. 3, a bus 12 provided with an arbiter 10 has signal lines * BR1 ... n, * BG1 ... for arbitration.
n, * BUSY, control signal line CLK, * START, * ACK, split cycle control signal line * PSTART, * PBUSY, address / data shared bus line A / D It is composed of BUS.

This bus 12 has an arbitration signal line * BR1.
..N, * BG1 ... n bus masters 14-1, 14-
2 ... 14-n are connected.

A disk controller board 16-1 and a memory boat 16-2 are also connected to the bus 12 as bus slaves, and a disk device 30 is connected to the disk controller board 16-1.

In this embodiment, the disk controller board 16-1 which has a slow response to the access is accessed in the split mode, and its configuration is shown in FIG.

In FIG. 4, the address decoder 40 has a bus line A / D.
BUS, signal line * PSTART is connected, and when the disk controller board 16-1 is accessed in split mode, the address decoder 40 sends the SCSI control circuit.
The access start of the disk device 30 is notified to 42.

From the SCSI control circuit 42, when the data transfer or response is ready, the drive circuit 44, BUSY control circuit 46,
An instruction is given to the ACK control circuit 48, and the SCS is given to the drive circuit 44.
When an instruction is given from the I control circuit 42, when the data can be transmitted from the drive circuit 44 to the signal lines * BR1 to BRn, the bus control right acquisition request * REQ1 ... Or n is asserted.

Further, after the SCSI control circuit 42 gives an instruction to the BUSY control circuit 46, if the acquisition of the control right of the bus 12 is confirmed by the BUSY control circuit 46 from the output of the multiplexer 50 and the level of the signal line * BUSY, the BUSY control circuit 46 is controlled. Busy signal from circuit 46 is signal line *
Dispatched to BUSY.

Further, when an instruction is given from the SCSI control circuit 42 to the ACK control circuit 48, an ACK signal for the access source is sent from the ACK control circuit 48 to the signal line * ACK.

The output of the latch 54 is given to the multiplexer 50 via the encoder 52, and the input of the signal line * BG1 ... Or n corresponding to the output is selected by the multiplexer 50 and output to the BUSY control circuit 46. To be done.

The output of the latch 54 is also given to the drive circuit 44 via the decoder 56.

Signal lines * PBUSY, * BR1 ... n are connected to the latch 54, and the bus control right input from any of the signal lines * BR1 ... n when the split mode access is started. Acquisition request * REQ1 ... or n is latch 54
It is stored and stored in.

The operation of this embodiment is described in FIG. 5. First, a bus mastership acquisition request * REQ1 is sent from the bus master 14-1 to the signal line * BR1 as shown in FIG. As shown in (H), acquisition of control of the bus 12 is permitted.

The access is performed in the normal mode as shown in FIG. 7B, and the memory board 16-is provided as shown in FIGS.
Data is written to 2.

Next, the bus master 14-2 sends a bus control right acquisition request * REQ2 to the signal line * BR2 as shown in FIG. 9G, and the bus 12 control right acquisition is permitted as shown in FIG. It

This access can be made to the disk controller board 16-1 in split mode as shown in FIG.
The bus control right at this time is abandoned during the access as shown in FIGS.

However, the signal line * PBUSY remains at the level indicating the split mode from the start of access as shown in FIG. 8E, and the request level (* REQ2) at this time is latched by the disk controller board 16-1.

When the bus 12 is released in this way, the bus master 14
The bus control right acquisition request * REQ1 is again sent from -1 to the signal line * BR1 as shown in FIG. 6F, and the bus 12 acquisition is permitted as shown in FIG.

The access is performed in the normal mode as shown in FIG.

This time, as shown in (J) and (K) of the figure, the memory board 16-
Data is read from 2.

Then, when the second normal access by the bus master 14-1 is completed, the latched request for acquiring bus mastership * REQ2 is sent from the disk controller board 16-1 to the signal line * BR2 as shown in FIG. Then, the acquisition of the bus control right is permitted as shown in FIG.

As a result, data transfer is performed between the disk controller board 16-1 and the bus master 14-2, and the completion of the split mode access is completed.

As described above, according to the present embodiment, the request level of bus mastership is latched at the access destination when the split mode access is started, and the latched request is resumed when the access is restarted. Since the bus mastership is obtained at the access destination using the level, it is not necessary to distinguish the access destination in the split mode and the normal mode by the request level.

Therefore, the bus signal line used for requesting acquisition of the bus control right and for receiving the acquisition permission can be omitted for all slave sides.

Therefore, it is possible to reduce the number of bus signal lines, improve the mounting efficiency of each master and slave, and further downsize the system.

[Effects of the Invention] As described above, according to the present invention, the number of bus signal lines to which a bus use right acquisition request is transmitted and the number of signal lines to which acquisition permission thereof is transmitted can be reduced to the number of bus masters, By using the split mode, it is possible to downsize a high-speed system capable of efficient access.

[Brief description of drawings]

 1 is an explanatory view of the principle of the invention, FIG. 2 is an explanatory view of a system to which the invention is applied, FIG. 3 is an explanatory view of the configuration of an embodiment, FIG. 4 is an explanatory view of the configuration of a disk controller board, and FIG. Is a time chart for explaining the operation of the embodiment, and FIG. 6 is an explanatory view of the prior art. 10 ...... Arbiter 12 ...... Bus 14-1, 14-2 ... 14-n ...... Bus master 16-1 ...... Disk controller board 16-2 ...... Memory board 30 ...... Disk device 40 ...... Address decoder 42 ...... SCSI control circuit 44 …… Drive circuit 46 …… BUSY control circuit 48 …… ACK control circuit 50 …… Multiplexer 52 …… Encoder 54 …… Latch 56 …… Decoder

Claims (1)

(57) [Claims] 1. A bus slave device connected to a bus provided with an arbiter and accessed in a split mode by a plurality of bus masters connected to the bus, wherein the bus mastership transmitted from the access source bus master to the bus. And a means for acquiring the bus control right at the request level stored at the time of sending the response to the access in the split mode, the bus slave device.