JP2540897B2 - Digital type ratio differential relay - Google Patents
Digital type ratio differential relayInfo
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- JP2540897B2 JP2540897B2 JP62324430A JP32443087A JP2540897B2 JP 2540897 B2 JP2540897 B2 JP 2540897B2 JP 62324430 A JP62324430 A JP 62324430A JP 32443087 A JP32443087 A JP 32443087A JP 2540897 B2 JP2540897 B2 JP 2540897B2
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は電力系統の母線等を保護するデジタル形比
率差動継電器に関するものである。Description: TECHNICAL FIELD The present invention relates to a digital ratio differential relay that protects a bus bar of a power system.
第3図は例えば、特開昭59−035526号公報に示された
従来の比率差動継電器の原理構成図であり、図におい
て、(1)は電力系統の母線、(2−1)〜(2−n)
は母線(1)に接続された各回線の電流を検出する変流
器(以下CTと称す)、(3−1)〜(3−n)はCT(2
−1)〜(2−n)に各々接続され、各回線の電流に比
例した交流量I1〜Inと絶対値量|E1|〜|En|を導出する入
力装置、信号IDは前記交流量I1〜Inを差動合成(ベクト
ル合成)して得る差動量、信号|ER|は前記絶対値量|E1|
〜|En|の内、最大値を導出した端子抑制量、(12)は比
率差動継電器で次の回路要素より構成されている。(1
3)は前記差動量IDのレベルを検出する第1要素、(1
4)は前記差動量IDに比例した絶対値量|E0|を出力する
抵抗、(15)は前記端子抑制量|ER|を出力する抵抗、
(16)は|ER|−|E0|>KRを検出する第2要素、(17)は
信号引延し回路、(18)はNOT回路、(19)はAND回路、
(20)は出力リレーである。FIG. 3 is a principle configuration diagram of a conventional ratio differential relay disclosed in, for example, Japanese Patent Laid-Open No. 59-035526, in which (1) is a bus of a power system and (2-1) to (). 2-n)
Is a current transformer (hereinafter referred to as CT) that detects the current of each line connected to the bus (1), and (3-1) to (3-n) are CT (2
-1) to (2-n), each of which is an input device for deriving an AC amount I1 to In and an absolute value amount | E1 | to | En | proportional to the current of each line, and the signal ID is the AC amount. The differential amount obtained by differentially combining (vector combining) I1 to In, the signal | E R | is the absolute value amount | E1 |
~ | En |, the maximum terminal value is the terminal suppression amount. (12) is a ratio differential relay and is composed of the following circuit elements. (1
3) is the first element for detecting the level of the differential amount I D , (1
4) is a resistor that outputs the absolute value amount | E 0 | proportional to the differential amount ID, and (15) is a resistor that outputs the terminal suppression amount | E R |
(16) is the second element that detects | E R | − | E 0 |> K R , (17) is a signal extension circuit, (18) is a NOT circuit, (19) is an AND circuit,
(20) is an output relay.
次に動作について説明する。第3図は電力系統の母線
(1)の事故を検出する母線保護装置に適用した例を示
しており、周知の比率差動原理を基本としている。常時
又は外部事故時においてCT飽和がない場合、差動量IDは
零のため第1要素(13)は不動作であるが、外部事故時
CT飽和が激しい場合、第1要素(13)は誤動作する。こ
の対策として第2要素(16)を設けたものであり、これ
を第4図を用いて説明する。Next, the operation will be described. FIG. 3 shows an example applied to a busbar protection device for detecting an accident on a busbar (1) of a power system, which is based on the well-known ratio differential principle. When there is no CT saturation at all times or during an external accident, the first element (13) does not operate because the differential amount I D is zero, but during an external accident
When the CT saturation is severe, the first element (13) malfunctions. As a countermeasure against this, a second element (16) is provided, which will be described with reference to FIG.
波形IFは事故点に流れる電流波形の一例で、実際の事
故電流波形はCTの飽和に対して最も過酷な条件下にあ
る。すなわち、事故発生時に過渡直流分電流が交流分電
流ピーク値に対し100%重畳したケースであり、交流分
電流をIFP、直流分電流の減衰時定数をTとすれば、事
故電流 で表わされる。波形I1は外部事故端のCT2次電流の波形
例であり、この外部事故端(流出端)CTの1次電流とし
ては波形IFで、大きさは事故電流の大きさと同一になる
ため最も飽和しやすい条件にある。波形の斜線部がCT2
次電流波形であり、点線はCTが飽和していない時を表わ
している。波形I2は誤差の差動電流であり、きびしい条
件として流入端CTが不飽和で、流出端(事故端)CTのみ
が波形I1のように飽和したとすれば、誤差差動電流I2と
しては波形IFと波形I1の差が発生することになるので、
斜線に示すような波形となる。この時、第3図の比率差
動継電器(12)の入力としては、動作入力ID第4図の波
形I2が印加され、又抑制入力|ER|としては、波形|I1|が
印加されるので、第3図の抵抗(14),(15に発生する
電圧|E0|及び|ER|は結局|E0|∝|I2|,|ER|∝|I1|となる
ため、電圧|ER|−|E0|の波形はK1|I1|−K2|I2|の波形と
同一になる。Waveform IF is an example of the current waveform flowing at the fault point, and the actual fault current waveform is under the most severe conditions for CT saturation. That is, when the accident occurs, the transient DC component current is 100% superposed on the AC component current peak value. If the AC component current is I FP and the DC component current decay time constant is T, the fault current is Is represented by Waveform I 1 is an example of the CT secondary current at the external fault end. The primary current of this external fault end (outflow end) CT is waveform I F , and the magnitude is the same as the magnitude of the fault current. It is in a condition where it is easily saturated. The shaded part of the waveform is CT2
This is the next current waveform, and the dotted line represents the time when CT is not saturated. The waveform I 2 is the differential current of the error, and if the inflow end CT is unsaturated and only the outflow end (fault end) CT is saturated as the waveform I 1 as a severe condition, the error differential current I 2 As a result, a difference between the waveform I F and the waveform I 1 will occur, so
The waveform is as shown by the diagonal lines. At this time, the operation input I D of the waveform I 2 of FIG. 4 is applied as the input of the ratio differential relay (12) of FIG. 3, and the suppression input | E R | is the waveform | I 1 | Since it is applied, the voltages | E 0 | and | E R | generated at the resistors (14) and (15) in Fig. 3 are eventually | E 0 | ∝ | I 2 |, | E R | ∝ | I 1 | Therefore, the waveform of the voltage | E R | − | E 0 | becomes the same as the waveform of K 1 | I 1 | −K 2 | I 2 |.
なお、第2要素(16)は|ER|−|E0|≧KRの時のみスイ
ツチングするようになつており、|E0|>|ER|(内部事故
時)では不動作となる。The second element (16) is designed to switch only when | E R | − | E 0 | ≧ K R and does not operate when | E 0 |> | E R | (in an internal accident). Become.
この|ER|−|E0|=K1|I1|−K2|I2|の波形は第4図に示
す如く、CTが飽和して差動電流I2が発生しだすと消滅す
るが、CT飽和に達するまでは電流I1に比例して出力が発
生する。The waveform of | E R | − | E 0 | = K 1 | I 1 | −K 2 | I 2 | disappears when CT is saturated and a differential current I 2 is generated, as shown in FIG. However, until CT saturation is reached, an output is generated in proportion to the current I 1 .
第2要素(16)の入力はK1|I1|−K2|I2|であるため、
第2要素(16)の出力信号(21)は第4図に示す如く第
1波の時間t1及び第2波の時間t2+t3において、K1|I1|
−K2|I2|の大きさが規定値以上に達した範囲においてス
イツチングして、出力パルスを発生し、これを信号引延
し回路(17)でT1時間信号を引延すためNOT回路(18)
の信号(22)は第4図の如く連続信号となる。この引延
し時間T1は直流分電流の減衰時間Tが長く、第2波にお
いて電流I1のt2+t3が短かく、K1|I1|−K2|I2|の大きさ
が小さいため第3図の信号(21)の第2パルスが発生し
ない場合は、時間T1を長くして第3波、又は第4波によ
るパルスまで引延せばよい。The input of the second element (16) is K 1 | I 1 | −K 2 | I 2 |
The output signal (21) of the second element (16) is K 1 | I 1 | at the time t 1 of the first wave and the time t 2 + t 3 of the second wave as shown in FIG.
Switching is performed within the range in which the magnitude of −K 2 | I 2 | reaches or exceeds the specified value, an output pulse is generated, and the signal is extended by the signal extension circuit (17) for T 1 time. Circuit (18)
The signal (22) is a continuous signal as shown in FIG. The extension time T 1 has a long DC component current decay time T and a short t 2 + t 3 of the current I 1 in the second wave, so that K 1 | I 1 | −K 2 | I 2 | If the second pulse is not generated because a small third diagram of a signal (21), third wave by increasing the time T 1, or may be allowed引延according to pulse fourth wave.
以上のようにCTの残留磁束によりCT2次電流が第1波
で著しく飽和し、又直流分電流により第2波以降も引続
き飽和が大きく生じても、第2要素の検出値及び信号引
延し回路(17)の信号引延し時間T1を適宜設定すること
により対策は充分可能となる。As described above, even if the CT secondary current is significantly saturated in the first wave due to the residual magnetic flux of the CT, and the saturation continues to occur after the second wave due to the DC component current, the detected value and signal of the second element will be delayed. By properly setting the signal delay time T 1 of the circuit (17), sufficient countermeasures can be taken.
なお、第4図は外部事故時における波形であるが、内
部事故時にCTが著しく飽和した場合でも差動電流が事故
発生と同時に生じ、かつ差動電流が各電源端CTの2次電
流和であるため、必ず各端CT2次電流よりは大きくなる
ため|E0|>|ER|となり第2要素(16)が検出する事はあ
り得ない。Note that Fig. 4 shows the waveform at the time of an external accident. Even if the CT is significantly saturated at the time of an internal accident, a differential current is generated at the same time as the accident occurs, and the differential current is the sum of the secondary currents at each power source CT. Since it is always larger than the CT secondary current at each end, it becomes | E 0 |> | E R | and the second element (16) cannot detect it.
従来の比率差動継電器は以上のように構成されている
ので、外部事故時のCT飽和対策性能を向上させるために
は、第2要素(16)の検出レベルを高感度とし、信号引
延し回路(17)の引延し時間T1を長くする必要がある
が、常時の負荷電流が第2要素(16)の検出レベル以上
ある場合、内部事故発生後上記時間T1分動作不能とな
り、動作時間が遅延する問題点があつた。Since the conventional ratio differential relay is configured as above, in order to improve the CT saturation countermeasure performance in the event of an external accident, the detection level of the second element (16) should be set to high sensitivity and signal extension should be performed. It is necessary to lengthen the delay time T 1 of the circuit (17), but if the constant load current is at or above the detection level of the second element (16), it will become inoperable for the time T 1 minutes after the occurrence of an internal accident, There was a problem that the operation time was delayed.
この発明は上記のような問題点を解消するためになさ
れたもので、常時負荷電流の影響で動作遅延を生じない
CT飽和対策を施すことを目的とする。The present invention has been made to solve the above problems, and does not always cause an operation delay due to the influence of the load current.
The purpose is to take measures against CT saturation.
第2の演算Max|Int|−ηp・Max{|IDt|,Kp|IDt−α
|}>0と、第3の演算Max|Int|>Kと第4の演算|Max
|Int|−Max|Int−180゜||>KTと、第5の演算|IDt|>K1
を行い、上記第4の演算又は第5の演算出力のうち少な
くとも第4の演算出力を所定時間引延してこれを起動信
号とし、第2の演算出力と第3の演算出力と前記起動信
号の内、少なくとも第2の演算出力と前記起動信号とを
含む各出力の論理積が出力された時、この出力を第2の
信号延引手段によって所定時間引延し、前記論理積の出
力により最終動作信号をロックする。Second operation Max | Int | −ηp · Max {| IDt |, Kp | IDt−α
|}> 0, the third operation Max | Int |> K, and the fourth operation | Max
| Int | −Max | Int−180 ° ||> KT and the fifth operation | IDt |> K1
And at least the fourth calculation output of the fourth calculation output or the fifth calculation output is delayed for a predetermined time and used as a start signal, and the second calculation output, the third calculation output, and the start signal are output. Among these, when the logical product of each output including at least the second operation output and the activation signal is output, this output is delayed by the second signal extending means for a predetermined time, and the output is finalized by the output of the logical product. Lock the motion signal.
この発明における第4の演算は電流の変化幅を検出す
るものであり、第5の演算は差動量を検出するものであ
るため、常時負荷電流では応動しない特徴がある。した
がつて、第2の演算及び第3の演算出力が常時負荷電流
で出力していても、第4又は第5の演算出力と論理積と
した出力は常時出力されることはなく、内部事故発生時
に所定時間動作ロツクされる心配がなくなる。The fourth calculation in the present invention is to detect the change width of the current, and the fifth calculation is to detect the differential amount. Therefore, there is a feature that the load current does not always respond. Therefore, even if the second calculation output and the third calculation output are always output with the load current, the output that is the logical product of the fourth calculation output and the fifth calculation output is not always output, and an internal accident occurs. When it occurs, there is no need to worry about it being locked for a predetermined time.
以上の理由から第3の演算の定数Kは負荷電流に関係
なく充分高感度とすることができ、外部事故時のCT飽和
対策として性能を向上させることが可能となる。For the above reason, the constant K of the third calculation can be set to have sufficiently high sensitivity regardless of the load current, and the performance can be improved as a CT saturation countermeasure in the event of an external accident.
以下、この発明の一実施例を第1図及び第2図につい
て説明する。第2図はデジタルリレーを適用して従来の
比率差動継電器の性能に加えて本発明の目的を達成する
ものであり、図において、(4−1)〜(4−n)はCT
(2−1)〜(2−n)の2次電流を受け図示していな
い電流/電圧変換回路を介して、電流に比例した適当な
電圧に変換する入力トランス、(5)はデジタルリレー
で、フイルター(6),サンプルホールド器(7),マ
ルチプレクサ(8),アナログ/デジタル変換器
(9),メモリー(10),マイクロプロセツサ(11)等
から成る。An embodiment of the present invention will be described below with reference to FIGS. FIG. 2 shows the purpose of the present invention in addition to the performance of a conventional ratio differential relay by applying a digital relay. In the figure, (4-1) to (4-n) are CTs.
An input transformer that receives the secondary currents (2-1) to (2-n) and converts it into an appropriate voltage proportional to the current through a current / voltage conversion circuit (not shown), and (5) is a digital relay. , A filter (6), a sample and hold device (7), a multiplexer (8), an analog / digital converter (9), a memory (10), a microprocessor (11) and the like.
入力トランス(4−1)〜(4−n)の2次出力は各
々フイルター(6)を介しサンプルホールド器(7)で
同一時刻、一定間隔のアナログ量瞬時値をサンプリング
する。マルチプレクサ(8)は、サンプルホールド器
(7)の出力を順次切替え、アナログ/デジタル変換器
(9)に導入し、アナログ/デジタル変換器(9)でア
ナログ量瞬時値に比例したデジタルデータに変換の上、
メモリー(10)に一時記憶させる。なお、メモリー(1
0)には演算が必要なプログラムも永久記憶されてお
り、マイクロプロセツサ(11)により時系列にデジタル
処理できるようになつている。Secondary outputs of the input transformers (4-1) to (4-n) are sampled by the sample-hold device (7) via the filter (6) at the same time and at constant intervals of analog values. The multiplexer (8) sequentially switches the output of the sample and hold device (7), introduces it into the analog / digital converter (9), and converts it into digital data proportional to the analog value instantaneous value by the analog / digital converter (9). upon,
Temporarily store in memory (10). The memory (1
Programs that require computation are also permanently stored in (0), and can be digitally processed in time series by the microprocessor (11).
以上の構成から成るデジタル形比率差動継電器におい
て演算原理を第1図に示す。FIG. 1 shows the operation principle of the digital type ratio differential relay having the above configuration.
第1図において、電流データIntは第2図のCT(2−
1)〜(2−n)の2次電流I1〜Inの時間tにおける瞬
時値デジタルデータを示しており、n=1〜nとする。
(100)は第1の演算手段、(101)(102)は第2及び
第3の演算手段で、第3図に示す従来の|ER|−|E0|>KR
を判定する第2要素(16)に相当する。(103)は第4
の演算ブロツク、(104)は第5の演算ブツアクで、第
3図の第1要素(13)に相当している。In FIG. 1, the current data Int is CT (2-
1) shows the instantaneous value digital data at time t of the secondary current I 1 ~I n of ~ (2-n), and n = 1 to n.
(100) is the first computing means, (101) and (102) are the second and third computing means, and the conventional | E R | − | E 0 |> K R shown in FIG.
This corresponds to the second element (16) for determining. (103) is the fourth
The calculation block (104) is a fifth calculation block, which corresponds to the first element (13) in FIG.
第2の演算手段(101)は比率差動演算であり、電流
データMax|Int|は前記の時間tにおける瞬時値電流デー
タI1t〜Intの絶対値の内、最大値を演算で導出したもの
であり、抑制量に相当する。電流データ|IDt|は時間t
における瞬時値電流データI1t〜Intの和 の絶対値を演算で導出したものであり、差動量に相当す
る。電流データ|IDt−α|は時間t−αにおける瞬時値
電流データI1t−α〜Int−αの和 の絶対値を演算で導出したものであり、位相特性改善の
為の補償用差動量であるが、本発明には直接関係しない
ため詳細説明は省略する。Second calculating means 101 is the ratio differential operation, current data Max | I nt | of the absolute value of the instantaneous value current data at the time t is I 1t ~I nt, deriving the maximum value in the calculation The amount of suppression is equivalent to the suppression amount. Current data | I Dt | is time t
Sum of instantaneous current data I 1t to Int at Is derived by calculation and corresponds to the differential amount. The current data | I Dt-α | is the sum of the instantaneous value current data I 1t-α to I nt-α at time t-α. Although it is an absolute value derived by calculation and is a compensation differential amount for improving the phase characteristic, detailed description thereof is omitted because it is not directly related to the present invention.
演算式Max|Int|−ηp・Max{|IDt|,Kp|IDt−α|}
>0 ……(1)式 は抑制量Max|Int|と差動量|IDt|又はKp|IDt−α|(但
し、Kpは定数)の内、大きい値との大きさ比較をしてい
るもので定数ηp>1としておけば、内部事故時は|IDt
|≧Max|Int|のため(1)式演算結果は<0となり出力
しない。Formula Max | I nt | −ηp · Max {| I Dt |, Kp | I Dt−α |}
> 0 …… (1) is compared with the maximum value of the suppression amount Max | I nt | and the differential amount | I Dt | or Kp | I Dt−α | (where Kp is a constant). If a constant ηp> 1 is set in the case of an internal accident, | I Dt
Since | ≧ Max | Int |, the operation result of equation (1) becomes <0 and is not output.
一方、外部事故時はCT不飽和期間中|IDt|≒0である
ためMax|Int|>ηp・Max{|IDt|,Kp|IDt−α|}とな
り(1)式演算結果は>0であり出力することになる。On the other hand, at the time of an external accident, during the CT unsaturated period, | I Dt | ≈ 0, so Max | I nt |> ηp ・ Max {| I Dt |, Kp | I Dt −α |} Is> 0 and will be output.
第3の演算手段(102)は抑制量Max|Int|のレベル検
出であり、前記(1)式出力とANDにすることにより従
来の|ER|−|E0|>KR判定と同等になる。The third calculating means (102) detects the level of the suppression amount Max | Int |, and by performing AND with the output of the equation (1), the conventional | E R | − | E 0 |> K R determination is made. Will be equivalent.
第4の演算手段(103)は抑制量Max|Int|の変化を検
出するもので、検出方法は例えば|Max|Int|−Max|I
nt−π||>KT(但し、KTは定数)、Max|Int−π|はMax
|Int|より180゜前の抑制量とすれば良い。The fourth calculation means (103) detects a change in the suppression amount Max | I nt |, and the detection method is, for example, | Max | I nt | −Max | I
nt−π ||> K T (where K T is a constant), Max | I nt−π | is Max
The amount of suppression 180 degrees before | Int |
第5の演算手段(104)は差動量|IDt|のレベルを検出
するものであり、K1は定数である。The fifth calculation means (104) detects the level of the differential amount | I Dt |, and K 1 is a constant.
演算要素(110)は差動量IDの振幅値を検出するもの
であり、検出方法は、例えば(IDt)2+(IDt−90゜)
2>K0(但しK0は定数)、IDt−90゜はIDtより90゜前の
差動量とした周知のベクトル演算形振幅値導出法でもよ
く、他の振幅値導出方法を適用しても良い。The calculation element (110) detects the amplitude value of the differential amount I D , and the detection method is, for example, (I Dt ) 2 + (I Dt −90 °).
2 > K 0 (where K 0 is a constant), and I Dt −90 ° may be a known vector operation type amplitude value derivation method in which the differential amount is 90 ° before I Dt , and other amplitude value derivation methods are applied. You may.
(105)は論理和(OR)要素、(106)は論理積(AN
D)要素、(107)は第1の信号延引手段、(108)(10
9)は複数回照合タイマーである。(17)は第2の信号
延引手段、(18)はNOT回路、(19)はAND回路であり、
これら(17),(18),(19)のものは従来の第3図の
ものと同一相当部分である。(105) is a logical sum (OR) element, and (106) is a logical product (AN
D) element, (107) is first signal extending means, (108) (10
9) is a multiple match timer. (17) is a second signal extending means, (18) is a NOT circuit, (19) is an AND circuit,
These (17), (18) and (19) are the same parts as those of the conventional one shown in FIG.
次に、前記の従来実施例での欠点であつた負荷電流の
影響による動作時間遅れに対する本発明の対策原理につ
いて説明する。CT飽和対策を強化するためには従来実施
例の演算|ER|−|EO|>KRにおける定数KRを小さくするこ
とと同様に第1図の第3図の演算手段(102)での演算M
ax|Int|>Kの定数Kを小さくする必要がある。この定
数Kを常時負荷電流以下とすれば、当然第3の演算手段
(102)の出力は常時出力されており、又、第2の演算
手段(101)の出力も常時差動量|IDt|又はIDt−α|が
零のため出力されている。しかし、第4及び第5の演算
手段(103),(104)を追加し、論理積(AND)要素(1
06)で論理積をとれば常時負荷電流が大きくても第4及
び第5の演算手段(103),(104)は常時動作出力を出
すことはないため、論理積(AND)要素(106)の出力は
常時出力されないことになる。一方、母線の内部又は外
部事故の発生時は、電流の大きさが変化するため、変化
幅を検出する第4の演算手段(103)又は差動量を検出
する第5の演算手段(104)が動作し、内・外部判定要
素である第2の演算手段(101)の出力条件ゲートに相
当する論理積(AND)要素(106)の動作条件が成立す
る。なお、第4及び第5の演算手段(103)(104)を論
理的要素(105)で合成している目的は事故発生直後一
定時間は負荷電流と事故電流の大きさ差分を検出する変
化幅検出手段(第4の演算手段)(103)が確実に動作
するが、一等時間以上(変化幅検出を前記例の通り|Max
|Int|−Max|Int−π| |>KTとした場合は1/2サイクル以
上)経過すると事故電流の変化が無くなるケースも考え
られるために設けたものであるが、信号引延手段(例え
ばタイマー)(107)の時間を充分長くするならば、必
ずしも必要ではない。Next, a description will be given of the principle of the countermeasure of the present invention against the operation time delay due to the influence of the load current, which is a drawback of the above-mentioned conventional embodiment. In order to strengthen the countermeasure against CT saturation, the calculation means (102) in FIG. 3 of FIG. 1 is used in the same manner as the constant K R in the calculation | E R | − | E O |> K R of the conventional embodiment is made small. Operation M
It is necessary to reduce the constant K of ax | Int |> K. If the constant K is always less than or equal to the load current, the output of the third calculation means (102) is always output, and the output of the second calculation means (101) is always the differential amount | I Dt. | Or I Dt−α | is output because it is zero. However, the fourth and fifth arithmetic means (103) and (104) are added, and the logical product (AND) element (1
If the logical product is taken in 06), the fourth and fifth arithmetic means (103) and (104) do not always output the operation even if the load current is always large, so that the logical product (AND) element (106) The output of is not always output. On the other hand, when an internal or external accident occurs on the bus bar, the magnitude of the current changes, so the fourth calculating means (103) for detecting the change width or the fifth calculating means (104) for detecting the differential amount. Operates, and the operation condition of the logical product (AND) element (106) corresponding to the output condition gate of the second arithmetic means (101), which is an internal / external determination element, is satisfied. The purpose of combining the fourth and fifth calculating means (103) and (104) with the logical element (105) is the change width for detecting the difference in magnitude between the load current and the fault current for a certain period immediately after the occurrence of the fault. Although the detection means (fourth calculation means) (103) operates reliably, it is equal to or longer than the equal time (the change width is detected as in the above example | Max.
| I nt | −Max | I nt − π | |> K T ) It is provided because it is possible that the change of the fault current may disappear after more than 1/2 cycle). It is not necessary if the time of the means (for example, timer) (107) is sufficiently long.
また、第3の演算手段(102)の定数Kと第4の演算
手段(103)の定数KTを同一値にできる場合は第3の演
算手段(102)を省略してもよい。また、第1図におけ
る各演算手段(100)(101)(103)(104)(110),
各論理要素(105)(106)……等は個別に設けてもよ
く、第2図に示すように共通の単一のCPU(11)で構成
しても良い。Further, if the constant K of the third calculating means (102) and the constant K T of the fourth calculating means (103) can be the same value, the third calculating means (102) may be omitted. Further, each calculation means (100) (101) (103) (104) (110) in FIG.
Each of the logic elements (105) (106), etc. may be provided individually, or may be composed of a single common CPU (11) as shown in FIG.
なお、上記実施例では変化幅検出手段(第4の演算手
段)(103)を各端電流Int絶対値の内、最大値であるMa
x|Int|の変化分検出としているが、各端電流Int絶対値
のスカラー和Σ|Int|の変化分検出としてもよい。つま
り、第1図における第4の演算手段(103)は、演算|Ma
x|Int|−Max|Int−180゜| |>KTに代えて、 (但し、 は時間tにおける各端子電流の瞬時値デジタル量の絶対
値|I1t|〜|Int|のスカラー和、 は同じく時間tより180゜前のスカラー和)を演算してI
nの変化幅を検出するようにしてもよい。In the above embodiment, the change width detection means (fourth calculation means) (103) is set to the maximum value Ma among the absolute values of the end currents Int.
The change amount of x | I nt | is detected, but the change amount of the scalar sum Σ | I nt | of the absolute value of each end current I nt may be detected. That is, the fourth computing means (103) in FIG.
x | I nt | −Max | I nt −180 ° | |> K T (However, Is the absolute sum of the instantaneous digital value of each terminal current at time t | I 1t | ~ | I nt | Is also the scalar sum 180 ° before time t) and I
The change width of n may be detected.
以上のように、この発明によればCT飽和対策用比率要
素(第3及び第4の演算手段)の起動用として、負荷電
流に影響されない電流変化幅検出要素(第4の演算手
段)と差動レベル検出要素(第5の演算手段)とを付加
するように構成したので、負荷電流による動作遅延現象
を生じない高性能のCT飽和対策付比率差動継電器とする
ことができる。As described above, according to the present invention, as a starting element of the CT saturation countermeasure ratio element (third and fourth calculating means), it is different from the current change width detecting element (fourth calculating means) which is not affected by the load current. Since the configuration is such that the dynamic level detecting element (fifth computing means) is added, a high-performance ratio differential relay with CT saturation countermeasure that does not cause an operation delay phenomenon due to load current can be obtained.
第1図はこの発明の一実施例を示すデジタル形比率差動
継電器の演算原理図、第2図は第1図の演算原理を利用
したデジタル形比率差動継電器のシステム構成図、第3
図は従来の比率差動継電器の原理を示す構成図、第4図
は従来及び本発明の原理を説明する波形図である。 図において、(100)は第1の演算手段、(101)は第2
の演算手段、(102)は第3の演算手段、(103)は第4
の演算手段、(104)は第5の演算手段、(107)は第1
の信号延引手段、(17)は第2の信号延引手段である。 なお、各図中、同一符号は同一又は相当部分を示す。FIG. 1 is a diagram showing the operation principle of a digital ratio differential relay according to an embodiment of the present invention, and FIG. 2 is a system configuration diagram of a digital ratio differential relay utilizing the operation principle shown in FIG.
FIG. 4 is a block diagram showing the principle of a conventional ratio differential relay, and FIG. 4 is a waveform diagram explaining the principle of the conventional ratio differential relay and the present invention. In the figure, (100) is the first computing means and (101) is the second
Calculation means, (102) is a third calculation means, and (103) is a fourth calculation means.
Calculation means, (104) is fifth calculation means, and (107) is first calculation means.
The signal extending means (17) is a second signal extending means. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (2)
サンプリングして得られる瞬時値をデジタル量に変換し
所定のプログラムに従って演算するデジタル形比率差動
継電器において、 時間tにおける各端電流の瞬時値デジタル量Int(I1t、
…、Int)を加算して得る差動量IDtと時間tよりα時間
前の瞬時値デジタル差動量IDt−αと時間tにおける各
端電流の瞬時値デジタル量の絶対値の内、最大値を導出
して得る抑制量Max|Int|と、時間tより180゜前の各端
電流の瞬時値デジタル量の絶対値の内、最大値を導出し
て得る制御量Max|Int−180゜|とを第1の演算手段によ
り得、第2の演算手段によって第2の演算Max|Int|−η
p・Max{|IDt|,Kp|IDt−α|}>0(但し、ηp,Kpは
定数、Max{|IDt|,Kp|IDt−α|は|IDt|又はKp|IDt−α
|の内、大きい値を導出)を、第3の演算手段により第
3の演算Max|Int|>K(但し、Kは定数)を、第4の演
算手段により第4の演算|Max|Int|−Max|Int−180゜||
>KTを、第5の演算手段により第5の演算|IDt|>K1
(但し、K1は定数)をそれぞれ行い、 上記第4の演算又は第5の演算出力のうち少なくとも第
4の演算出力を第1の信号延引手段により所定時間引延
してこれを起動信号とし、第2の演算出力と第3の演算
出力と前記起動信号の内、少なくとも第2の演算出力と
前記起動信号とを含む各出力の論理積が出力された時、
この出力を第2の信号延引手段によって所定時間引延
し、前記論理積の出力により最終動作信号をロックする
ことを特徴とするデジタル形比率差動継電器。1. A digital type ratio differential relay which converts an instantaneous value obtained by synchronously sampling the current of each terminal of a power system at a constant cycle into a digital value and calculates the digital value according to a predetermined program. Instantaneous value digital amount Int (I1t,
, Int) and the differential value IDt obtained by adding the instantaneous value digital differential value αt before time t and the absolute value of the instantaneous value digital value of each end current at time t. Control amount Max | Int−180 ° | obtained by deriving the maximum value of the suppression amount Max | Int | obtained by deriving the absolute value and the absolute value of the instantaneous value digital value of each end current 180 ° before time t Are obtained by the first calculation means, and the second calculation Max | Int | −η is obtained by the second calculation means.
p · Max {| IDt |, Kp | IDt−α |}> 0 (where ηp and Kp are constants, and Max {| IDt |, Kp | IDt−α | is | IDt | or Kp | IDt−α
│ out of a larger value), the third calculation means calculates the third calculation Max | Int |> K (where K is a constant), and the fourth calculation means calculates the fourth calculation | Max | Int. | −Max | Int−180 ° ||
> KT, and the fifth operation | IDt |> K1 by the fifth operation means.
(However, K1 is a constant), and at least the fourth operation output of the fourth operation or the fifth operation output is extended by the first signal extension means for a predetermined time, and this is used as a start signal, When a logical product of the outputs including at least the second calculation output and the start signal among the second calculation output, the third calculation output, and the start signal is output,
A digital ratio differential relay characterized in that this output is extended for a predetermined time by a second signal extending means, and the final operation signal is locked by the output of the logical product.
180゜||>KTに代えて は時間tにおける各端子電流の瞬時値デジタル量の絶対
値|I1t|〜|Int|のスカラー和、 は同じく時間tより180゜前のスカラー和)の演算をす
ることを特徴とする特許請求の範囲第1項記載のデジタ
ル形比率差動継電器。2. The fourth calculation means is | Max | Int | −Max | Int−.
180 ° || Replace KT Is the scalar sum of absolute value | I1t | to | Int | of the instantaneous digital value of each terminal current at time t, Is also a scalar sum 180 ° before the time t), and the digital type ratio differential relay according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62324430A JP2540897B2 (en) | 1987-12-22 | 1987-12-22 | Digital type ratio differential relay |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62324430A JP2540897B2 (en) | 1987-12-22 | 1987-12-22 | Digital type ratio differential relay |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01170317A JPH01170317A (en) | 1989-07-05 |
JP2540897B2 true JP2540897B2 (en) | 1996-10-09 |
Family
ID=18165712
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62324430A Expired - Lifetime JP2540897B2 (en) | 1987-12-22 | 1987-12-22 | Digital type ratio differential relay |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2540897B2 (en) |
-
1987
- 1987-12-22 JP JP62324430A patent/JP2540897B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH01170317A (en) | 1989-07-05 |
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