JP3768441B2

JP3768441B2 - Busbar protection relay

Info

Publication number: JP3768441B2
Application number: JP2001391539A
Authority: JP
Inventors: 重遠尾田
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2001-12-25
Filing date: 2001-12-25
Publication date: 2006-04-19
Anticipated expiration: 2021-12-25
Also published as: JP2003199244A

Description

【０００１】
【発明の属する技術分野】
この発明は、電力系統の母線を保護する母線保護リレ−、特に電流差動リレ−に関するものである。
【０００２】
【従来の技術】
図７は、例えば“系統保護継電方式の標準的な考え方（デジタル編）、平成４年３月、電気事業連合会工務部保護制御担当課長会議”の“３−３母線保護継電方式の特徴解説”に示された従来の電流差動方式における動作原理を示す機能ブロック図、図８は図７の動作の参考図で、ＣＴ流入電流、ＣＴ流出電流、差動誤差電流、差動要素出力、起動要素出力、外部判別要素出力、ＣＴ飽和対策要素出力、リレ−動作出力、サンプリング周期を比較して示す波形図である。図７において、１は母線、２はＣＴ、３はＡｕｘＣＴ（補助ＣＴ）、４は単純差動要素、５は比率差動要素、６は外部判定要素、７は起動要素、８はＡＮＤ回路、９はタイマ−回路、１０はＮＯＴ回路、１１はＡＮＤ回路、１２は差動演算回路、１３は抑制演算回路、１４は差動演算回路、１５はタイマ−回路である。なお、前記単純差動要素４は、前記差動演算回路１２と、前記差動演算回路１４と、前記タイマ−回路１５とで構成されている。１６は比率判定回路、１７はタイマ−回路である。なお、前記比率差動要素５は、前記抑制演算回路１３と、前記比率判定回路１６と、前記タイマ−回路１７とで構成されている。
【０００３】
１８は電流変化判定回路、１９はタイマ−回路、２０は瞬時差動演算回路、２１は瞬時抑制演算回路、２２は外部判定回路である。なお、前記外部判定要素６は、前記瞬時差動演算回路２０と、前記瞬時抑制演算回路２１と、前記外部判定回路２２とで構成されている。また、前記起動要素７は、前記電流変化判定回路１８と、前記タイマ−回路１９とで構成されている。１００は差動要素で、前記単純差動要素４と前記比率差動要素５とで構成されている。２００はＣＴ飽和対策要素で、前記外部判定要素６と、前記起動要素７と、前記ＡＮＤ回路８と、前記タイマ−回路９と、前記ＮＯＴ回路１０とで構成されている。なお、前記差動演算回路１２、前記抑制演算回路１３、前記差動演算回路１４、前記比率判定回路１６、前記電流変化判定回路１８、前記瞬時差動演算回路２０、前記瞬時抑制演算回路２１、及び前記外部判定回路２２の各ブロック内の式は、各々の機能を表す。
【０００４】
母線１に接続される各フィ−ダＣＴ２の電流はＡｕｘＣＴ（補助ＣＴ）３を介してリレ−に入力され、リレ-内の要素としては、大別して、単純差動要素４と比率差動要素５と
で構成される差動要素１００と、外部判定要素７と起動要素６とＡＮＤ回路８とで構成されるＣＴ飽和対策要素２００とで構成される。リレ−の動作出力としては、差動要素１００の出力を、ＣＴ飽和対策要素２００の出力でロックして出力するため、前記単純差動要素４、比率差動要素５と、ＣＴ飽和対策のＮＯＴ回路１０の出力とを入力するＡＮＤ回路１１を出力とする。フィ−ダＴ１〜Ｔｎの各電流ＩＴ１〜ＩＴｎは、フィ−ダＣＴ２、ＡｕｘＣＴ３を介してリレ−に入力され、電流ｉ１，・・・，ｉｎとなる。
【０００５】
差動電流Ｉｄは、ベクトル和の実行値｜ｉ１+・・・+ｉｎ｜を演算する演算回路１２で計算され、抑制電流Ｉｒｅｓは、スカラ−和｜ｉ１｜+・・・+｜ｉｎ｜を演算する演算回路１３で計算される（ここで、｜｜は実行値演算の結果を示す）。単純差動要素４において、差動演算回路１４で、Ｉｄ＞Ｋ１が判定される。比率差動要素５において、比率判定回路１６で、Ｉｄ＞Ｒ１・Ｉｒｅｓ−Ｋ２が判定される。前記差動演算回路１４および比率判定回路１６の各出力にはタイマ−（オンディレイタイマ−）回路１５，１７がある。これらタイマ−１５，１７のｔ１／ｔ２の意味は、ｔ１は動作側ディレイ時間、ｔ２は復帰側ディレイ時間を示す。
【０００６】
一方、ＣＴ飽和対策要素２００の起動要素７は各フィ−ダ−ＣＴ２電流の変化分を検出し、変化分が一定以上で出力するもので、｜Δｉ１｜＞Ｋ３，・・・｜Δｉｎ｜＞Ｋ３のどれかが成立することで判定する回路１８の出力を入力とするタイマ−回路１９を通して出力する。
【０００７】
ＣＴ飽和対策要素２００の外部判別要素６は、入力電流サンプル値（瞬時値）から比率演算または、差動電流の無変化検出をするもので、例えば、｜｜ｉ１+・・・+ｉｎ｜｜＜Ｒ２・（｜｜ｉ１｜｜+・・・+｜｜ｉｎ｜｜）、（ここで｜｜＊＊｜｜は＊の絶対値を示す）で表される演算回路２０，２１，２２で構成される。
【０００８】
このように瞬時値を使用することで，外部故障発生による大電流でＣＴが飽和して差動電流が発生しても、ＣＴ飽和が生じるまでの時間の数サンプリングで検出できる回路としてある。このＣＴ飽和対策回路２００が常時潮流で検出しないように故障発生時のみ検出できるように前記起動要素とＡＮＤ回路８とＡＮＤ
して出力される。その出力後、ＣＴ飽和現象が収まって、差動要素が不要動作しなくなるまでの間の或る一定期間差動をロックする為に復帰側に数サイクルの設定がされているタイマ−回路９がある。
【０００９】
従来技術では、前述のように外部故障が発生してＣＴ飽和が生じるまでの短い時間で外部故障を判定して、一定時間差動要素をロックすることで、例え、外部故障でＣＴが飽和することで差動量が発生しても誤動作の無い母線リレ−を実現している。
【００１０】
次に動作について説明する。フィ−ダＣＴが全く飽和しない場合には、外部故障の場合、差動電流Ｉｄは、ＣＴの誤差の合計やリレ−の誤差に相当する分しか発生せず、差動要素は動作しない。一方、内部故障では、全フィ−ダ−電流のベクトル和Ｉｄとスカラ−和Ｉｒｅｓはほぼ同じ量になるので、差動要素回路４の動作式で表される動作域内になるので動作する。これで、内外部故障が識別される。
【００１１】
従来技術で記載のＣＴ飽和対策を図６について説明する。外部故障発生時、どれかのフィ−ダ回線ＣＴに電流が集中することでその回線ＣＴの飽和が始まると、飽和していない回線と飽和している回線の和で計算される差動誤差電流Ｉｄ（図では簡単化のためフィ−ダ−が２回線で、流入側ＣＴは飽和せず、流出側ＣＴが飽和した場合を示す）は、ＣＴ飽和が始まると急に増加し、その為に差動要素１００が内部判定する。しかし、外部故障発生直後のＣＴ飽和が未だ始まっていない数ｍｓ間のＩｄとして殆ど無視できる期間で検出して外部判別要素が出力し（図では２サンプリング間）、それによりＣＴ飽和対策回路２００が出力する。その出力を引き伸ばして、ＣＴ飽和で差電流が出ている間差動要素１００の出力をロックする方式を採ることで、最終的にリレ−動作出力を阻止している。起動要素７は、常時潮流で外部判定させないために、故障発生時にのみ外部判定要素が出力できるように構成されている。
【００１２】
【発明が解決しようとする課題】
従来の母線保護リレ−は、前述のように構成されているので、外部故障電流で或る回線に電流が集中しその回線のＣＴ飽和がある場合にＣＴ飽和よって発生する差動電流により差動要素が不要出力を出す前に外部検出しその出力をロックする。そのロック時間は差動電流が検出されている期間（例えば，数サイクル）に設定されている。このロック時間を長くするほど外部故障に対して安定した動作が得られるが、その代わり、例えば、外部故障から内部故障へと故障が進展した場合、内部故障に対して直ぐには動作しなくなると言う欠点を持っている。
【００１３】
さらに、現状の起動要素は母線１相故障時において、故障相以外の健全相についても１相故障発生時に健全相電流も変化するため不要検出する可能性がある。このために、例えば、外部１相故障から内部の他相への故障進展があると、初めの外部故障で起動要素が出力して外部判定しているので、他相内部故障への進展時にもロックがされているので、動作が大きく遅れるという欠点がある。
【００１４】
この発明は上記のような課題を解決するためになされたものであり、外部故障時のＣＴ飽和対策をより的確に行えるようにすることを目的とし、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを少なくすることを目的とするものである。
【００１５】
【課題を解決するための手段】
請求項１に記載の発明に係る母線保護リレ−は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、前記差動要素が動作域の異なる複数の比率差動出力を出すと共に、前記ＣＴ飽和対策要素が前記複数の比率差動出力の差動誤差電流不要出力時間に対応した異なるロック時間の複数のロック出力を出し、差動誤差電流不要出力時間が長い比率差動出力に対しては長いロック時間のロック出力によってロックし、差動誤差電流不要出力時間が短い比率差動出力に対しては短いロック時間のロック出力によってロックすることにより、前記誤動作出力を防止するものである。
【００１６】
請求項２に記載の発明に係る母線保護リレ−は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、前記差動要素が動作域の異なる複数の比率差動出力を出すと共に、前記ＣＴ飽和対策要素の出力により差動誤差電流不要出力時間が長い比率差動出力のオンディレイ設定時間を、差動誤差電流不要出力時間が短い比率差動出力のオンディレイ設定時間より長い時間に変えることにより前記誤動作出力を防止するものである。
【００１７】
請求項３に記載の発明に係る母線保護リレ−は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、前記差動要素が動作域の異なる複数の比率差動出力を出すと共に、前記ＣＴ飽和対策要素が前記複数の比率差動出力の差動誤差電流不要出力時間に対応した異なるロック時間の複数のロック出力を出し、差動誤差電流不要出力時間が長い比率差動出力に対しては長いロック時間のロック出力によってロックし差動誤差電流不要出力時間が短い比率差動出力に対しては短いロック時間のロック出力によってロックすることにより前記誤動作出力を防止すると共に、前記ＣＴ飽和対策要素の出力により差動誤差電流不要出力時間が長い比率差動出力のオンディレイ設定時間を差動誤差電流不要出力時間が短い比率差動出力のオンディレイ設定時間より長い時間に変えることにより前記誤動作出力を防止するものである。
【００１８】
請求項４に記載の発明に係る母線保護リレ−は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を前記動作出力を所定時間ロックすることにより防止するＣＴ飽和対策要素を備えた母線保護リレ−において、ＣＴ飽和が大きく差動電流幅が大きい場合のロック時間よりＣＴ飽和が小さく差動電流幅が小さい場合のロック時間を小さく制御するものである。
【００１９】
請求項５に記載の発明に係る母線保護リレ−は、請求項１〜４の何れか一に記載の母線保護リレ−において、不足電圧要素、方向リレ−要素、及び距離リレ−要素の何れかにより母線電圧から故障相を判定しこの判定結果により前記ＣＴ飽和対策要素が故障相についてのみ起動するものである。
【００２０】
【発明の実施の形態】
実施の形態１．
以下、この発明の実施の形態１を図に基づいて説明する。図１はこの発明の実施の形態１による母線保護リレ−の機能ブロック図で、前述の従来の機能ブロック図（図７）と同一符号は、前述の従来の機能ブロック図（図７）と同一もしくは同一目的のものであり、特に同一のものについては説明は割愛する。
【００２１】
図１において、１６１は第２の比率差動要素、１７１は前記第２の比率差動要素１６１の出力に設けられたタイマ−回路、２３は第２のタイマ−で、起動要素７と外部判定要素６とのＡＮＤをとるＡＮＤ回路８の出力を入力する。２４はＡＮＤ回路で、前記比率判定回路１６の出力を前記タイマ−回路１７を介して入力すると共に、前記タイマ−回路９の出力をＮＯＴ回路１０を介して入力する。３４はＡＮＤ回路で、前記第２の比率判定回路１６１の出力を前記タイマ−回路１７１を介して入力すると共に、前記タイマ−回路２３の出力をＮＯＴ回路１０を介して入力する。なお、前記タイマ−回路９の復帰ディレイ設定時間ｔ６は３サイクル程度、前記第２のタイマ−２３の復帰ディレイ設定時間ｔ７は１サイクル程度と、前記タイマ−回路９の復帰ディレイ設定時間ｔ６との関係はｔ６＞ｔ７としてある。
【００２２】
次に動作について説明する。内部故障発生時のリレ−動作高速化のために、比率差動要素５と単純差動要素４の各動作照合時間ｔ１（タイマ−回路１５，１７のオンディレイ設定時間ｔ１）はできる限り短く設定してある。一方、外部故障発生時には、動作照合時間は長く設定することで、安定した動作が得られる。外部故障時にＣＴ飽和が発生すると図６で説明したように差動誤差電流Ｉｄが増減を繰り返す。その様子を図２に示す。
【００２３】
図２に示されているように、第１波（サンプリング第１周期の差動誤差電流）において、第１の比率差動要素１６（動作域はＩｄ＞Ｒ１・Ｉｒｅｓ−Ｋ２）での動作時間（差動誤差電流不要出力時間）は比較的長いが、前記第１の比率差動要素１６より狭い動作領域を持つ第２の比率差動要素１６１（動作域はＩｄ＞Ｒ１１・Ｉｒｅｓ−Ｋ２１）での動作時間（差動誤差電流不要出力時間）は短いことが解かった。即ち、前記第１の比率差動要素１６の不要動作時間をロックする時間を長くすることは必要である（例えば３サイクル）が、前記第２の比率差動要素１６１に対するロック時間は短くできる（例えば１サイクル）ことが解かる。
【００２４】
これを利用して、比率差動要素の動作領域に合わせて、ロック時間を最適に設定することができ、外部故障から内部への故障進展が発生しても、内部故障は本質的にＩｄ＝Ｉｒｅｓ（外部故障が除去された場合）になるので、第２の比率差動要素１６１の短いロック時間解除後に動作が可能となる。
【００２５】
前述の実施形態１は、換言すれば、母線１に接続される全てのフィ−ダ−線のＣＴ電流を入力してフィ−ダ−電流をベクトル加算した差動電流Ｉｄとスカラ−和した抑制電流Ｉｒｅｓを演算して比率特性を持たせ母線上の内部故障を検出する母線保護リレ−において、第２の比率差動要素１６１と第２の外部判定出力要素２３を設け、外部判定時に比率差動領域に応じたロック時間とすることができるＣＴ飽和対策要素２００を備えたもので、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを少なくできるものである。
【００２６】
前述の実施形態１は、更に概念的に換言すれば、母線１に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素１００及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素２００を備えた母線保護リレ−において、前記差動要素１００が動作域の異なる複数の比率差動出力（比率判定回路１６，１６１の出力）を出すと共に、前記ＣＴ飽和対策要素が前記複数の比率差動出力に対応して複数のロック出力（タイマ−９，２３の出力）を出し、前記複数の比率差動出力と前記複数のロック出力とにより前記誤動作出力を防止するもので、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを少なくできるものである。
【００２７】
具体的には、前述のように、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、前記差動要素が動作域の異なる複数の比率差動出力を出すと共に、前記ＣＴ飽和対策要素が前記複数の比率差動出力の差動誤差電流不要出力時間に対応した異なるロック時間の複数のロック出力を出し、差動誤差電流不要出力時間が長い比率差動出力に対しては長いロック時間のロック出力によってロックし、差動誤差電流不要出力時間が短い比率差動出力に対しては短いロック時間のロック出力によってロックすることにより、前記誤動作出力を防止するもので、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを少なくできるものである。
【００２８】
実施の形態２．
前述の実施形態１では、比率差動要素５をロックする方式を例示したが、図３に示すように、第１の比率差動要素１６および第２の比率差動要素１６１の夫々の照合時間（即ち動作確認時間）を、ＣＴ飽和対策要素２００の出力がある場合、制御する、即ち、第１の比率差動要素１６の出力端のタイマ−回路１７のオンディレイ設定時間ｔ１をｔ８（例えば４０ｍｓ）に制御し、差動領域が第１の比率差動要素１６より狭い第２の比率差動要素１６１の出力端のタイマ−回路１７１のオンディレイ設定時間ｔ１をｔ９（例えば１５ｍｓ）に制御することで、前述の実施形態１におけるロックの場合と同様に、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを少なくできるものである。
【００２９】
尚、図３において、２５は前記タイマ−回路１７のオンディレイ設定時間ｔ１をｔ８（例えば４０ｍｓ）に制御するタイマ−制御回路で、ＣＴ飽和対策要素２００のタイマ−回路９の出力により制御動作を行う。２６は前記タイマ−回路１７１のオンディレイ設定時間ｔ１をｔ９（例えば１５ｍｓ）に制御するタイマ−制御回路で、ＣＴ飽和対策要素２００のタイマ−回路２３の出力により制御動作を行う。この構成の場合、タイマ−回路２３を削除し、タイマ−回路９の出力でタイマ−制御回路２５，２６を両方とも制御することも可能である。
【００３０】
前述の実施形態２は、換言すれば、母線１に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素１００及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素２００を備えた母線保護リレ−において、前記差動要素１００が動作域の異なる複数の比率差動出力（比率判定回路１６，１６１の出力）を出すと共に、前記ＣＴ飽和対策要素２００が前記複数の比率差動出力に対応して複数の出力（タイマ−制御回路２５，２６の出力）を出し、前記ＣＴ飽和対策要素の前記複数の比率差動出力に対応した複数の出力により前記複数の比率差動出力の出る時間を変えることにより前記誤動作出力を防止するもので、前述の実施形態１におけるロックの場合と同様に、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを少なくできるものである。
【００３１】
具体的には、前述のように、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、前記差動要素が動作域の異なる複数の比率差動出力を出すと共に、前記ＣＴ飽和対策要素の出力により差動誤差電流不要出力時間が長い比率差動出力のオンディレイ設定時間を、差動誤差電流不要出力時間が短い比率差動出力のオンディレイ設定時間より長い時間に変えることにより前記誤動作出力を防止するもので、前述の実施形態１におけるロックの場合と同様に、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを少なくできるものである。
【００３２】
実施の形態３．
図４は実施形態３を示す母線保護リレ−の機能ブロック図で、前述の実施形態１と実施形態２の機能を併せ持つもので、回路構成も、前述の実施形態１の回路に前述の実施形態２の回路を加えたもので、前述の実施形態１よりも、また、前述の実施形態２よりも的確な動作をし、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを的確に少なくできるものである。
【００３３】
具体的には、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、前記差動要素が動作域の異なる複数の比率差動出力を出すと共に、前記ＣＴ飽和対策要素が前記複数の比率差動出力の差動誤差電流不要出力時間に対応した異なるロック時間の複数のロック出力を出し、差動誤差電流不要出力時間が長い比率差動出力に対しては長いロック時間のロック出力によってロックし差動誤差電流不要出力時間が短い比率差動出力に対しては短いロック時間のロック出力によってロックすることにより前記誤動作出力を防止すると共に、前記ＣＴ飽和対策要素の出力により差動誤差電流不要出力時間が長い比率差動出力のオンディレイ設定時間を差動誤差電流不要出力時間が短い比率差動出力のオンディレイ設定時間より長い時間に変えることにより前記誤動作出力を防止するもので、前述の実施形態１よりも、また、前述の実施形態２よりも的確な動作をし、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを的確に少なくできるものである。
【００３４】
実施の形態４．
前述の実施形態１では、外部判定要素６の出力を受ける一定時間ロックの回路を２回路設ける方式を例示したが、この実施形態４は、図５に示すように、瞬時差動電流が或る値以上存在する時間（時間幅）を計測する時間幅計測回路２７と、この時間幅計測回路２７で得られた時間幅に応じてロック時間ｔ６をｔ１０に制御するタイマ−制御回路２８を設け、外部故障時の作動誤差電流の発生幅に応じてロックする時間を制御するものである。
【００３５】
ＣＴ飽和が大きく、第２波までＣＴ飽和の影響が継続する場合、ロック時間を２もしくは３サイクル以上に設定する必要があるが、ＣＴ飽和が比較的小さい場合には、第１波と第２波との間には再び外部判定できる機会が生じる。この場合は、ロック時間は１サイクルでよいことになる。即ち、瞬時差動誤差電流の絶対値が或る一定値（例えばＫ３）以上存在する時間幅Ｔを計測してその時間に応じたロック時間に変更することで、最適なロック時間にすることができ、必要以上に長くロックしないため、外部から内部への故障進展での動作遅れを最小限にすることができる。簡単な応用としては、瞬時差動電流の存在時間Ｔが或る時間（例えば０．５サイクル）以上継続している場合には、ロック時間を数サイクルにセットするが、存在時間Ｔがそれより短い場合には、ロック時間を例えば１サイクルにする制御を行うことも実現できる。
【００３６】
換言すれば、この発明の実施の形態４は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を前記動作出力を所定時間ロックすることにより防止するＣＴ飽和対策要素を備えた母線保護リレ−において、ＣＴ飽和が大きく差動電流幅が大きい場合のロック時間よりＣＴ飽和が小さく差動電流幅が小さい場合のロック時間を小さく制御するものであり、これにより、前述のように、最適なロック時間にすることができ、必要以上に長くロックしないため、外部から内部への故障進展での動作遅れを最小限にすることができるものである。
【００３７】
実施の形態５．
前述の実施形態１〜４では、外部故障と同相の内部故障への進展故障での動作時間遅れ対策を例示したが、この実施形態５では、図６に示すように、外部から内部への他相への故障進展での動作遅れ対策を例示するものである。図６において、２９は母線電圧をリレ−に導くためのＰＴ（電圧変換器）、３０はＰＴ出力電圧をリレ−内部回路電圧に変換する電圧変換器、３１は不足電圧検出要素で、電圧比較回路３２とタイマ−回路３３とで構成されている。不足電圧検出要素３１の出力はＡＮＤ回路８へ入力している。
【００３８】
従来の起動要素７は電流変化によるものであるため、例えば、外部１相故障発生時にも故障相以外の健全相電流も変化するため、不要検出する可能性があったが、母線電圧については、健全相電圧の低下は比較的少ないために不足電圧要素の検出設定として故障相判定が可能な設定値にすることが可能である。この不足電圧検出と組み合わせることにより、故障発生相についてのみ起動できる回路が得られ、外部１相から内部他相への故障進展の場合でも動作遅れのない回路が得られる。なお、不足電圧要素に代えて、リレ−の方向要素や距離要素としても不足電圧要素を使った場合と同様な効果を奏する。
【００３９】
換言すれば、この発明の実施の形態５は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、不足電圧要素、方向リレ−要素、及び距離リレ−要素の何れかにより母線電圧から故障相を判定しこの判定結果により前記ＣＴ飽和対策要素が故障相についてのみ起動するものであり、ＣＴ飽和対策要素のみであれば健全相までロックすることにより外部故障とは異相の内部故障へ進展した場合に当該ロックにより内部故障に対する動作が遅れる不都合を解消できる。
【００４０】
【発明の効果】
請求項１に記載の母線保護リレ−の発明は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、前記差動要素が動作域の異なる複数の比率差動出力を出すと共に、前記ＣＴ飽和対策要素が前記複数の比率差動出力の差動誤差電流不要出力時間に対応した異なるロック時間の複数のロック出力を出し、差動誤差電流不要出力時間が長い比率差動出力に対しては長いロック時間のロック出力によってロックし、差動誤差電流不要出力時間が短い比率差動出力に対しては短いロック時間のロック出力によってロックすることにより、前記誤動作出力を防止するようにしたので、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを少なくできる効果がある。
【００４１】
請求項２に記載の母線保護リレ−の発明は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、前記差動要素が動作域の異なる複数の比率差動出力を出すと共に、前記ＣＴ飽和対策要素の出力により差動誤差電流不要出力時間が長い比率差動出力のオンディレイ設定時間を、差動誤差電流不要出力時間が短い比率差動出力のオンディレイ設定時間より長い時間に変えることにより前記誤動作出力を防止するようにしたので、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを少なくできる効果がある。
【００４２】
請求項３に記載の母線保護リレ−の発明は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を防止するＣＴ飽和対策要素を備えた母線保護リレ−において、前記差動要素が動作域の異なる複数の比率差動出力を出すと共に、前記ＣＴ飽和対策要素が前記複数の比率差動出力の差動誤差電流不要出力時間に対応した異なるロック時間の複数のロック出力を出し、差動誤差電流不要出力時間が長い比率差動出力に対しては長いロック時間のロック出力によってロックし差動誤差電流不要出力時間が短い比率差動出力に対しては短いロック時間のロック出力によってロックすることにより前記誤動作出力を防止すると共に、前記ＣＴ飽和対策要素の出力により差動誤差電流不要出力時間が長い比率差動出力のオンディレイ設定時間を差動誤差電流不要出力時間が短い比率差動出力のオンディレイ設定時間より長い時間に変えることにより前記誤動作出力を防止するようにしたので、外部故障時のＣＴ飽和対策をより的確に行え、また、外部故障から内部故障へ進展した場合のＣＴ飽和対策に依る動作遅れを的確に少なくできる効果がある。
【００４３】
請求項４に記載の発明に係る母線保護リレ−は、母線に接続される各フィ−ダ線の電流をＣＴを介して入力する差動要素及び外部故障時のＣＴ飽和による前記差動要素の動作による誤動作出力を前記動作出力を所定時間ロックすることにより防止するＣＴ飽和対策要素を備えた母線保護リレ−において、ＣＴ飽和が大きく差動電流幅が大きい場合のロック時間よりＣＴ飽和が小さく差動電流幅が小さい場合のロック時間を小さく制御するようにしたので、外部故障時のＣＴ飽和対策をより的確に行え、また、外部から内部への故障進展での動作遅れを最小限にすることができる効果がある。
【００４４】
請求項５に記載の発明に係る母線保護リレ−は、請求項１〜４の何れか一に記載の母線保護リレ−において、不足電圧要素、方向リレ−要素、及び距離リレ−要素の何れかにより母線電圧から故障相を判定しこの判定結果により前記ＣＴ飽和対策要素が故障相についてのみ起動するようにしたので、外部故障時のＣＴ飽和対策をより的確に行え、外部１相から内部他相への故障進展の場合でも動作遅れを解消できる効果がある。
【００４５】
【図面の簡単な説明】
【図１】この発明の実施の形態１を示す機能ブロック図。
【図２】この発明の実施の形態１の動作説明図。
【図３】この発明の実施の形態２を示す機能ブロック図。
【図４】この発明の実施の形態３を示す機能ブロック図。
【図５】この発明の実施の形態４を示す機能ブロック図。
【図６】この発明の実施の形態５を示す機能ブロック図。
【図７】従来の母線保護リレ−の機能ブロック図。
【図８】従来の母線保護リレ−の動作波形図。
【００４６】
【符号の説明】
１母線、２ＣＴ
４単純差動要素、５比率差動要素、
６外部判定要素、７起動要素、
１２差動演算回路、１３抑制演算回路、
１４差動演算回路、１６比率判定回路、
２５タイマ−制御回路、２６第２のタイマ−制御回路、
２７時間幅計測回路、２８タイマ−制御回路、
３１不足電圧要素、３２電圧判定回路、
１６１第２の比率判定回路、１００：差動要素、
２００ＣＴ飽和対策要素。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bus protection relay for protecting a bus of an electric power system, and more particularly to a current differential relay.
[0002]
[Prior art]
Fig. 7 is an example of “3-3 Bus Protection Relay System” in “Standard Concept of Grid Protection Relay System (Digital Edition), March 1992, Manager Meeting for Protection Control Section, Engineering Division, Electric Power Industry Federation” 8 is a functional block diagram showing the principle of operation in the conventional current differential method shown in “Characteristics”, and FIG. 8 is a reference diagram of the operation in FIG. 7. CT inflow current, CT outflow current, differential error current, differential element It is a wave form diagram which compares and shows an output, starting element output, external discrimination element output, CT saturation countermeasure element output, relay operation output, and sampling period. In FIG. 7, 1 is a bus, 2 is CT, 3 is AuxCT (auxiliary CT), 4 is a simple differential element, 5 is a ratio differential element, 6 is an external determination element, 7 is an activation element, 8 is an AND circuit, 9 is a timer circuit, 10 is a NOT circuit, 11 is an AND circuit, 12 is a differential operation circuit, 13 is a suppression operation circuit, 14 is a differential operation circuit, and 15 is a timer circuit. The simple differential element 4 includes the differential arithmetic circuit 12, the differential arithmetic circuit 14, and the timer circuit 15. 16 is a ratio determination circuit, and 17 is a timer circuit. The ratio differential element 5 includes the suppression calculation circuit 13, the ratio determination circuit 16, and the timer circuit 17.
[0003]
18 is a current change determination circuit, 19 is a timer circuit, 20 is an instantaneous differential operation circuit, 21 is an instantaneous suppression operation circuit, and 22 is an external determination circuit. The external determination element 6 includes the instantaneous differential calculation circuit 20, the instantaneous suppression calculation circuit 21, and the external determination circuit 22. The activation element 7 includes the current change determination circuit 18 and the timer circuit 19. Reference numeral 100 denotes a differential element, which includes the simple differential element 4 and the ratio differential element 5. Reference numeral 200 denotes a CT saturation countermeasure element, which includes the external determination element 6, the activation element 7, the AND circuit 8, the timer circuit 9, and the NOT circuit 10. The differential arithmetic circuit 12, the suppression arithmetic circuit 13, the differential arithmetic circuit 14, the ratio determination circuit 16, the current change determination circuit 18, the instantaneous differential arithmetic circuit 20, the instantaneous suppression arithmetic circuit 21, And the expression in each block of the external determination circuit 22 represents each function.
[0004]
The current of each feeder CT2 connected to the bus 1 is input to the relay via the AuxCT (auxiliary CT) 3, and the elements in the relay are roughly divided into a simple differential element 4 and a ratio differential element. 5 and
And a CT saturation countermeasure element 200 including an external determination element 7, an activation element 6, and an AND circuit 8. As the operation output of the relay, since the output of the differential element 100 is locked by the output of the CT saturation countermeasure element 200, the simple differential element 4, the ratio differential element 5, and the CT saturation countermeasure NOT are used. An AND circuit 11 that inputs the output of the circuit 10 is used as an output. The currents IT1 to ITn of the feeders T1 to Tn are input to the relay via the feeders CT2 and AuxCT3, and become currents i1,.
[0005]
The differential current Id is calculated by the arithmetic circuit 12 that calculates the execution value | i1 +... + In | of the vector sum, and the suppression current Ires is the scalar sum | i1 | +. Calculation is performed by the arithmetic circuit 13 that performs the calculation (where || indicates the result of the execution value calculation). In the simple differential element 4, the differential arithmetic circuit 14 determines Id> K1. In the ratio differential element 5, the ratio determination circuit 16 determines Id> R1 · Ires−K2. Timer (on-delay timer) circuits 15 and 17 are provided at the outputs of the differential arithmetic circuit 14 and the ratio determining circuit 16, respectively. In the meanings of t1 / t2 of the timers 15 and 17, t1 indicates an operation side delay time, and t2 indicates a return side delay time.
[0006]
On the other hand, the activation element 7 of the CT saturation countermeasure element 200 detects a change amount of each feeder CT2 current, and outputs the change amount when the change amount exceeds a certain value. | Δi1 |> K3,... | Δin |> The output is output through a timer circuit 19 that receives the output of the circuit 18 that is determined when any of K3 is established.
[0007]
The external discrimination element 6 of the CT saturation countermeasure element 200 performs a ratio calculation from the input current sample value (instantaneous value) or detects no change in the differential current. For example, || i1 +... + In || <R2 · (|| i1 || + ... + || in ||) (where || ** || indicates the absolute value of *), the arithmetic circuits 20, 21, 22 Composed.
[0008]
By using the instantaneous value in this way, even when a CT is saturated with a large current due to the occurrence of an external failure and a differential current is generated, the circuit can be detected by sampling several times until CT saturation occurs. In order that the CT saturation countermeasure circuit 200 can detect only when a failure occurs so that it is not always detected by the power flow, the activation element and the AND circuit 8 are ANDed.
Is output. After the output, the timer circuit 9 set for several cycles on the return side in order to lock the differential for a certain period until the CT saturation phenomenon is settled and the differential element ceases to operate unnecessary. is there.
[0009]
In the prior art, as described above, the external failure is determined in a short time until the CT saturation occurs and the differential element is locked for a certain period of time, for example, the CT is saturated by the external failure. Thus, a bus relay that does not malfunction even when a differential amount occurs is realized.
[0010]
Next, the operation will be described. When the feeder CT is not saturated at all, in the case of an external failure, the differential current Id is generated only by the amount corresponding to the sum of CT errors and relay errors, and the differential element does not operate. On the other hand, in the case of an internal failure, the vector sum Id and the scalar sum Ires of all the feeder currents are almost the same amount, so that they operate within the operating range represented by the operation formula of the differential element circuit 4. Thus, the internal / external failure is identified.
[0011]
The CT saturation countermeasure described in the prior art will be described with reference to FIG. When an external fault occurs, when current concentrates on any feeder line CT and saturation of that line CT begins, the differential error current calculated by the sum of the unsaturated line and the saturated line Id (in the figure, the feeder has two lines for simplification, the inflow side CT does not saturate and the outflow side CT saturates) increases suddenly when CT saturation starts, The differential element 100 determines internally. However, CT saturation immediately after the occurrence of an external failure has been detected as an Id of several ms that has not yet started, and an external discriminating element is output in a period that can be neglected (between two samplings in the figure). Output. The relay operation output is finally blocked by extending the output and locking the output of the differential element 100 while a difference current is generated due to CT saturation. The activation element 7 is configured so that the external determination element can be output only when a failure occurs, so that the external determination is not always performed by the power flow.
[0012]
[Problems to be solved by the invention]
Since the conventional bus protection relay is configured as described above, when the current concentrates on a certain line due to an external fault current and there is CT saturation on the line, the differential current is generated by the differential current generated by CT saturation. Before an element outputs an unnecessary output, the output is detected and the output is locked. The lock time is set to a period during which a differential current is detected (for example, several cycles). The longer the lock time, the more stable operation can be obtained against external faults. Instead, for example, when a fault progresses from an external fault to an internal fault, it will stop working immediately against the internal fault. Have drawbacks.
[0013]
Furthermore, the current starting element may be detected unnecessarily because a healthy phase current also changes when a one-phase failure occurs in a healthy phase other than the failed phase when a bus one-phase failure occurs. For this reason, for example, when there is a failure progression from an external one-phase failure to an internal other phase, First Since the starting element outputs an external failure for the purpose of external determination and the external determination is made, there is a drawback in that the operation is greatly delayed because it is locked even when progressing to another phase internal failure.
[0014]
The present invention has been made to solve the above-mentioned problems, and is intended to enable more accurate countermeasures against CT saturation at the time of an external failure, and when it has progressed from an external failure to an internal failure. The purpose is to reduce the operation delay due to the CT saturation countermeasure.
[0015]
[Means for Solving the Problems]
The bus protection relay according to the first aspect of the present invention includes a differential element that inputs a current of each feeder line connected to the bus line via the CT and the differential element caused by CT saturation at the time of an external failure. In a bus protection relay including a CT saturation countermeasure element that prevents malfunction output due to operation, the differential element outputs a plurality of ratio differential outputs having different operating ranges, and the CT saturation countermeasure element includes the plurality of ratio differences. Multiple lock outputs with different lock times corresponding to the differential error current unnecessary output time of the dynamic output are output, and the ratio of the differential error current unnecessary output time is long The differential output is locked by the lock output with the long lock time. The erroneous output is prevented by locking the differential output with a short differential error current unnecessary output time with a lock output having a short lock time.
[0016]
According to a second aspect of the present invention, there is provided a bus protection relay including a differential element for inputting a current of each feeder line connected to the bus via the CT and a differential element caused by CT saturation at the time of an external failure. In a bus protection relay provided with a CT saturation countermeasure element that prevents malfunction output due to operation, the differential element outputs a plurality of ratio differential outputs having different operating ranges, and a differential error is generated by the output of the CT saturation countermeasure element. The above-mentioned malfunction output is prevented by changing the ON delay setting time of the differential output with a long current unnecessary output time to a time longer than the ON delay setting time of the differential output with a short differential error current unnecessary output time. is there.
[0017]
According to a third aspect of the present invention, there is provided a bus protection relay including a differential element for inputting a current of each feeder line connected to the bus via the CT, and a differential element caused by CT saturation at the time of an external fault. In a bus protection relay including a CT saturation countermeasure element that prevents malfunction output due to operation, the differential element outputs a plurality of ratio differential outputs having different operating ranges, and the CT saturation countermeasure element includes the plurality of ratio differences. Multiple lock outputs with different lock times corresponding to the differential error current unnecessary output time of the dynamic output are output, and the ratio of the differential error current unnecessary output time is long The differential output is locked by the lock output with the long lock time. The differential error current unnecessary output time is short. The differential output is locked by a lock output having a short lock time to prevent the malfunction output and the CT saturation countermeasure element. By changing the ON delay setting time of the differential output with a long differential error current unnecessary output time to a longer ratio than the ON delay setting time of the differential output without changing the differential error current unnecessary output time. It is to prevent.
[0018]
According to a fourth aspect of the present invention, there is provided a bus protection relay comprising: a differential element that inputs a current of each feeder line connected to the bus line via CT; and the differential element that is caused by CT saturation at the time of an external fault. In a bus protection relay having a CT saturation countermeasure element that prevents malfunction output due to operation by locking the operation output for a predetermined time, CT saturation is smaller than the lock time when CT saturation is large and the differential current width is large. The lock time is controlled to be small when the dynamic current width is small.
[0019]
The busbar protection relay according to the invention of claim 5 is: As described in any one of Claims 1-4. In the bus protection relay, the fault phase is determined from the bus voltage by any of the undervoltage element, the direction relay element, and the distance relay element, and the CT saturation countermeasure element is activated only for the fault phase based on the determination result. is there.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram of a bus protection relay according to Embodiment 1 of the present invention. The same reference numerals as those in the conventional functional block diagram (FIG. 7) are the same as those in the conventional functional block diagram (FIG. 7). Or, it is for the same purpose, and the description of the same thing is omitted.
[0021]
In FIG. 1, 161 is a second ratio differential element, 171 is a timer circuit provided at the output of the second ratio differential element 161, and 23 is a second timer. The output of the AND circuit 8 that takes an AND with the element 6 is input. An AND circuit 24 inputs the output of the ratio determination circuit 16 via the timer circuit 17 and inputs the output of the timer circuit 9 via the NOT circuit 10. An AND circuit 34 inputs the output of the second ratio determination circuit 161 via the timer circuit 171 and inputs the output of the timer circuit 23 via the NOT circuit 10. The return delay setting time t6 of the timer circuit 9 is about 3 cycles, the return delay setting time t7 of the second timer 23 is about 1 cycle, and the return delay setting time t6 of the timer circuit 9 is The relationship is t6> t7.
[0022]
Next, the operation will be described. In order to speed up the relay operation when an internal failure occurs, each operation verification time t1 of the differential differential element 5 and the simple differential element 4 (on-delay setting time t1 of the timer circuits 15 and 17) is set as short as possible. It is. On the other hand, when an external failure occurs, a stable operation can be obtained by setting the operation verification time longer. When CT saturation occurs at the time of an external failure, the differential error current Id repeatedly increases and decreases as described with reference to FIG. This is shown in FIG.
[0023]
As shown in FIG. 2, in the first wave (differential error current in the first sampling period), the operating time in the first ratio differential element 16 (the operating range is Id> R1 · Ires−K2). (Differential error current unnecessary output time) is relatively long, but the second ratio differential element 161 having an operation area narrower than the first ratio differential element 16 (the operation area is Id> R11 · Ires−K21) It was found that the operation time (output time without differential error current) was short. That is, it is necessary to lengthen the time for locking the unnecessary operation time of the first ratio differential element 16 (for example, three cycles), but the lock time for the second ratio differential element 161 can be shortened ( For example, one cycle) is understood.
[0024]
By utilizing this, the lock time can be optimally set in accordance with the operation region of the ratio differential element, and even if a failure progresses from an external failure to an internal failure, the internal failure is essentially Id = Since Ires (when the external fault is removed), the second ratio differential element 161 can be operated after the short lock time is released.
[0025]
In other words, the first embodiment described above is a suppression that is scalar summed with the differential current Id obtained by inputting the CT currents of all feeder lines connected to the bus 1 and adding the feeder currents as vectors. In a bus protection relay for calculating a current Ires to provide a ratio characteristic to detect an internal failure on the bus, a second ratio differential element 161 and a second external determination output element 23 are provided, and a ratio difference is determined at the time of external determination. A CT saturation countermeasure element 200 that can be set to a lock time according to the moving region can be used to more accurately take measures against CT saturation at the time of an external failure, and CT saturation when an external failure progresses to an internal failure. The operation delay due to the countermeasures can be reduced.
[0026]
In other words, in the first embodiment, the differential element 100 for inputting the current of each feeder line connected to the bus 1 via the CT and the differential due to the CT saturation at the time of an external failure are put in another concept. In the bus protection relay including the CT saturation countermeasure element 200 that prevents malfunction output due to the operation of the element, the differential element 100 outputs a plurality of ratio differential outputs (outputs of the ratio determination circuits 16 and 161) having different operation ranges. The CT saturation countermeasure element outputs a plurality of lock outputs (outputs of timers 9 and 23) corresponding to the plurality of ratio differential outputs, and the plurality of ratio differential outputs and the plurality of lock outputs This prevents the malfunction output, can more accurately take measures against CT saturation at the time of external failure, and can reduce the operational delay due to measures against CT saturation when progressing from an external failure to an internal failure.
[0027]
Specifically, as described above, the malfunction output due to the differential element that inputs the current of each feeder line connected to the bus via the CT and the operation of the differential element due to the CT saturation at the time of external failure is generated. In a bus protection relay having a CT saturation countermeasure element to prevent, the differential element outputs a plurality of ratio differential outputs having different operating ranges, and the CT saturation countermeasure element provides a differential of the plurality of ratio differential outputs. Multiple lock outputs with different lock times corresponding to the error current unnecessary output time are output, and the differential error current unnecessary output time ratio is long. By locking the differential output with a short unnecessary output time with a lock output with a short lock time, the malfunction output is prevented, and the CT saturation countermeasure at the time of external failure is more accurately For example, also those which can reduce the operational delay due to CT saturation measures in the case of progress to internal faults external faults.
[0028]
Embodiment 2. FIG.
In the first embodiment, the method of locking the ratio differential element 5 has been exemplified. However, as shown in FIG. 3, the respective comparison times of the first ratio differential element 16 and the second ratio differential element 161 are compared. (That is, the operation confirmation time) is controlled when there is an output of the CT saturation countermeasure element 200, that is, the on-delay setting time t1 of the timer circuit 17 at the output end of the first ratio differential element 16 is set to t8 (for example, 40 ms), and the on-delay setting time t1 of the timer circuit 171 at the output end of the second ratio differential element 161 whose differential region is narrower than that of the first ratio differential element 16 is controlled to t9 (for example, 15 ms). Thus, as in the case of the lock in the first embodiment, the CT saturation countermeasure at the time of the external failure can be performed more accurately, and the operation delay due to the CT saturation countermeasure when the external failure progresses to the internal failure is reduced. At least Is shall.
[0029]
In FIG. 3, reference numeral 25 denotes a timer control circuit for controlling the on-delay set time t1 of the timer circuit 17 to t8 (for example, 40 ms). The control operation is controlled by the output of the timer circuit 9 of the CT saturation countermeasure element 200. Do. A timer control circuit 26 controls the on-delay set time t1 of the timer circuit 171 to t9 (for example, 15 ms), and performs a control operation based on the output of the timer circuit 23 of the CT saturation countermeasure element 200. In the case of this configuration, it is possible to delete the timer circuit 23 and control both the timer control circuits 25 and 26 with the output of the timer circuit 9.
[0030]
In other words, the above-described second embodiment is based on the differential element 100 that inputs the current of each feeder line connected to the bus 1 via the CT and the operation of the differential element due to CT saturation at the time of external failure. In the bus protection relay including the CT saturation countermeasure element 200 for preventing malfunction output, the differential element 100 outputs a plurality of ratio differential outputs (outputs of the ratio determination circuits 16 and 161) having different operation ranges, and The CT saturation countermeasure element 200 outputs a plurality of outputs (outputs of the timer-control circuits 25 and 26) corresponding to the plurality of ratio differential outputs, and corresponds to the plurality of ratio differential outputs of the CT saturation countermeasure element. The malfunction output is prevented by changing the time at which the plurality of ratio differential outputs are output by a plurality of outputs. Similarly to the case of the lock in the first embodiment, the CT saturation pair at the time of external failure More accurately performed, also those that can reduce the operation delay due to CT saturation measures in the case of progress to internal faults external faults.
[0031]
Specifically, as described above, the malfunction output due to the differential element that inputs the current of each feeder line connected to the bus via the CT and the operation of the differential element due to the CT saturation at the time of external failure is generated. In a bus protection relay having a CT saturation countermeasure element to prevent, the differential element outputs a plurality of ratio differential outputs having different operating ranges, and the differential error current unnecessary output time is determined by the output of the CT saturation countermeasure element. The malfunction output is prevented by changing the on-delay setting time of the long ratio differential output to a time longer than the on-delay setting time of the ratio differential output that has a short differential error current unnecessary output time. As in the case of the lock in No. 1, the CT saturation countermeasure at the time of external failure can be performed more accurately, and the operation delay due to the CT saturation countermeasure when progressing from an external failure to an internal failure can be reduced. It is intended.
[0032]
Embodiment 3 FIG.
FIG. 4 is a functional block diagram of the busbar protection relay showing the third embodiment, which has the functions of the first embodiment and the second embodiment, and the circuit configuration is the same as that of the first embodiment. In addition to the circuit of the first embodiment, the operation of the second embodiment is more accurate than that of the above-described first embodiment and the second embodiment of the present invention. It is possible to accurately reduce the operation delay due to the CT saturation countermeasure when progressing to an internal failure.
[0033]
Specifically, a differential element that inputs the current of each feeder line connected to the bus via CT, and a CT saturation countermeasure that prevents malfunction output due to the operation of the differential element due to CT saturation at the time of external failure In a bus protection relay including an element, the differential element outputs a plurality of ratio differential outputs having different operating ranges, and the CT saturation countermeasure element outputs a differential error current unnecessary output time of the plurality of ratio differential outputs. Outputs multiple lock outputs with different lock times corresponding to the ratio of the output time that does not require differential error current is long Ratio of differential outputs that are locked by lock output that has a long lock time and short output time that does not require differential error current The differential output is locked by a lock output with a short lock time to prevent the malfunction output, and the output of the CT saturation countermeasure element prevents a differential error current from being output. The erroneous output is prevented by changing the on-delay setting time of the long ratio differential output to a time longer than the on-delay setting time of the short ratio differential output. 1. More accurate operation than 1 and the above-described second embodiment, can more accurately take measures against CT saturation at the time of external failure, and also operate according to measures against CT saturation when progressing from an external failure to an internal failure The delay can be reduced appropriately.
[0034]
Embodiment 4 FIG.
In the first embodiment described above, a system in which two circuits for a fixed time receiving the output of the external determination element 6 are provided is illustrated. However, as shown in FIG. 5, the fourth embodiment has an instantaneous differential current. A time width measuring circuit 27 that measures a time (time width) that is equal to or greater than the value, and a timer-control circuit 28 that controls the lock time t6 to t10 according to the time width obtained by the time width measuring circuit 27, The lock time is controlled according to the generation width of the operation error current at the time of external failure.
[0035]
When CT saturation is large and the influence of CT saturation continues until the second wave, it is necessary to set the lock time to 2 or 3 cycles or more, but when CT saturation is relatively small, the first wave and the second wave An opportunity to make an external decision again occurs between the waves. In this case, the lock time may be one cycle. That is, an optimum lock time can be obtained by measuring a time width T in which the absolute value of the instantaneous differential error current is greater than a certain value (for example, K3) and changing to a lock time corresponding to that time. Since it does not lock longer than necessary, it is possible to minimize the operation delay due to the failure progression from the outside to the inside. As a simple application, when the existence time T of the instantaneous differential current continues for a certain time (for example, 0.5 cycle) or more, the lock time is set to several cycles. In the case where the lock time is short, it is also possible to perform control to set the lock time to one cycle, for example.
[0036]
In other words, the fourth embodiment of the present invention is based on the differential element that inputs the current of each feeder line connected to the bus line via CT and the operation of the differential element due to CT saturation at the time of external failure. In a bus protection relay provided with a CT saturation countermeasure element that prevents malfunction output by locking the operation output for a predetermined time, the CT saturation is smaller than the lock time when the CT saturation is large and the differential current width is large. The lock time when the width is small is controlled to be small, and as described above, the optimum lock time can be set and the lock time is not longer than necessary. The operation delay can be minimized.
[0037]
Embodiment 5. FIG.
In the above-described first to fourth embodiments, the countermeasure for delaying the operation time in the case of a failure that progresses to an internal failure in phase with the external failure is exemplified. However, in this fifth embodiment, as shown in FIG. This is an example of countermeasures against an operation delay caused by a failure progress to a phase. In FIG. 6, 29 is a PT (voltage converter) for guiding the bus voltage to the relay, 30 is a voltage converter for converting the PT output voltage to the relay internal circuit voltage, 31 is an undervoltage detection element, and voltage comparison The circuit 32 and the timer circuit 33 are constituted. The output of the undervoltage detection element 31 is input to the AND circuit 8.
[0038]
Since the conventional starting element 7 is due to a current change, for example, a healthy phase current other than the fault phase also changes when an external one-phase fault occurs, so there is a possibility of unnecessary detection, but for the bus voltage, Since the decrease in the healthy phase voltage is relatively small, it is possible to set a setting value at which the fault phase can be determined as the detection setting for the undervoltage element. By combining with this undervoltage detection, a circuit that can be activated only for the failure occurrence phase is obtained, and a circuit that has no operation delay even in the case of failure progression from one external phase to another internal phase is obtained. In place of the undervoltage element, the same effect as in the case where the undervoltage element is used as a relay direction element or distance element can be obtained.
[0039]
In other words, the fifth embodiment of the present invention is based on the differential element that inputs the current of each feeder line connected to the bus line via CT and the operation of the differential element due to CT saturation at the time of external failure. In a bus protection relay having a CT saturation countermeasure element for preventing malfunction output, a fault phase is determined from the bus voltage by any of an undervoltage element, a direction relay element, and a distance relay element, and the CT If the saturation countermeasure element is activated only for the failure phase, and if only the CT saturation countermeasure element is used, the lock is performed up to the healthy phase by locking up to the healthy phase, and when the internal failure progresses to an internal failure that is different from the external failure, The inconvenience that is delayed can be solved.
[0040]
【The invention's effect】
The invention of the bus protection relay according to claim 1 is characterized in that the current of each feeder line connected to the bus is input via the CT and the operation of the differential element due to CT saturation in the event of an external failure. In the bus protection relay provided with a CT saturation countermeasure element for preventing malfunction output due to the above, the differential element outputs a plurality of ratio differential outputs with different operating ranges, and the CT saturation countermeasure element includes the plurality of ratio differentials. Multiple lock outputs with different lock times corresponding to output differential error current unnecessary output time are output, ratio of differential error current unnecessary output time is long, and differential output is locked by lock output with long lock time, Since the differential output without unnecessary differential error current is locked by the lock output with a short lock time for the differential output, the malfunction output is prevented. Performed saturated measures more accurately, also, there is an effect of reducing the operational delay due to CT saturation measures in the case of progress to internal faults external faults.
[0041]
The invention of the bus protection relay according to claim 2 is characterized in that the current of each feeder line connected to the bus is input via the CT and the operation of the differential element due to CT saturation at the time of external failure In the bus protection relay provided with a CT saturation countermeasure element for preventing malfunction output due to the above-mentioned, the differential element outputs a plurality of ratio differential outputs with different operating ranges, and the CT saturation countermeasure element Out of By changing the ratio of the differential error current unnecessary output time to a longer ratio, the differential output on-delay setting time is changed to the ratio of the differential error current unnecessary output time to a shorter ratio differential output on-delay setting time. Therefore, it is possible to more accurately take measures against CT saturation at the time of an external failure, and to reduce the operation delay due to the measures against CT saturation when progressing from an external failure to an internal failure.
[0042]
The invention of the bus protection relay according to claim 3 is a differential element for inputting the current of each feeder line connected to the bus via the CT, and the operation of the differential element due to CT saturation at the time of external failure. In the bus protection relay provided with a CT saturation countermeasure element for preventing malfunction output due to the above, the differential element outputs a plurality of ratio differential outputs with different operating ranges, and the CT saturation countermeasure element includes the plurality of ratio differentials. Outputs multiple lock outputs with different lock times corresponding to the output time that does not require differential error current of the output.The ratio of differential output that does not require differential error current is long. The differential output with a short dynamic error current unnecessary output time is locked by a lock output with a short lock time to prevent the malfunction output and output of the CT saturation countermeasure element The ratio of the output delay time without the differential error current is longer. The output delay time of the differential output is changed to the time longer than the ratio of the ON delay setting time of the differential output. Thus, there is an effect that the CT saturation countermeasure at the time of an external failure can be performed more accurately, and the operation delay due to the CT saturation countermeasure when progressing from an external failure to an internal failure can be accurately reduced.
[0043]
According to a fourth aspect of the present invention, there is provided a bus protection relay comprising: a differential element that inputs a current of each feeder line connected to the bus line via CT; and the differential element that is caused by CT saturation at the time of an external fault. In a bus protection relay having a CT saturation countermeasure element that prevents malfunction output due to operation by locking the operation output for a predetermined time, CT saturation is smaller than the lock time when CT saturation is large and the differential current width is large. Since the lock time is controlled to be small when the dynamic current width is small, it is possible to more appropriately take measures against CT saturation at the time of external failure, and to minimize the operation delay due to the failure progress from the outside to the inside. There is an effect that can.
[0044]
The busbar protection relay according to the invention of claim 5 is: As described in any one of Claims 1-4. In the bus protection relay, the fault phase is determined from the bus voltage by any of the undervoltage element, the direction relay element, and the distance relay element, and the CT saturation countermeasure element is activated only for the fault phase based on the determination result. Therefore, the CT saturation countermeasure at the time of external failure can be more accurately performed, and there is an effect that operation delay can be eliminated even in the case of failure progression from one external phase to another internal phase.
[0045]
[Brief description of the drawings]
FIG. 1 is a functional block diagram showing a first embodiment of the present invention.
FIG. 2 is an operation explanatory diagram of Embodiment 1 of the present invention.
FIG. 3 is a functional block diagram showing Embodiment 2 of the present invention.
FIG. 4 is a functional block diagram showing Embodiment 3 of the present invention.
FIG. 5 is a functional block diagram showing Embodiment 4 of the present invention.
FIG. 6 is a functional block diagram showing Embodiment 5 of the present invention.
FIG. 7 is a functional block diagram of a conventional bus protection relay.
FIG. 8 is an operation waveform diagram of a conventional busbar protection relay.
[0046]
[Explanation of symbols]
1 bus, 2 CT
4 simple differential elements, 5 ratio differential elements,
6 external decision elements, 7 activation elements,
12 differential operation circuit, 13 suppression operation circuit,
14 differential operation circuit, 16 ratio determination circuit,
25 timer-control circuit, 26 second timer-control circuit,
27 time width measurement circuit, 28 timer control circuit,
31 undervoltage element, 32 voltage judgment circuit,
161 Second ratio determination circuit, 100: differential element,
200 CT saturation countermeasure element.

Claims

A bus having a differential element for inputting the current of each feeder line connected to the bus through the CT and a CT saturation countermeasure element for preventing malfunction output due to the operation of the differential element due to CT saturation at the time of external failure In the protection relay, the differential element outputs a plurality of differential ratio outputs with different operating ranges, and the CT saturation countermeasure element has different locks corresponding to the differential error current unnecessary output time of the plurality of differential ratio outputs. Output multiple lock outputs of time, ratio output with a long differential error current unnecessary output time is locked to a differential output with a lock output with a long lock time, and a differential output with a short differential error current unnecessary output time On the other hand, a bus protection relay, wherein the malfunction output is prevented by locking with a lock output with a short lock time.

A bus having a differential element for inputting the current of each feeder line connected to the bus through the CT and a CT saturation countermeasure element for preventing malfunction output due to the operation of the differential element due to CT saturation at the time of external failure In the protection relay, the differential element outputs a plurality of differential ratio outputs having different operating ranges, and the differential delay current unnecessary output time is long due to the output of the CT saturation countermeasure element. The bus protection relay is characterized in that the malfunction output is prevented by changing the output time to a time longer than the on-delay setting time of the differential output where the differential error current unnecessary output time is short.

A bus having a differential element for inputting the current of each feeder line connected to the bus through the CT and a CT saturation countermeasure element for preventing malfunction output due to the operation of the differential element due to CT saturation at the time of external failure In the protection relay, the differential element outputs a plurality of differential ratio outputs with different operating ranges, and the CT saturation countermeasure element has different locks corresponding to the differential error current unnecessary output time of the plurality of differential ratio outputs. Outputs multiple lock outputs of the time, and the ratio of the differential error current unnecessary output time is long. In addition, the malfunction output is prevented by locking with a lock output with a short lock time, and the output time of the differential error current unnecessary output is long due to the output of the CT saturation countermeasure element. Bus protection relay, characterized in that to prevent the malfunction output by changing the on-delay setting time of the dynamic output to the differential error current required output time is short ratio differential output longer than the on-delay setting time -.

By locking the operation output for a predetermined time by a differential element that inputs the current of each feeder line connected to the bus through the CT and a malfunction output due to the operation of the differential element due to CT saturation at the time of external failure In a bus protection relay having a CT saturation countermeasure element to prevent, the lock time when CT saturation is small and the differential current width is small is controlled to be smaller than the lock time when CT saturation is large and the differential current width is large. Featured busbar protection relay.

5. The bus protection relay according to claim 1, wherein a fault phase is determined from a bus voltage by any one of an undervoltage element, a direction relay element, and a distance relay element, and the CT is determined based on the determination result. A bus protection relay in which the saturation countermeasure element is activated only for the fault phase.