JP3207643B2 - Short circuit accident high-speed judgment circuit - Google Patents

Short circuit accident high-speed judgment circuit

Info

Publication number
JP3207643B2
JP3207643B2 JP30074293A JP30074293A JP3207643B2 JP 3207643 B2 JP3207643 B2 JP 3207643B2 JP 30074293 A JP30074293 A JP 30074293A JP 30074293 A JP30074293 A JP 30074293A JP 3207643 B2 JP3207643 B2 JP 3207643B2
Authority
JP
Japan
Prior art keywords
circuit
output
short
integration
wave rectifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP30074293A
Other languages
Japanese (ja)
Other versions
JPH07163042A (en
Inventor
誠一 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP30074293A priority Critical patent/JP3207643B2/en
Publication of JPH07163042A publication Critical patent/JPH07163042A/en
Application granted granted Critical
Publication of JP3207643B2 publication Critical patent/JP3207643B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Emergency Protection Circuit Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、短絡事故による過大電
流の立上りに反応し高速判定する回路殊に保護継電器に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for determining a high speed in response to the rise of an excessive current caused by a short circuit, and more particularly to a protective relay.

【0002】[0002]

【従来の技術】従来、短絡保護継電器では、過大電流レ
ベルが連続して流れた場合に短絡事故を判定しているた
め、半サイクル以上の判定時間必要であり、更に外部出
力を生ずるまでには数msの時間が必要となる。
2. Description of the Related Art Conventionally, in a short-circuit protection relay, a short-circuit fault is determined when an excessive current level continuously flows. Therefore, a determination time of half a cycle or more is required. A time of several ms is required.

【0003】すなわち、図5に示すように正常時の負荷
電流波形Aに対して短絡事故時の短絡電流Zが生じた場
合、短絡電流判定値レベルLを基準に判定しており、短
絡電流検出波形Kを得る。このとき、ノイズやサージに
よる誤動作を防止するため過大電流の連続性を確認して
いる。したがって、数十msの過大電流が流れてから短
絡判定が行なわれる。
That is, as shown in FIG. 5, when a short-circuit current Z at the time of a short-circuit fault occurs with respect to a normal load current waveform A, the judgment is made based on the short-circuit current judgment value level L. A waveform K is obtained. At this time, the continuity of the excessive current is confirmed to prevent malfunction due to noise or surge. Therefore, short circuit determination is performed after an excessive current of several tens of ms flows.

【0004】[0004]

【発明が解決しようとする課題】上述の如く保護動作時
に数十msの間短絡電流が負荷や電路に流れるので、計
測器や保護継電器の交換が必要なこともあり、また負荷
や電路に過大なストレスを生じている。
As described above, a short-circuit current flows through a load or an electric circuit for several tens of milliseconds during the protection operation, so that the measuring instrument or the protective relay may need to be replaced. Stress is occurring.

【0005】本発明は、上述の問題に鑑み、半サイクル
以上の短絡事故判定時間を短縮して負荷や電路へのスト
レスを小さく短絡事故の損傷を最低限にする短絡事故高
速判定回路の提供を目的とする。
The present invention has been made in view of the above-mentioned problems, and provides a short-circuit accident high-speed judgment circuit which shortens a short-circuit accident judgment time of half a cycle or more, reduces stress on a load or an electric circuit, and minimizes damage of a short-circuit accident. Aim.

【0006】[0006]

【課題を解決するための手段】上述の目的を達成する本
発明は、負荷電流に比例した検出電圧の半波のみを整流
する半波整流回路と、この半波整流回路の出力を入力す
る第1積分回路及び遅延回路と、この遅延回路の出力を
入力するレベル検出回路及び第2積分回路と、このレベ
ル検出回路及び第2積分回路それぞれの出力を加算する
加算回路と、この加算回路の出力と上記第1積分回路の
出力との差を求める減算回路と、この減算回路出力と予
め定められた値とを比較する比較回路と、を有すること
を要旨とする。
SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a half-wave rectifier circuit for rectifying only a half-wave of a detection voltage proportional to a load current, and a second circuit for inputting an output of the half-wave rectifier circuit. (1) an integration circuit and a delay circuit, a level detection circuit and a second integration circuit that receive an output of the delay circuit, an addition circuit that adds the outputs of the level detection circuit and the second integration circuit, and an output of the addition circuit And a comparison circuit for comparing the output of the subtraction circuit with a predetermined value.

【0007】また、本発明は、負荷電流に比例した検出
電圧の半波のみを整流する半波整流回路と、この半波整
流回路の出力を入力とする第1積分回路及び遅延回路
と、この遅延回路出力を入力する第2積分回路と、上記
第1積分回路と第2積分回路との出力差を得る減算回路
と、この減算回路出力と予め定められた値とを比較する
比較回路と、を有することを要旨とする。
Further, the present invention provides a half-wave rectifier circuit for rectifying only a half-wave of a detection voltage proportional to a load current, a first integration circuit and a delay circuit which receive an output of the half-wave rectifier circuit, A second integration circuit for receiving an output of the delay circuit, a subtraction circuit for obtaining an output difference between the first integration circuit and the second integration circuit, a comparison circuit for comparing the output of the subtraction circuit with a predetermined value, The gist is to have.

【0008】さらに、本発明は、上記にあって、負荷電
流につき正負各極性二通りの回路構成を有し、それぞれ
の比較回路出力の論理和を採り出力を得ることを要旨と
する。
Further, the present invention has the above-mentioned configuration, and has a gist having a circuit configuration of two types of positive and negative polarities with respect to a load current, and obtaining an output by taking a logical sum of outputs of respective comparison circuits.

【0009】[0009]

【作用】短絡事故による過大電流変化量を遅延回路によ
るΔt時間内の積算値により判定しているため、最終短
絡電流近傍に至るまえに短絡事故を検出でき、またΔt
時間の積算値により判断しているため、ノイズ、サージ
等の瞬時レベル変化による誤動作も防止できるので、検
出後即座に判定出力が得られる。この結果、短絡事故を
Δt時間で判定することが可能になる。
Since the amount of change in excessive current due to a short circuit is determined based on the integrated value within the time Δt by the delay circuit, the short circuit can be detected before reaching the vicinity of the final short circuit current.
Since the determination is made based on the integrated value of time, malfunction due to an instantaneous level change such as noise and surge can be prevented, so that a determination output can be obtained immediately after detection. As a result, a short circuit accident can be determined based on the time Δt.

【0010】[0010]

【実施例】図1〜図4を参照して本発明の実施例を説明
する。図1において、電路には変流器1が設置され、こ
の変流器1はI/V変換器2に接続されている。このI
/V変換器2は、検出した負荷電流に比例した電流を電
圧に変換するものである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. In FIG. 1, a current transformer 1 is installed on an electric circuit, and the current transformer 1 is connected to an I / V converter 2. This I
The / V converter 2 converts a current proportional to the detected load current into a voltage.

【0011】I/V変換器2による出力電圧は、正極性
の半波と負極性の半波の各ルートに分けて処理されるの
であるが、ここでは便宜上正極性のルートを中心に説明
する。
The output voltage of the I / V converter 2 is processed separately in each of a positive half-wave route and a negative half-wave route. Here, the positive polarity route will be mainly described for convenience. .

【0012】I/V変換器2の出力の正電圧のみを整流
する半波整流回路3が備えられ、この半波整流回路3の
出力は第1積分回路9と遅延回路5とに接続される。こ
の第1積分回路9は電圧の積分値(面積)を得るもので
あり、遅延回路5は時間Δt計測用に用いられる。
A half-wave rectifier circuit 3 for rectifying only the positive voltage output from the I / V converter 2 is provided, and the output of the half-wave rectifier circuit 3 is connected to a first integration circuit 9 and a delay circuit 5. . The first integration circuit 9 obtains an integrated value (area) of the voltage, and the delay circuit 5 is used for measuring the time Δt.

【0013】遅延回路5の出力は、レベル検出器13と
第2積分回路10とに接続され、レベル検出器13はh
1 ×Δtのレベル検出を行ない(図2参照)、第2積分
回路10ではS1 の積分を行なう(図2参照)。
The output of the delay circuit 5 is connected to a level detector 13 and a second integration circuit 10, and the level detector 13 outputs h
Performs level detection of 1 × Delta] t (see FIG. 2), the second integrating circuit 10 performs integration of S 1 (see FIG. 2).

【0014】したがって、加算回路15では、レベル検
出器13の出力h1 ×Δtと第2積分回路10の出力S
1 とが加算される。そして、この加算回路15の出力と
第1積分回路9との減算を減算回路17にて行ない図2
斜線部分であるS2 −(S1 +h1 ×Δt)を求める。
この減算回路17の出力は比較回路10にて整定値回路
19の値と比較し、一定値を越えると比較回路20の出
力が出る。すなわち、前述のS2 −(S1 +h1 ×Δ
t)が一定以上あるときには比較出力が出ることにな
る。また、第1及び第2積分回路9,10での放電は、
反転半波整流回路4によるルートでの立上り検出器8に
て行なわれている。
Therefore, in the adding circuit 15, the output h 1 × Δt of the level detector 13 and the output S
1 is added. Then, the output of the adder 15 and the first integrator 9 are subtracted by a subtractor 17 to obtain a signal shown in FIG.
A hatched portion S 2 - Request (S 1 + h 1 × Δt ).
The output of the subtraction circuit 17 is compared with the value of the set value circuit 19 by the comparison circuit 10, and when the output exceeds a certain value, the output of the comparison circuit 20 is output. That is, the aforementioned S 2 − (S 1 + h 1 × Δ
When t) exceeds a certain value, a comparison output is output. The discharge in the first and second integrating circuits 9 and 10 is as follows.
This is performed by the rising detector 8 along the route of the inverted half-wave rectifier circuit 4.

【0015】全く同様に負極性のルートでも、反転半波
整流回路4、第1積分回路11、遅延回路6、レベル検
出器14、第2積分回路12、加算回路16、及び減算
回路18、比較回路21にて構成され、比較回路20,
21の出力の論理和22にて出力される。
Similarly, in the route of the negative polarity, the inverted half-wave rectifier circuit 4, the first integrating circuit 11, the delay circuit 6, the level detector 14, the second integrating circuit 12, the adding circuit 16, the subtracting circuit 18, A comparison circuit 20,
It is output as the logical sum 22 of the output of 21.

【0016】かかる、図1の構成にあって、図2にて作
用を示すに、図中のt1 は短絡事故点、t2 =t1 +Δ
t時間とする。本図を電圧の正電圧の半波整流回路3の
出力波形としてみると、時刻t1 までの面積S1 は第2
積分回路10の積分値であり、時刻t2 =t1 +Δtま
での面積S2 は第1積分回路9の積分値である。レベル
検出器13の出力値は図中のh1 ×Δt=h1 ×(t2
−t1 )である。また加算回路15の出力は、S1
(h1 ×Δt)となる。従って減算回路の出力値はS2
−[S1 +(h1 ×Δt)]すなわち図中の斜線部とな
る。この斜線部の面積が予め定められた整定値回路19
の値を越えると(トリップ)出力を外部に出力すること
になる。同様に本図を負電圧の反転半波整流回路4の出
力波形についてみても、まったく同様である。
In the configuration of FIG. 1, the operation is shown in FIG. 2. In FIG. 2, t 1 is a short-circuit fault point, and t 2 = t 1 + Δ.
Let it be t time. When this FIG viewed as a positive voltage output waveform of the half-wave rectifier circuit 3 of the voltage, the area S 1 until time t 1 second
The area S 2 up to the time t 2 = t 1 + Δt is the integrated value of the first integrating circuit 9. The output value of the level detector 13 is h 1 × Δt = h 1 × (t 2
−t 1 ). The output of the adder 15 is S 1 +
(H 1 × Δt). Therefore, the output value of the subtraction circuit is S 2
− [S 1 + (h 1 × Δt)], that is, the hatched portion in the figure. The setting value circuit 19 in which the area of the hatched portion is predetermined
When the value exceeds the value, a (trip) output is output to the outside. Similarly, this figure is completely the same when the output waveform of the inverting half-wave rectifier circuit 4 of the negative voltage is viewed in the figure.

【0017】以上のような構成により、短絡事故を最終
短絡電流近傍に至るまえにΔt時間で検出、決定するこ
とができる。図3、図4は他の実施例を示す。この図3
に示す例は、過電流領域の最大レベル×Δtと前記予め
定められた整定値回路の値において、予め定められた整
定値の値が明らかに大きい時、図3のように図1の回路
構成を簡素化するものである。
With the above configuration, it is possible to detect and determine a short circuit accident at time Δt before reaching the vicinity of the final short circuit current. 3 and 4 show another embodiment. This figure 3
In the example shown in FIG. 3, when the value of the predetermined set value is clearly larger between the maximum level of the overcurrent region × Δt and the value of the predetermined set value circuit, the circuit configuration of FIG. Is to simplify.

【0018】すなわち、図3では図1に示すレベル検出
器13,14と加算回路15,16とを省いた構成とな
っている。そして、動作としては、図4に示すように積
分回路9または11の積分値S2 と積分回路10または
12の積分値S1 の差(S2−S1 )すなわち図中の斜
線部の面積が、予め定められた整定値回路19の値を越
えると外部に出力をだす構成となっている。
That is, FIG. 3 has a configuration in which the level detectors 13 and 14 and the adders 15 and 16 shown in FIG. 1 are omitted. Then, as the operation, the area of the shaded portion of the integrating circuit 9 or the integrated value difference of the integral values S 1 of S 2 and the integrating circuit 10 or 12 of the 11 (S 2 -S 1) i.e. in the figure as shown in FIG. 4 However, when the value exceeds a predetermined value of the set value circuit 19, an output is output to the outside.

【0019】[0019]

【発明の効果】以上説明したように本発明によれば、図
5にも示すように短絡事故を、短絡電流近傍に電流が増
加する前に短絡事故を判定し、外部出力する保護継電器
を提供することができる。従って負荷や電路へのストレ
スを小さくでき、短絡事故時の損傷を最低限にすること
ができる。また電流の変化を積分値、面積で判断してい
るので、ノイズ、サージ等による誤動作を防止すること
もできる。
As described above, according to the present invention, as shown in FIG. 5, there is provided a protection relay for judging a short circuit accident before the current increases near the short circuit current and outputting the same to the outside. can do. Therefore, the stress on the load and the electric circuit can be reduced, and the damage in the event of a short circuit can be minimized. Further, since the change in the current is determined based on the integral value and the area, malfunction due to noise, surge, and the like can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す構成図である。FIG. 1 is a configuration diagram showing one embodiment of the present invention.

【図2】本発明の作用を説明する波形図である。FIG. 2 is a waveform diagram illustrating the operation of the present invention.

【図3】本発明の他の実施例を示す構成図である。FIG. 3 is a configuration diagram showing another embodiment of the present invention.

【図4】本発明の他の実施例の作用を説明する波形図で
ある。
FIG. 4 is a waveform diagram illustrating the operation of another embodiment of the present invention.

【図5】従来と本発明の短絡事故検出、判定方法の相異
を表す波形図である。
FIG. 5 is a waveform diagram showing a difference between a conventional method and a method for detecting and determining a short circuit accident according to the present invention.

【符号の説明】[Explanation of symbols]

1 整流器 2 I/V変換器 3,4 半波整流回路 5,6 遅延回路 7,8 立上り検出回路 9,11 第1積分回路 10,12 第2積分回路 13,14 レベル検出器 15,16 加算回路 17,18 減算回路 19 整定値回路 20,21 比較回路 DESCRIPTION OF SYMBOLS 1 Rectifier 2 I / V converter 3, 4 Half-wave rectifier circuit 5, 6 Delay circuit 7, 8 Rise detection circuit 9, 11 First integration circuit 10, 12 Second integration circuit 13, 14, Level detector 15, 16 Addition Circuits 17, 18 Subtraction circuit 19 Set value circuit 20, 21 Comparison circuit

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 負荷電流に比例した検出電圧の半波のみ
を整流する半波整流回路と、 この半波整流回路の出力を入力する第1積分回路及び遅
延回路と、 この遅延回路の出力を入力するレベル検出回路及び第2
積分回路と、 このレベル検出回路及び第2積分回路それぞれの出力を
加算する加算回路と、 この加算回路の出力と上記第1積分回路の出力との差を
求める減算回路と、 この減算回路出力と予め定められた値とを比較する比較
回路と、 を有する短絡事故高速判定回路。
1. A half-wave rectifier circuit for rectifying only a half-wave of a detection voltage proportional to a load current, a first integrating circuit and a delay circuit for receiving an output of the half-wave rectifier circuit, and an output of the delay circuit. Input level detection circuit and second level detection circuit
An integrating circuit; an adding circuit for adding outputs of the level detecting circuit and the second integrating circuit; a subtracting circuit for obtaining a difference between an output of the adding circuit and an output of the first integrating circuit; A comparison circuit for comparing a predetermined value with a predetermined value.
【請求項2】 負荷電流に比例した検出電圧の半波のみ
を整流する半波整流回路と、 この半波整流回路の出力を入力とする第1積分回路及び
遅延回路と、 この遅延回路出力を入力する第2積分回路と、 上記第1積分回路と第2積分回路との出力差を得る減算
回路と、 この減算回路出力と予め定められた値とを比較する比較
回路と、 を有する短絡事故高速判定回路。
2. A half-wave rectifier circuit for rectifying only a half-wave of a detection voltage proportional to a load current, a first integration circuit and a delay circuit which receive an output of the half-wave rectifier circuit, and an output of the delay circuit. A short circuit having: a second integration circuit to be input; a subtraction circuit for obtaining an output difference between the first integration circuit and the second integration circuit; and a comparison circuit for comparing the output of the subtraction circuit with a predetermined value. High-speed judgment circuit.
【請求項3】 負荷電流につき正負各極性二通りの回路
構成を有し、それぞれの比較回路出力の論理和を採り出
力を得る請求項1又は請求項2記載の短絡事故高速判定
回路。
3. The high-speed short-circuit fault judging circuit according to claim 1, which has a circuit configuration of positive and negative polarities with respect to the load current, and obtains an output by taking a logical sum of outputs of the respective comparison circuits.
JP30074293A 1993-12-01 1993-12-01 Short circuit accident high-speed judgment circuit Expired - Lifetime JP3207643B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30074293A JP3207643B2 (en) 1993-12-01 1993-12-01 Short circuit accident high-speed judgment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30074293A JP3207643B2 (en) 1993-12-01 1993-12-01 Short circuit accident high-speed judgment circuit

Publications (2)

Publication Number Publication Date
JPH07163042A JPH07163042A (en) 1995-06-23
JP3207643B2 true JP3207643B2 (en) 2001-09-10

Family

ID=17888559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30074293A Expired - Lifetime JP3207643B2 (en) 1993-12-01 1993-12-01 Short circuit accident high-speed judgment circuit

Country Status (1)

Country Link
JP (1) JP3207643B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200441685Y1 (en) * 2006-12-29 2008-09-01 엘에스산전 주식회사 Apparatus for protecting Air Circuit Breaker

Also Published As

Publication number Publication date
JPH07163042A (en) 1995-06-23

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