JP2536664B2 - Reset circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit, and more particularly to a reset circuit at power-on of a communication control device having peripheral input / output ports with a processor.

[Conventional technology]

FIG. 2 is a circuit diagram showing an example of a conventional reset circuit.

In the reset circuit of this example, the gate 4 receives the output of the charging / discharging circuit 100 including the resistor 1, the capacitor 3 and the diode 2, and the signal output until the threshold level of 4 is exceeded is used as the reset signal. .

[Problems to be Solved by the Invention]

Since the conventional reset circuit described above is only a charging / discharging circuit that includes a resistor and a capacitor, when the power supply rises and is in a normal operating state, the power supply voltage can be up to a certain value for a moment due to input power fluctuation or momentary interruption. When the voltage drops and returns to the normal power supply voltage value again, if the lowered voltage value is higher than the threshold level of the gate of the reset circuit and lower than the operation guarantee voltage of the IC or LSI, a reset signal is generated. Therefore, there is a drawback in that the operation of peripheral I / O port LSIs that require sequential mode setting may not be guaranteed and may result in abnormal operation.

[Means for solving the problem]

A reset circuit of the present invention is a communication control device having a processor and peripheral input / output ports, a one-shot circuit controlled by the processor to generate a reset signal, a reset signal of a charge / discharge circuit output, and the one-shot circuit. A gate for ORing an output with a reset signal, connecting one of the output ports to one of the input ports, the processor monitoring an output signal level to one of the output ports, and The one-shot circuit is driven when the level of the input signal to one of the input ports is different, and the input and output ports are initialized by the output signal of the theoretical sum gate.

〔Example〕

 Next, the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of the reset circuit of the present invention.

After the reset signal 21 at power-on is released, the processor 10 sets the mode of the peripheral output port 11 and the input port 12 via the address bus 14 and the data bus 15, and the decoder 13 in the normal communication control mode. The output port select signals 16 and 17 control the output of the output signal 18 and input the input signal 19. Where 1 of this output port 11
One output signal 8 is received as one of the inputs of the input port 12.

In this state, if the input power supply of this communication control device is momentarily cut off and the power supply voltage on the secondary side drops momentarily and then returns to the normal voltage, the voltage drop does not fall below the threshold level of the gate 4, and the reset signal 21 does not turn on, and the operation of the LSI and the like used for the peripheral output port 11 and input port 12 is not guaranteed due to the voltage drop.

Also, when the power supply voltage returns to normal, the processor 10
Controls the output signal 8 of the output port 11 to outputs "1" and "0", and the output is directly input to the processor 10 through the input port 12. The processor 10 determines whether or not the signal level of this signal input via the data bus 15 is the level set for the output signal 8, and if a normal signal level is not recognized, the one via the address bus 14 and the decoder 13 The trigger signal 9 is given to the shot circuit 5, the one shot circuit 5 generates the reset signal 6 under the control of the processor 10, and the output port 11 and the input port 12 are forcibly forced by the port reset signal 7 via the OR gate 20. Initialize and restart from mode setting to set the communication control mode.

〔The invention's effect〕

As described above, according to the present invention, the conventional reset circuit including the charge and discharge circuit of the resistor and the capacitor is ORed with the one-shot circuit controlled by the processor and the output of the reset signal output one-shot circuit by the charge and discharge circuit. It is equipped with a gate, and the output of one output port is input to the input port and the output signal level to that output port is monitored. When an unguaranteed situation occurs, it has the effect of immediately recovering from that situation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a reset circuit of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional reset circuit. 1 ... Resistance, 2 ... Diode, 3 ... Capacitor, 4
...... Gate, 5 ...... One-shot circuit, 7 ...... Port reset signal, 8 ...... One output signal of output port 11, 9
...... Trigger signal, 10 ... Processor, 11 ... Output port, 12 ... Input port, 13 ... Decoder, 14 ... Address bus, 15 ... Data bus, 20 ... OR gate.

Claims (2)

(57) [Claims] 1. A communication control device having a processor and peripheral input / output ports, a one-shot circuit controlled by the processor to generate a reset signal, a reset signal of a charge / discharge circuit output, and the one-shot circuit output. A gate for ORing with a reset signal, one of the output ports is connected to one of the input ports, and the processor monitors the output signal level to one of the output ports to monitor the input port. A reset circuit which drives the one-shot circuit when the input signal level to one of the two is different. 2. The input / output port is initialized by an output signal of the logical sum gate.
The reset circuit described.